//
// \brief This function confiugres the AINTC to receive UART interrupts.
//
void CPDMAAINTCConfigure(int usbInstance)
{
if(usbInstance)
{
IntProtectionDisable();
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_USBSSINT, USB1HostIntHandler);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_USBSSINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_USBSSINT);
IntProtectionEnable();
}
else
{
IntProtectionDisable();
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_USBSSINT, USB0HostIntHandler);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_USBSSINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_USBSSINT);
IntProtectionEnable();
}
}
void _EDMAAppRegisterEdma3Interrupts()
{
/* Enable IRQ in CPSR. */
IntMasterIRQEnable();
/* Intialize ARM interrupt controller */
IntAINTCInit();
/* Register Interrupts Here */
/******************** Completion Interrupt ********************************/
/* Registers Edma3ComplHandler0 Isr in Interrupt Vector Table of AINTC. */
IntRegister(SYS_INT_EDMACOMPINT , _EDMAAppEdma3ccComplIsr);
/* Set priority for system interrupt in AINTC */
IntPrioritySet(SYS_INT_EDMACOMPINT, 0u, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the EDMA CC0 system interrupt in AINTC.*/
IntSystemEnable(SYS_INT_EDMACOMPINT);
/********************** CC Error Interrupt ********************************/
/*
** Registers the EDMA3_0 Channel Controller 0 Error Interrupt Isr in the
** Interrupt Vector Table of AINTC.
*/
IntRegister(SYS_INT_EDMAERRINT , _EDMAAppEdma3ccErrIsr);
/* Set priority for system interrupt in AINTC */
IntPrioritySet(SYS_INT_EDMAERRINT, 0u, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the EDMA CCERR system interrupt AINTC.*/
IntSystemEnable(SYS_INT_EDMAERRINT);
}
/* Interrupt mapping to AINTC and registering McSPI ISR */
void McSPIAintcConfigure(unsigned char instance)
{
switch(instance)
{
case 0:
//IntProtectionDisable();
/* Register McSPIIsr interrupt handler */
IntRegister(SYS_INT_SPI0INT, McSPI0Isr);
/* Set Interrupt Priority */
IntPrioritySet(SYS_INT_SPI0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable system interrupt in AINTC */
IntSystemEnable(SYS_INT_SPI0INT);
//IntProtectionEnable();
break;
case 1:
//IntProtectionDisable();
/* Register McSPIIsr interrupt handler */
IntRegister(SYS_INT_SPI1INT, McSPI1Isr);
/* Set Interrupt Priority */
IntPrioritySet(SYS_INT_SPI1INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable system interrupt in AINTC */
IntSystemEnable(SYS_INT_SPI1INT);
//IntProtectionEnable();
break;
}
}
/*
** This function configures the AINTC to receive EDMA3 interrupts.
*/
static void EDMA3AINTCConfigure(void)
{
/* Initializing the ARM Interrupt Controller. */
IntAINTCInit();
/* Registering EDMA3 Channel Controller transfer completion interrupt. */
IntRegister(EDMA_COMPLTN_INT_NUM, Edma3CompletionIsr);
/* Setting the priority for EDMA3CC completion interrupt in AINTC. */
IntPrioritySet(EDMA_COMPLTN_INT_NUM, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Registering EDMA3 Channel Controller Error Interrupt. */
IntRegister(EDMA_ERROR_INT_NUM, Edma3CCErrorIsr);
/* Setting the priority for EDMA3CC Error interrupt in AINTC. */
IntPrioritySet(EDMA_ERROR_INT_NUM, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the EDMA3CC completion interrupt in AINTC. */
IntSystemEnable(EDMA_COMPLTN_INT_NUM);
/* Enabling the EDMA3CC Error interrupt in AINTC. */
IntSystemEnable(EDMA_ERROR_INT_NUM);
/* Registering HSMMC Interrupt handler */
IntRegister(MMCSD_INT_NUM, HSMMCSDIsr);
/* Setting the priority for EDMA3CC completion interrupt in AINTC. */
IntPrioritySet(MMCSD_INT_NUM, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the HSMMC interrupt in AINTC. */
IntSystemEnable(MMCSD_INT_NUM);
/* Enabling IRQ in CPSR of ARM processor. */
IntMasterIRQEnable();
}
/*
** configures arm interrupt controller to generate raster interrupt
*/
void SetupIntc(void)
{
#ifdef _TMS320C6X
IntDSPINTCInit();
IntRegister(C674X_MASK_INT4, LCDIsr);
IntEventMap(C674X_MASK_INT4, SYS_INT_LCDC_INT);
IntEnable(C674X_MASK_INT4);
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_LCDINT, LCDIsr);
/* Set the channnel number 2 of AINTC for LCD system interrupt.
*/
IntChannelSet(SYS_INT_LCDINT, 2);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_LCDINT);
IntSystemEnable(SYS_INT_I2CINT0);
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
static void USBAINTCConfigure(int usbInstance)
{
if(usbInstance)
{
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_USB1, USB1HostIntHandler);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_USB1, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_USB1);
}
else
{
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_USB0, USB0HostIntHandler);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_USB0, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_USB0);
}
}
/*
** Configures arm/dsp interrupt controller to generate frame interrupt
*/
static void SetupIntc(void)
{
#ifdef _TMS320C6X
/* Initialize the DSP interrupt controller */
IntDSPINTCInit();
/* Register VPIF ISR to vector table */
IntRegister(C674X_MASK_INT5, VPIFIsr);
/* Map system interrupt to DSP maskable interrupt for VPIF */
IntEventMap(C674X_MASK_INT5, SYS_INT_VPIF_INT);
/* Enable DSP maskable interrupt for VPIF */
IntEnable(C674X_MASK_INT5);
/* Register LCD ISR to vector table */
IntRegister(C674X_MASK_INT6, LCDIsr);
/* Map system interrupt to DSP maskable interrupt for LCD */
IntEventMap(C674X_MASK_INT6, SYS_INT_LCDC_INT);
/* Enable DSP maskable interrupt for LCD */
IntEnable(C674X_MASK_INT6);
/* Enable DSP interrupts */
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_VPIF, VPIFIsr);
/* Set the channel number 2 of AINTC for LCD system interrupt. */
IntChannelSet(SYS_INT_VPIF, 2);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_VPIF);
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_LCDINT, LCDIsr);
/* Set the channnel number 2 of AINTC for LCD system interrupt. */
IntChannelSet(SYS_INT_LCDINT, 3);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_LCDINT);
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
/* Configures AINTC to generate interrupt */
void I2CAINTCConfigure(new_twi* TwiStruct)
{
/* Intialize the ARM Interrupt Controller(AINTC) */
//IntAINTCInit();
switch (TwiStruct->TwiNr)
{
case 0:
IntProtectionDisable();
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_I2C1_IRQ, I2C0Isr);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_I2C1_IRQ, TwiStruct->Priority, AINTC_HOSTINT_ROUTE_IRQ );
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_I2C1_IRQ);
IntProtectionEnable();
break;
case 1:
IntProtectionDisable();
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_I2C2_IRQ, I2C1Isr);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_I2C2_IRQ, TwiStruct->Priority, AINTC_HOSTINT_ROUTE_IRQ );
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_I2C2_IRQ);
IntProtectionEnable();
break;
case 2:
IntProtectionDisable();
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_I2C3_IRQ, I2C2Isr);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_I2C3_IRQ, TwiStruct->Priority, AINTC_HOSTINT_ROUTE_IRQ );
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_I2C3_IRQ);
IntProtectionEnable();
break;
case 3:
IntProtectionDisable();
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_I2C4_IRQ, I2C3Isr);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_I2C4_IRQ, TwiStruct->Priority, AINTC_HOSTINT_ROUTE_IRQ );
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_I2C4_IRQ);
IntProtectionEnable();
break;
}
}
/*
** This function configures the AINTC to receive EDMA3 interrupts.
*/
static void ConfigureAINTCIntEDMA3(void)
{
IntRegister(SYS_INT_CCINT0, Edma3ComplHandlerIsr);
IntChannelSet(SYS_INT_CCINT0, 2);
IntSystemEnable(SYS_INT_CCINT0);
IntRegister(SYS_INT_CCERRINT, Edma3CCErrHandlerIsr);
IntChannelSet(SYS_INT_CCERRINT, 2);
IntSystemEnable(SYS_INT_CCERRINT);
}
/*
** RTC configuration function
*/
static void RTCSetupAndEnable(void)
{
/* Performing the System Clock configuration for RTC. */
RTCModuleClkConfig();
/* Disabling Write Protection for RTC registers.*/
RTCWriteProtectDisable(RTC_INST_BASE);
/* Selecting Internal Clock source for RTC. */
RTC32KClkSourceSelect(RTC_INST_BASE, RTC_INTERNAL_CLK_SRC_SELECT);
/* Enabling RTC to receive the Clock inputs. */
RTC32KClkClockControl(RTC_INST_BASE, RTC_32KCLK_ENABLE);
/* Enable the RTC module. */
RTCEnable(RTC_INST_BASE);
/* Dummy: Programming calendar information in the Calendar registers. */
RTCCalendarSet(RTC_INST_BASE, RTC_CAL_VAL_DUMMY);
/* Dummy: Programming the time information in the Time registers. */
RTCTimeSet(RTC_INST_BASE, RTC_TIME_VAL_DUMMY);
/* Set the 32KHz counter to run. */
RTCRun(RTC_INST_BASE);
/* Enabling RTC interrupts. Configuring RTC to interrupt every second.*/
RTCIntTimerEnable(RTC_INST_BASE, RTC_INT_EVERY_SECOND);
/* Enabling the system interrupt in AINTC for RTC. */
IntSystemEnable(RTC_INT_NUM);
}
/*
** RTC configuration function
*/
static void RTCSetupAndEnable(void)
{
/* Performing the System Clock configuration for RTC. */
RTCModuleClkConfig();
/* Disabling Write Protection for RTC registers.*/
RTCWriteProtectDisable(SOC_RTC_0_REGS);
/* Selecting Internal Clock source for RTC. */
RTC32KClkSourceSelect(SOC_RTC_0_REGS, RTC_INTERNAL_CLK_SRC_SELECT);
/* Enabling RTC to receive the Clock inputs. */
RTC32KClkClockControl(SOC_RTC_0_REGS, RTC_32KCLK_ENABLE);
/* Enable the RTC module. */
RTCEnable(SOC_RTC_0_REGS);
/* Dummy: Programming calendar information in the Calendar registers. */
RTCCalendarSet(SOC_RTC_0_REGS, 0x29111000 | RTC_DOTW_MON);
/* Dummy: Programming the time information in the Time registers. */
RTCTimeSet(SOC_RTC_0_REGS, (0x08473100 | RTC_ANTE_MERIDIEM));
/* Set the 32KHz counter to run. */
RTCRun(SOC_RTC_0_REGS);
/* Enabling RTC interrupts. Configuring RTC to interrupt every second.*/
RTCIntTimerEnable(SOC_RTC_0_REGS, RTC_INT_EVERY_SECOND);
/* Enabling the system interrupt in AINTC for RTC. */
IntSystemEnable(SYS_INT_RTCINT);
}
void SysDelayTimerSetup(void)
{
#ifdef DELAY_USE_INTERRUPTS
/* This function will enable clocks for the DMTimer7 instance */
DMTimer7ModuleClkConfig();
/* Registering DMTimerIsr */
IntRegister(SYS_INT_TINT7, DMTimerIsr);
/* Set the priority */
IntPrioritySet(SYS_INT_TINT7, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the system interrupt */
IntSystemEnable(SYS_INT_TINT7);
DMTimerCounterSet(SOC_DMTIMER_7_REGS, 0);
/* Configure the DMTimer for Auto-reload and compare mode */
DMTimerModeConfigure(SOC_DMTIMER_7_REGS, DMTIMER_ONESHOT_NOCMP_ENABLE);
#else
DMTimer7ModuleClkConfig();
DMTimerModeConfigure(SOC_DMTIMER_7_REGS, DMTIMER_ONESHOT_NOCMP_ENABLE);
#endif
}
/*
** configures arm interrupt controller to generate PWM interrupts
*/
static void SetupIntc(void)
{
#ifdef _TMS320C6X
// Initialize the DSP interrupt controller
IntDSPINTCInit();
// Register the ISRs to the vector table
IntRegister(C674X_MASK_INT4, PWMEventIsr);
IntRegister(C674X_MASK_INT5, PWMTZIsr);
// Map system events to the DSP maskable interrupts
IntEventMap(C674X_MASK_INT4, SYS_INT_EHRPWM1);
IntEventMap(C674X_MASK_INT5, SYS_INT_EHRPWM1TZ);
// Enable the DSP maskable interrupts
IntEnable(C674X_MASK_INT4);
IntEnable(C674X_MASK_INT5);
// Enable DSP interrupts globally
IntGlobalEnable();
#else
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
IntSystemStatusClear(SYS_INT_EHRPWM1);
EHRPWMETIntClear(SOC_EHRPWM_1_REGS);
/************************PWM1****************************************/
IntRegister(SYS_INT_EHRPWM1, PWMEventIsr);
IntChannelSet(SYS_INT_EHRPWM1, 2);
IntSystemEnable(SYS_INT_EHRPWM1);
/********************************************************************/
IntRegister(SYS_INT_EHRPWM1TZ, PWMTZIsr);
IntChannelSet(SYS_INT_EHRPWM1TZ, 2);
IntSystemEnable(SYS_INT_EHRPWM1TZ);
/********************************************************************/
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Enable the interrupts in GER of AINTC.*/
IntGlobalEnable();
/* Enable the interrupts in HIER of AINTC.*/
IntIRQEnable();
#endif
}
/*
** Registers Touch Screen Interrupt
*/
void TouchIntRegister(void)
{
IntRegister(SYS_INT_ADC_TSC_GENINT, TouchScreenIsr);
IntPrioritySet(SYS_INT_ADC_TSC_GENINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_ADC_TSC_GENINT);
}
/*
** Set up the ARM Interrupt Controller for generating timer interrupt
*/
void AintcCPSWIntrSetUp(void)
{
IntProtectionDisable();
/* Register the Receive ISR for Core 0 */
IntRegister(SYS_INT_3PGSWRXINT0, CPSWCore0RxIsr);
/* Register the Transmit ISR for Core 0 */
IntRegister(SYS_INT_3PGSWTXINT0, CPSWCore0TxIsr);
/* Set the priority */
IntPrioritySet(SYS_INT_3PGSWTXINT0, 1, AINTC_HOSTINT_ROUTE_IRQ);
IntPrioritySet(SYS_INT_3PGSWRXINT0, 1, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the system interrupt */
IntSystemEnable(SYS_INT_3PGSWTXINT0);
IntSystemEnable(SYS_INT_3PGSWRXINT0);
IntProtectionEnable();
}
/*
** Sets up the interrupts for EDMA in AINTC
*/
static void EDMA3IntSetup(void)
{
IntRegister(EDMA_COMPLTN_INT_NUM, EDMA3CCComplIsr);
IntPrioritySet(EDMA_COMPLTN_INT_NUM, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(EDMA_COMPLTN_INT_NUM);
}
/*
** configures arm interrupt controller to generate raster interrupt
*/
static void LCDAINTCConfigure(void)
{
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_LCDCINT, LCDIsr);
IntPrioritySet(SYS_INT_LCDCINT, 0, AINTC_HOSTINT_ROUTE_IRQ );
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_LCDCINT);
}
void ConfigureAINTCIntI2C(void)
{
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(SYS_INT_I2CINT0, I2CIsr);
IntChannelSet(SYS_INT_I2CINT0, 3);
/* Enable the System Interrupts for AINTC.*/
IntSystemEnable(SYS_INT_I2CINT0);
}
/*
** Sets up the interrupts for McASP in AINTC
*/
static void McASPIntSetup(void)
{
IntRegister(MCASP_TX_INT, McASPTxIsr);
IntPrioritySet(MCASP_TX_INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(MCASP_TX_INT);
}
/*
** Registers the Timer2 ISR.
*/
void Timer2IntRegister(void)
{
IntRegister(SYS_INT_TINT2, Timer2Isr);
/* Set the priority */
IntPrioritySet(SYS_INT_TINT2, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the system interrupt */
IntSystemEnable(SYS_INT_TINT2);
}
/*
**Configure AINTC for enabling RTC alarm interrupt
*/
void RTCAlarmAINTCConfigure(void)
{
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_RTCALARMINT, RTCAlarmIsr);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_RTCALARMINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_RTCALARMINT);
}
static void LCDAINTCConfigure(void)
{
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_LCDCINT, LCDIsr);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_LCDCINT, 1, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_LCDCINT);
}
/*
** Registers the Timer6 ISR.
*/
void Timer6IntRegister(void)
{
/* Register timer 6 ISR */
IntRegister(SYS_INT_TINT6, Timer6Isr);
/* Set the priority */
IntPrioritySet(SYS_INT_TINT6, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enable the system interrupt */
IntSystemEnable(SYS_INT_TINT6);
}
/******************************************************************************
* *
* \brief This function Configure the AINTC controller for UART.\n *
* *
* \param none *
* *
* \return none. *
* *
******************************************************************************/
static void UARTAINTCConfigure(void)
{
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_UART0INT, USBUARTIntHandler);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_UART0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_UART0INT);
}
/*
** Sets up the interrupts for EDMA in AINTC
*/
static void EDMA3IntSetup(void)
{
#ifdef _TMS320C6X
IntRegister(C674X_MASK_INT5, EDMA3CCComplIsr);
IntEventMap(C674X_MASK_INT5, SYS_INT_EDMA3_0_CC0_INT1);
IntEnable(C674X_MASK_INT5);
#else
IntRegister(SYS_INT_CCINT0, EDMA3CCComplIsr);
IntChannelSet(SYS_INT_CCINT0, INT_CHANNEL_EDMACC);
IntSystemEnable(SYS_INT_CCINT0);
#endif
}
/*
** Sets up the I2C interrupt in the AINTC
*/
static void I2CCodecIntSetup(unsigned int sysIntNum, unsigned int channel)
{
#ifdef _TMS320C6X
IntRegister(C674X_MASK_INT4, I2CCodecIsr);
IntEventMap(C674X_MASK_INT4, sysIntNum);
IntEnable(C674X_MASK_INT4);
#else
/* Register the ISR in the Interrupt Vector Table.*/
IntRegister(sysIntNum, I2CCodecIsr);
IntChannelSet(sysIntNum, channel);
IntSystemEnable(sysIntNum);
#endif
}
/*
** Sets up the error interrupts for McASP in AINTC
*/
static void McASPErrorIntSetup(void)
{
#ifdef _TMS320C6X
IntRegister(C674X_MASK_INT6, McASPErrorIsr);
IntEventMap(C674X_MASK_INT6, SYS_INT_MCASP0_INT);
IntEnable(C674X_MASK_INT6);
#else
/* Register the error ISR for McASP */
IntRegister(SYS_INT_MCASPINT, McASPErrorIsr);
IntChannelSet(SYS_INT_MCASPINT, INT_CHANNEL_MCASP);
IntSystemEnable(SYS_INT_MCASPINT);
#endif
}
static void SetupIntc(void)
{
/* Enable IRQ in CPSR.*/
IntMasterIRQEnable();
/* Initialize the ARM Interrupt Controller.*/
IntAINTCInit();
IntRegister(SYS_INT_ADC_TSC_GENINT, ADCIsr);
IntPrioritySet(SYS_INT_ADC_TSC_GENINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
IntSystemEnable(SYS_INT_ADC_TSC_GENINT);
}
/*
** This function configures the AINTC to receive EDMA3 interrupts.
*/
static void EDMA3INTCConfigure(void)
{
/* Initializing the ARM Interrupt Controller. */
IntAINTCInit();
/* Registering EDMA3 Channel Controller 0 transfer completion interrupt. */
IntRegister(SYS_INT_EDMACOMPINT, Edma3CompletionIsr);
/* Setting the priority for EDMA3CC0 completion interrupt in AINTC. */
IntPrioritySet(SYS_INT_EDMACOMPINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Registering EDMA3 Channel Controller 0 Error Interrupt. */
IntRegister(SYS_INT_EDMAERRINT, Edma3CCErrorIsr);
/* Setting the priority for EDMA3CC0 Error interrupt in AINTC. */
IntPrioritySet(SYS_INT_EDMAERRINT, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the EDMA3CC0 completion interrupt in AINTC. */
IntSystemEnable(SYS_INT_EDMACOMPINT);
/* Enabling the EDMA3CC0 Error interrupt in AINTC. */
IntSystemEnable(SYS_INT_EDMAERRINT);
}
/*
** This function configures the AINTC to receive UART interrupts.
*/
static void UART0AINTCConfigure(void)
{
/* Initializing the ARM Interrupt Controller. */
IntAINTCInit();
/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_UART0INT, UARTIsr);
/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_UART0INT, 0, AINTC_HOSTINT_ROUTE_IRQ);
/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_UART0INT);
}
