/**
* Output Test Point function .
*
* @param[in,out] StdHeader The Pointer of Standard Header.
*
* @retval AGESA_SUCCESS Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
* @retval AGESA_ERROR Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
*
**/
AGESA_STATUS
IdsPerfAnalyseTimestamp (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS status;
LOCATE_HEAP_PTR LocateHeapStructPtr;
UINT32 TscRateInMhz;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
IDS_CALLOUT_STRUCT IdsCalloutData;
AGESA_STATUS Status;
PERFREGBACKUP PerfReg;
UINT32 CR4reg;
UINT64 SMsr;
LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
LocateHeapStructPtr.BufferPtr = NULL;
status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
if (status != AGESA_SUCCESS) {
return status;
}
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz;
((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->Version = IDS_PERF_VERSION;
IdsCalloutData.IdsNvPtr = NULL;
IdsCalloutData.StdHeader = *StdHeader;
IdsCalloutData.Reserved = 0;
Status = AgesaGetIdsData (IDS_CALLOUT_GET_PERF_BUFFER, &IdsCalloutData);
//Check if Platform BIOS provide a buffer to copy
if ((Status == AGESA_SUCCESS) && (IdsCalloutData.Reserved != 0)) {
LibAmdMemCopy ((VOID *)IdsCalloutData.Reserved, LocateHeapStructPtr.BufferPtr, sizeof (TP_Perf_STRUCT), StdHeader);
} else {
//No platform performance buffer provide, use the default HDTOUT output
if (AmdIdsHdtOutSupport () == FALSE) {
//Init break point
IdsPerfSaveReg (&PerfReg, StdHeader);
LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, StdHeader);
SMsr |= 1;
LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, StdHeader);
LibAmdWriteCpuReg (DR2_REG, 0x99cc);
LibAmdWriteCpuReg (DR7_REG, 0x02000420);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
IdsPerfHdtOut (1, (UINT32) (UINT64) LocateHeapStructPtr.BufferPtr, StdHeader);
IdsPerfRestoreReg (&PerfReg, StdHeader);
}
}
return status;
}
STATIC VOID
IdsPerfRestoreReg (
IN PERFREGBACKUP * perfreg,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdMsrWrite (0xC001100A, &perfreg->SMsr, StdHeader);
LibAmdWriteCpuReg (DR0_REG, perfreg->Dr0Reg);
LibAmdWriteCpuReg (DR7_REG, perfreg->Dr7Reg);
LibAmdWriteCpuReg (CR4_REG, perfreg->Cr4Reg);
}
/**
*
* Restore register setting used for HDT out Function.
*
*
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
VOID
AmdIdsHdtOutRegisterInit (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CR4reg;
UINT64 SMsr;
SMsr |= 1;
LibAmdWriteCpuReg (DR2_REG, 0x99CC);
LibAmdWriteCpuReg (DR7_REG, 0x02000420);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
}
/**
*
* Initial register setting used for HDT out Function.
*
*
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
VOID
AmdIdsHdtOutRegisterRestore (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CR4reg;
UINT64 SMsr;
SMsr &= ~BIT0;
LibAmdWriteCpuReg (DR2_REG, 0);
LibAmdWriteCpuReg (DR3_REG, 0);
LibAmdWriteCpuReg (DR7_REG, 0);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg & (~BIT3));
}
/**
*
* Initial register setting used for HDT out Function.
*
*
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
STATIC VOID
AmdIdsHdtOutRegisterRestore (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 CR4reg;
UINT64 SMsr;
LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, StdHeader);
SMsr &= ~BIT0;
LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, StdHeader);
LibAmdWriteCpuReg (DR2_REG, 0);
LibAmdWriteCpuReg (DR3_REG, 0);
LibAmdWriteCpuReg (DR7_REG, 0);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg & (~BIT3));
}
/**
* Output Test Point function .
*
* @param[in,out] StdHeader The Pointer of Standard Header.
*
* @retval AGESA_SUCCESS Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
* @retval AGESA_ERROR Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE.
*
**/
AGESA_STATUS
IdsPerfAnalyseTimestamp (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS status;
LOCATE_HEAP_PTR LocateHeapStructPtr;
UINT32 TscRateInMhz;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
PERFREGBACKUP PerfReg;
UINT32 CR4reg;
UINT64 SMsr;
LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE;
LocateHeapStructPtr.BufferPtr = NULL;
status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader);
if (status != AGESA_SUCCESS) {
return status;
}
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader);
((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz;
//Init break point
IdsPerfSaveReg (&PerfReg, StdHeader);
LibAmdMsrRead (0xC001100A, (UINT64 *)&SMsr, StdHeader);
SMsr |= 1;
LibAmdMsrWrite (0xC001100A, (UINT64 *)&SMsr, StdHeader);
LibAmdWriteCpuReg (DR0_REG, 0x8899);
LibAmdWriteCpuReg (DR7_REG, 0x00020402);
LibAmdReadCpuReg (CR4_REG, &CR4reg);
LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3));
IdsPerfHdtOut (1, (UINT32) LocateHeapStructPtr.BufferPtr, StdHeader);
IdsPerfRestoreReg (&PerfReg, StdHeader);
return status;
}
VOID
MemRecTEndTraining (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
S_UINT64 SMsr;
MEM_DATA_STRUCT *MemPtr;
MEM_NB_BLOCK *NBPtr;
NBPtr = TechPtr->NBPtr;
MemPtr = NBPtr->MemPtr;
LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg);
LibAmdMsrRead (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
SMsr.lo = TechPtr->HwcrLo;
LibAmdMsrWrite (HWCR, (UINT64 *)&SMsr, &MemPtr->StdHeader);
}
/**
*
* Enable all the caches on current core.
*
* @param[in] ApExeParams Handle to config for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
EnableAllCaches (
IN AP_EXE_PARAMS *ApExeParams
)
{
UINT32 CR0Data;
L3_FEATURE_FAMILY_SERVICES *FamilyServices;
// Enable cache through CR0.
LibAmdReadCpuReg (0, &CR0Data);
CR0Data &= ~(0x60000000);
LibAmdWriteCpuReg (0, CR0Data);
GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (const VOID **) &FamilyServices, &ApExeParams->StdHeader);
FamilyServices->HookEnableCache (FamilyServices, &ApExeParams->StdHeader);
return AGESA_SUCCESS;
}
VOID
MemRecTBeginTraining (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
S_UINT64 SMsr;
MEM_DATA_STRUCT *MemPtr;
MEM_NB_BLOCK *NBPtr;
NBPtr = TechPtr->NBPtr;
MemPtr = NBPtr->MemPtr;
LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg);
LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32) 1 << 9)); // enable SSE2
LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); // HWCR
TechPtr->HwcrLo = SMsr.lo;
SMsr.lo |= 0x00020000; // turn on HWCR.wrap32dis
SMsr.lo &= 0xFFFF7FFF; // turn off HWCR.SSEDIS
LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
}
/**
*
* Disable all the caches on current core.
*
* @param[in] ApExeParams Handle to config for library and services.
*
* @retval AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
DisableAllCaches (
IN AP_EXE_PARAMS *ApExeParams
)
{
UINT32 CR0Data;
L3_FEATURE_FAMILY_SERVICES *FamilyServices;
// Disable cache through CR0.
LibAmdReadCpuReg (0, &CR0Data);
CR0Data |= (0x60000000);
LibAmdWriteCpuReg (0, CR0Data);
// Execute wbinvd
LibAmdWriteBackInvalidateCache ();
GetFeatureServicesOfCurrentCore (&L3FeatureFamilyServiceTable, (const VOID **) &FamilyServices, &ApExeParams->StdHeader);
FamilyServices->HookDisableCache (FamilyServices, *(BOOLEAN *) ApExeParams->RelatedDataBlock, &ApExeParams->StdHeader);
return AGESA_SUCCESS;
}
/**
*
* Initial function for HDT out Function.
*
* Init required Debug register & heap, and will also fire a HDTOUT
* Command to let hdtout script do corresponding things.
*
* @param[in,out] StdHeader The Pointer of AGESA Header
*
**/
VOID
AmdIdsHdtOutInit (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
ALLOCATE_HEAP_PARAMS AllocHeapParams;
HDTOUT_HEADER HdtoutHeader;
UINT8 Persist;
AGESA_STATUS IgnoreSts;
HDTOUT_HEADER *pHdtoutHeader;
IDS_FUNCLIST_EXTERN ();
if (AmdIdsHdtOutSupport ()) {
AmdIdsHdtOutRegisterInit (StdHeader);
// Initialize HDTOUT Header
HdtoutHeader.Signature = HDTOUT_HEADER_SIGNATURE;
HdtoutHeader.Version = HDTOUT_VERSION;
HdtoutHeader.BufferSize = HDTOUT_DEFAULT_BUFFER_SIZE;
HdtoutHeader.DataIndex = 0;
HdtoutHeader.PrintCtrl = HDTOUT_PRINTCTRL_ON;
HdtoutHeader.NumBreakpointUnit = 0;
HdtoutHeader.FuncListAddr = (UINTN)IDS_FUNCLIST_ADDR;
HdtoutHeader.StatusStr[0] = 0;
HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_ON;
HdtoutHeader.EnableMask = 0;
HdtoutHeader.ConsoleFilter = IDS_DEBUG_PRINT_MASK;
// Trigger HDTOUT breakpoint to get inputs from script
IdsOutPort (HDTOUT_INIT, (UINTN) &HdtoutHeader, 0);
// Disable AP HDTOUT if set BspOnlyFlag
if (HdtoutHeader.BspOnlyFlag == HDTOUT_BSP_ONLY) {
if (!IsBsp (StdHeader, &IgnoreSts)) {
AmdIdsHdtOutRegisterRestore (StdHeader);
return;
}
}
// Convert legacy EnableMask to new ConsoleFilter
HdtoutHeader.ConsoleFilter |= HdtoutHeader.EnableMask;
// Disable the buffer if the size is not large enough
if (HdtoutHeader.BufferSize < 128) {
HdtoutHeader.BufferSize = 0;
HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_OFF;
} else {
HdtoutHeader.OutBufferMode = HDTOUT_BUFFER_MODE_ON;
}
// Check if Hdtout header have been initialed, if so it must 2nd time come here
if (AmdIdsHdtoutGetHeader (&pHdtoutHeader, StdHeader)) {
Persist = HEAP_SYSTEM_MEM;
} else {
Persist = HEAP_LOCAL_CACHE;
}
// Allocate heap
do {
AllocHeapParams.RequestedBufferSize = HdtoutHeader.BufferSize + sizeof (HdtoutHeader) - 2;
AllocHeapParams.BufferHandle = IDS_HDT_OUT_BUFFER_HANDLE;
AllocHeapParams.Persist = Persist;
if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
break;
} else {
IdsOutPort (HDTOUT_ERROR, HDTOUT_ERROR_HEAP_ALLOCATION, AllocHeapParams.RequestedBufferSize);
HdtoutHeader.BufferSize -= 256;
}
} while ((HdtoutHeader.BufferSize & 0x8000) == 0);
// If the buffer have been successfully allocated?
if ((HdtoutHeader.BufferSize & 0x8000) == 0) {
LibAmdWriteCpuReg (DR3_REG, (UINTN)AllocHeapParams.BufferPtr);
LibAmdMemCopy (AllocHeapParams.BufferPtr, &HdtoutHeader, sizeof (HdtoutHeader) - 2, StdHeader);
} else {
/// Clear DR3_REG
IdsOutPort ((UINT32)HDTOUT_ERROR, (UINT32)HDTOUT_ERROR_HEAP_AllOCATE_FAIL, (UINT32)IDS_DEBUG_PRINT_MASK);
LibAmdWriteCpuReg (DR3_REG, 0);
}
}
}
