void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
{
uint32_t u32sel = 0, u32div = 0;
uint32_t u32SelTbl[4] = {0x0, 0x4, 0xC, 0x24};
if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
{
/* Get clock divider control register address */
u32div = (uint32_t)&CLK->CLKDIV + ((MODULE_CLKDIV(u32ModuleIdx)) * 4);
/* Apply new divider */
M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
}
if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
{
/* Get clock select control register address */
u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
/* Set new clock selection setting */
M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
}
}
/***********************************************************************
*
* Function: board_nor_verify
*
* Purpose: Verify Flash Contents
*
* Processing:
* See function.
*
* Parameters:
* adr: Start Address
* buf: Write Buffer Address
* sz: Write Size
*
* Outputs: None
*
* Returns: 0 - OK, 1 - Failed
*
* Notes: None
*
**********************************************************************/
UNS_32 board_nor_verify(UNS_32 adr, UNS_8 *buf, UNS_32 sz )
{
UNS_32 i;
for (i = 0; i < ((sz+3)/4); i++)
{
if (M32(adr) != *((UNS_32 *)buf))
return (1);
buf += 4;
adr += 4;
}
return (0);
}
int Polling (unsigned long adr) {
unsigned int q6l, q6h;
fsr.v = M32(adr);
q6l = fsr.b.q6l;
q6h = fsr.b.q6h;
do {
fsr.v = M32(adr);
if ((fsr.b.q6l == q6l) && (fsr.b.q6h == q6h)) {
return (0); // Done
}
q6l = fsr.b.q6l;
q6h = fsr.b.q6h;
} while ((fsr.b.q5l == 0) || (fsr.b.q5h == 0)); // Check for Timeout
fsr.v = M32(adr);
q6l = fsr.b.q6l;
q6h = fsr.b.q6h;
fsr.v = M32(adr);
if ((fsr.b.q6l == q6l) && (fsr.b.q6h == q6h)) {
return (0); // Done
}
M32(adr) = 0x00F000F0; // Reset Device
return (1); // Failed
}
unsigned long Verify (unsigned long adr, unsigned long sz, unsigned char *buf) {
unsigned long i, adr_dest;
adr_dest = adr;
if (adr < EXT_NOR)
adr_dest = (adr - EXT_SDRAM) + EXT_NOR + BOOT_SIZE;
for (i = 0; i < ((sz+3)/4); i++) {
if (M32(adr_dest) != *((unsigned long *)buf)) return (adr);
buf += 4;
adr += 4;
adr_dest += 4;
}
return (adr);
}
void
DOMMatrixReadOnly::Stringify(nsAString& aResult)
{
nsAutoString matrixStr;
if (mMatrix3D) {
matrixStr.AppendPrintf("matrix3d(%g, %g, %g, %g, %g, %g, %g, %g, %g, %g, %g, %g, %g, %g, %g, %g)",
M11(), M12(), M13(), M14(),
M21(), M22(), M23(), M24(),
M31(), M32(), M33(), M34(),
M41(), M42(), M43(), M44());
} else {
matrixStr.AppendPrintf("matrix(%g, %g, %g, %g, %g, %g)", A(), B(), C(), D(), E(), F());
}
aResult = matrixStr;
}
int EraseChip (void) {
// Start Chip Erase Command
M32(base_adr + (0x555 << 2)) = 0x00AA00AA;
M32(base_adr + (0x2AA << 2)) = 0x00550055;
M32(base_adr + (0x555 << 2)) = 0x00800080;
M32(base_adr + (0x555 << 2)) = 0x00AA00AA;
M32(base_adr + (0x2AA << 2)) = 0x00550055;
M32(base_adr + (0x555 << 2)) = 0x00100010;
return (Polling(base_adr)); // Wait until Erase completed
}
/***********************************************************************
*
* Function: board_nor_erase_chip
*
* Purpose: Erase whole NOR chip.
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: 0 - OK, 1 - Failed
*
* Notes: None
*
**********************************************************************/
INT_32 board_nor_erase_chip(void)
{
/* Start Chip Erase Command */
M32(base_adr + (0x555 << 2)) = 0x00AA00AA;
M32(base_adr + (0x2AA << 2)) = 0x00550055;
M32(base_adr + (0x555 << 2)) = 0x00800080;
M32(base_adr + (0x555 << 2)) = 0x00AA00AA;
M32(base_adr + (0x2AA << 2)) = 0x00550055;
M32(base_adr + (0x555 << 2)) = 0x00100010;
/* Wait until Erase completed */
return (board_not_polling(base_adr));
}
/***********************************************************************
*
* Function: board_nor_erase_sector
*
* Purpose: Erase Sector in Flash Memory
*
* Processing:
* See function.
*
* Parameters:
* adr: Sector Address
*
* Outputs: None
*
* Returns: 0 - OK, 1 - Failed
*
* Notes: None
*
**********************************************************************/
INT_32 board_nor_erase_sector(UNS_32 adr)
{
/* Start Erase Sector Command */
M32(base_adr + (0x555 << 2)) = 0x00AA00AA;
M32(base_adr + (0x2AA << 2)) = 0x00550055;
M32(base_adr + (0x555 << 2)) = 0x00800080;
M32(base_adr + (0x555 << 2)) = 0x00AA00AA;
M32(base_adr + (0x2AA << 2)) = 0x00550055;
M32(adr) = 0x00300030;
/* Wait for Sector Erase Timeout */
do {
fsr.v = M32(adr);
} while ((fsr.b.q3l == 0) || (fsr.b.q3h == 0));
/* Wait until Erase completed */
return (board_not_polling(adr));
}
int fs_EraseSector (U32 adr) {
U32 fsreg;
M32(base_adr | (0xAAA << 1)) = 0x00AA00AA;
M32(base_adr | (0x554 << 1)) = 0x00550055;
M32(base_adr | (0xAAA << 1)) = ERASE;
M32(base_adr | (0xAAA << 1)) = 0x00AA00AA;
M32(base_adr | (0x554 << 1)) = 0x00550055;
M32(adr) = ERA_SECT;
/* Wait for Sector Erase Timeout. */
do {
fsreg = M32(adr);
} while ((fsreg & DQ3) < DQ3);
/* Wait until Erase Completed */
return (Q6Polling (adr));
} /* end of fs_EraseSector */
int EraseSector (unsigned long adr) {
if (adr < EXT_NOR)
adr = (adr - EXT_SDRAM) + EXT_NOR + BOOT_SIZE;
// Start Erase Sector Command
M32(base_adr + (0x555 << 2)) = 0x00AA00AA;
M32(base_adr + (0x2AA << 2)) = 0x00550055;
M32(base_adr + (0x555 << 2)) = 0x00800080;
M32(base_adr + (0x555 << 2)) = 0x00AA00AA;
M32(base_adr + (0x2AA << 2)) = 0x00550055;
M32(adr) = 0x00300030;
do { // Wait for Sector Erase Timeout
fsr.v = M32(adr);
} while ((fsr.b.q3l == 0) || (fsr.b.q3h == 0));
return (Polling(adr)); // Wait until Erase completed
}
void
DOMMatrixReadOnly::Stringify(nsAString& aResult)
{
nsAutoString matrixStr;
if (mMatrix3D) {
// We can't use AppendPrintf here, because it does locale-specific
// formatting of floating-point values.
matrixStr.AssignLiteral("matrix3d(");
AppendFloat(matrixStr, M11()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M12()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M13()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M14()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M21()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M22()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M23()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M24()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M31()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M32()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M33()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M34()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M41()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M42()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M43()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, M44());
matrixStr.AppendLiteral(")");
} else {
// We can't use AppendPrintf here, because it does locale-specific
// formatting of floating-point values.
matrixStr.AssignLiteral("matrix(");
AppendFloat(matrixStr, A()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, B()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, C()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, D()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, E()); matrixStr.AppendLiteral(", ");
AppendFloat(matrixStr, F());
matrixStr.AppendLiteral(")");
}
aResult = matrixStr;
}
/*****************************************************************************
* x264_macroblock_analyse:
*****************************************************************************/
void dull_macroblock_analyse_P_SKIP( x264_t *h )
{
x264_mb_analysis_t analysis;
int i;
dull_mb_analyse_init_P( h, &analysis );
/*--------------------------- Do the analysis ---------------------------*/
assert ( h->sh.i_type == SLICE_TYPE_P );
//{ macroblock_analyse_P //{ macroblock_analyse_P //{ macroblock_analyse_P //{ macroblock_analyse_P
{
h->mb.i_type = P_SKIP;
h->mb.i_partition = D_16x16;
assert( h->mb.cache.pskip_mv[1] <= h->mb.mv_max_spel[1] || h->i_thread_frames == 1 );
/* Set up MVs for future predictors */
for( i = 0; i < h->mb.pic.i_fref[0]; i++ )
M32( h->mb.mvr[0][i][h->mb.i_mb_xy] ) = 0;
}
//} macroblock_analyse_P //} macroblock_analyse_P //} macroblock_analyse_P //} macroblock_analyse_P
dull_analyse_update_cache_P( h, &analysis );
}
static int read_frame_internal( cli_pic_t *pic, y4m_hnd_t *h )
{
size_t slen = strlen( Y4M_FRAME_MAGIC );
int pixel_depth = x264_cli_csp_depth_factor( pic->img.csp );
int i = 0;
char header[16];
/* Read frame header - without terminating '\n' */
if( fread( header, 1, slen, h->fh ) != slen )
return -1;
header[slen] = 0;
FAIL_IF_ERROR( strncmp( header, Y4M_FRAME_MAGIC, slen ), "bad header magic (%"PRIx32" <=> %s)\n",
M32(header), header )
/* Skip most of it */
while( i < MAX_FRAME_HEADER && fgetc( h->fh ) != '\n' )
i++;
FAIL_IF_ERROR( i == MAX_FRAME_HEADER, "bad frame header!\n" )
h->frame_size = h->frame_size - h->frame_header_len + i+slen+1;
h->frame_header_len = i+slen+1;
int error = 0;
for( i = 0; i < pic->img.planes && !error; i++ )
{
error |= fread( pic->img.plane[i], pixel_depth, h->plane_size[i], h->fh ) != h->plane_size[i];
if( h->bit_depth & 7 )
{
/* upconvert non 16bit high depth planes to 16bit using the same
* algorithm as used in the depth filter. */
uint16_t *plane = (uint16_t*)pic->img.plane[i];
uint64_t pixel_count = h->plane_size[i];
int lshift = 16 - h->bit_depth;
for( uint64_t j = 0; j < pixel_count; j++ )
plane[j] = plane[j] << lshift;
}
}
return error;
}
static int read_frame_internal( cli_pic_t *pic, y4m_hnd_t *h )
{
size_t slen = strlen( Y4M_FRAME_MAGIC );
int i = 0;
char header[16];
/* Read frame header - without terminating '\n' */
if( fread( header, 1, slen, h->fh ) != slen )
return -1;
header[slen] = 0;
FAIL_IF_ERROR( strncmp( header, Y4M_FRAME_MAGIC, slen ), "bad header magic (%"PRIx32" <=> %s)\n",
M32(header), header )
/* Skip most of it */
while( i < MAX_FRAME_HEADER && fgetc( h->fh ) != '\n' )
i++;
FAIL_IF_ERROR( i == MAX_FRAME_HEADER, "bad frame header!\n" )
h->frame_size = h->frame_size - h->frame_header_len + i+slen+1;
h->frame_header_len = i+slen+1;
return read_picture_with_correct_bit_depth( pic, h->handler );
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
uint32_t u32data;
/* In end of main function, program issued CPU reset and write-protection will be disabled. */
if(SYS_IsRegLocked() == 0)
SYS_LockReg();
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
/*
This sample code will show some function about system manager controller and clock controller:
1. Read PDID
2. Get and clear reset source
3. Setting about BOD
4. Change system clock depended on different PLL settings
5. Output system clock from CKO pin, and the output frequency = system clock / 4
*/
printf("+--------------------------------------------+\n");
printf("| NUC029xEE System Driver Sample Code |\n");
printf("+--------------------------------------------+\n");
if(M32(FLAG_ADDR) == SIGNATURE) {
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = 0;
printf(" Press any key to continue ...\n");
getchar();
}
/*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/
/* Read Part Device ID */
printf("Product ID 0x%x\n", SYS_ReadPDID());
/* Get reset source from last operation */
u32data = SYS_GetResetSrc();
printf("Reset Source 0x%x\n", u32data);
/* Clear reset source */
SYS_ClearResetSrc(u32data);
/* Unlock protected registers for Brown-Out Detector settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if(SYS_IsRegLocked() == 0) {
printf("Protected Address is Unlocked\n");
}
/* Enable Brown-Out Detector, and set Brown-Out Detector voltage 2.7V */
SYS_EnableBOD(SYS_BODCR_BOD_INTERRUPT_EN, SYS_BODCR_BOD_VL_2_7V);
/* Enable BOD IRQ */
NVIC_EnableIRQ(BOD_IRQn);
/* Enable Low Voltage Reset function */
SYS_ENABLE_LVR();
/* Run PLL Test */
SYS_PLL_Test();
/* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n");
/* Waiting for message send out */
UART_WAIT_TX_EMPTY(UART0);
/* Switch HCLK clock source to Internal RC 22.1184MHz clock and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Set PLL to Power down mode and HW will also clear PLL_STB bit in CLKSTATUS register */
CLK_DisablePLL();
/* Reset CPU */
SYS_ResetCPU();
}
/*****************************************************************************
* x264_macroblock_analyse:
*****************************************************************************/
void dull_macroblock_analyse_P_BEST( x264_t *h )
{
x264_mb_analysis_t analysis;
int i_cost = COST_MAX;
int i;
dull_mb_analyse_init_P( h, &analysis );
/*--------------------------- Do the analysis ---------------------------*/
//{ macroblock_analyse_P //{ macroblock_analyse_P //{ macroblock_analyse_P //{ macroblock_analyse_P
{
int b_skip = 0;
analysis.b_try_skip = 0;
if( b_skip )
{
h->mb.i_type = P_SKIP;
h->mb.i_partition = D_16x16;
assert( h->mb.cache.pskip_mv[1] <= h->mb.mv_max_spel[1] || h->i_thread_frames == 1 );
/* Set up MVs for future predictors */
for( i = 0; i < h->mb.pic.i_fref[0]; i++ )
M32( h->mb.mvr[0][i][h->mb.i_mb_xy] ) = 0;
}
else
{
const unsigned int flags = h->param.analyse.inter;
int i_type;
int i_partition;
x264_mb_analyse_load_costs( h, &analysis );
dull_mb_analyse_inter_p16x16_2( h, &analysis );
if( h->mb.i_type == P_SKIP )
{
for( i = 1; i < h->mb.pic.i_fref[0]; i++ )
M32( h->mb.mvr[0][i][h->mb.i_mb_xy] ) = 0;
return;
}
if( flags & X264_ANALYSE_PSUB16x16 )
{
if( h->param.analyse.b_mixed_references )
x264_mb_analyse_inter_p8x8_mixed_ref( h, &analysis );
else
dull_mb_analyse_inter_p8x8_2( h, &analysis );
}
/* Select best inter mode */
i_type = P_L0;
i_partition = D_16x16;
i_cost = analysis.l0.me16x16.cost;
if( ( flags & X264_ANALYSE_PSUB16x16 ) &&
analysis.l0.i_cost8x8 < analysis.l0.me16x16.cost )
{
i_type = P_8x8;
i_partition = D_8x8;
i_cost = analysis.l0.i_cost8x8;
/* Do sub 8x8 */
if( flags & X264_ANALYSE_PSUB8x8 )
{
for( i = 0; i < 4; i++ )
{
x264_mb_analyse_inter_p4x4( h, &analysis, i );
if( analysis.l0.i_cost4x4[i] < analysis.l0.me8x8[i].cost )
{
int i_cost8x8 = analysis.l0.i_cost4x4[i];
h->mb.i_sub_partition[i] = D_L0_4x4;
i_cost += i_cost8x8 - analysis.l0.me8x8[i].cost;
}
x264_mb_cache_mv_p8x8( h, &analysis, i );
}
analysis.l0.i_cost8x8 = i_cost;
}
}
h->mb.i_partition = i_partition;
/* refine qpel */
//FIXME mb_type costs?
if( analysis.i_mbrd || !h->mb.i_subpel_refine )
{
/* refine later */
}
else if( i_partition == D_16x16 )
{
x264_me_refine_qpel( h, &analysis.l0.me16x16 );
i_cost = analysis.l0.me16x16.cost;
}
else if( i_partition == D_16x8 )
{
x264_me_refine_qpel( h, &analysis.l0.me16x8[0] );
x264_me_refine_qpel( h, &analysis.l0.me16x8[1] );
i_cost = analysis.l0.me16x8[0].cost + analysis.l0.me16x8[1].cost;
}
else if( i_partition == D_8x16 )
{
x264_me_refine_qpel( h, &analysis.l0.me8x16[0] );
x264_me_refine_qpel( h, &analysis.l0.me8x16[1] );
i_cost = analysis.l0.me8x16[0].cost + analysis.l0.me8x16[1].cost;
}
else if( i_partition == D_8x8 )
{
int i8x8;
i_cost = 0;
for( i8x8 = 0; i8x8 < 4; i8x8++ )
{
switch( h->mb.i_sub_partition[i8x8] )
{
case D_L0_8x8:
x264_me_refine_qpel( h, &analysis.l0.me8x8[i8x8] );
i_cost += analysis.l0.me8x8[i8x8].cost;
break;
case D_L0_8x4:
x264_me_refine_qpel( h, &analysis.l0.me8x4[i8x8][0] );
x264_me_refine_qpel( h, &analysis.l0.me8x4[i8x8][1] );
i_cost += analysis.l0.me8x4[i8x8][0].cost +
analysis.l0.me8x4[i8x8][1].cost;
break;
case D_L0_4x8:
x264_me_refine_qpel( h, &analysis.l0.me4x8[i8x8][0] );
x264_me_refine_qpel( h, &analysis.l0.me4x8[i8x8][1] );
i_cost += analysis.l0.me4x8[i8x8][0].cost +
analysis.l0.me4x8[i8x8][1].cost;
break;
case D_L0_4x4:
x264_me_refine_qpel( h, &analysis.l0.me4x4[i8x8][0] );
x264_me_refine_qpel( h, &analysis.l0.me4x4[i8x8][1] );
x264_me_refine_qpel( h, &analysis.l0.me4x4[i8x8][2] );
x264_me_refine_qpel( h, &analysis.l0.me4x4[i8x8][3] );
i_cost += analysis.l0.me4x4[i8x8][0].cost +
analysis.l0.me4x4[i8x8][1].cost +
analysis.l0.me4x4[i8x8][2].cost +
analysis.l0.me4x4[i8x8][3].cost;
break;
default:
x264_log( h, X264_LOG_ERROR, "internal error (!8x8 && !4x4)\n" );
break;
}
}
}
if( h->mb.b_chroma_me )
{
x264_mb_analyse_intra_chroma( h, &analysis );
x264_mb_analyse_intra( h, &analysis, i_cost - analysis.i_satd_i8x8chroma );
analysis.i_satd_i16x16 += analysis.i_satd_i8x8chroma;
analysis.i_satd_i8x8 += analysis.i_satd_i8x8chroma;
analysis.i_satd_i4x4 += analysis.i_satd_i8x8chroma;
}
else
x264_mb_analyse_intra( h, &analysis, i_cost );
COPY2_IF_LT( i_cost, analysis.i_satd_i16x16, i_type, I_16x16 );
COPY2_IF_LT( i_cost, analysis.i_satd_i8x8, i_type, I_8x8 );
COPY2_IF_LT( i_cost, analysis.i_satd_i4x4, i_type, I_4x4 );
h->mb.i_type = i_type;
if( analysis.i_mbrd >= 2 && h->mb.i_type != I_PCM )
{
if( IS_INTRA( h->mb.i_type ) )
{
x264_intra_rd_refine( h, &analysis );
}
else if( i_partition == D_16x16 )
{
x264_macroblock_cache_ref( h, 0, 0, 4, 4, 0, analysis.l0.me16x16.i_ref );
analysis.l0.me16x16.cost = i_cost;
x264_me_refine_qpel_rd( h, &analysis.l0.me16x16, analysis.i_lambda2, 0, 0 );
}
else if( i_partition == D_16x8 )
{
h->mb.i_sub_partition[0] = h->mb.i_sub_partition[1] =
h->mb.i_sub_partition[2] = h->mb.i_sub_partition[3] = D_L0_8x8;
x264_macroblock_cache_ref( h, 0, 0, 4, 2, 0, analysis.l0.me16x8[0].i_ref );
x264_macroblock_cache_ref( h, 0, 2, 4, 2, 0, analysis.l0.me16x8[1].i_ref );
x264_me_refine_qpel_rd( h, &analysis.l0.me16x8[0], analysis.i_lambda2, 0, 0 );
x264_me_refine_qpel_rd( h, &analysis.l0.me16x8[1], analysis.i_lambda2, 8, 0 );
}
else if( i_partition == D_8x16 )
{
h->mb.i_sub_partition[0] = h->mb.i_sub_partition[1] =
h->mb.i_sub_partition[2] = h->mb.i_sub_partition[3] = D_L0_8x8;
x264_macroblock_cache_ref( h, 0, 0, 2, 4, 0, analysis.l0.me8x16[0].i_ref );
x264_macroblock_cache_ref( h, 2, 0, 2, 4, 0, analysis.l0.me8x16[1].i_ref );
x264_me_refine_qpel_rd( h, &analysis.l0.me8x16[0], analysis.i_lambda2, 0, 0 );
x264_me_refine_qpel_rd( h, &analysis.l0.me8x16[1], analysis.i_lambda2, 4, 0 );
}
else if( i_partition == D_8x8 )
{
int i8x8;
x264_analyse_update_cache( h, &analysis );
for( i8x8 = 0; i8x8 < 4; i8x8++ )
{
if( h->mb.i_sub_partition[i8x8] == D_L0_8x8 )
{
x264_me_refine_qpel_rd( h, &analysis.l0.me8x8[i8x8], analysis.i_lambda2, i8x8*4, 0 );
}
else if( h->mb.i_sub_partition[i8x8] == D_L0_8x4 )
{
x264_me_refine_qpel_rd( h, &analysis.l0.me8x4[i8x8][0], analysis.i_lambda2, i8x8*4+0, 0 );
x264_me_refine_qpel_rd( h, &analysis.l0.me8x4[i8x8][1], analysis.i_lambda2, i8x8*4+2, 0 );
}
else if( h->mb.i_sub_partition[i8x8] == D_L0_4x8 )
{
x264_me_refine_qpel_rd( h, &analysis.l0.me4x8[i8x8][0], analysis.i_lambda2, i8x8*4+0, 0 );
x264_me_refine_qpel_rd( h, &analysis.l0.me4x8[i8x8][1], analysis.i_lambda2, i8x8*4+1, 0 );
}
else if( h->mb.i_sub_partition[i8x8] == D_L0_4x4 )
{
x264_me_refine_qpel_rd( h, &analysis.l0.me4x4[i8x8][0], analysis.i_lambda2, i8x8*4+0, 0 );
x264_me_refine_qpel_rd( h, &analysis.l0.me4x4[i8x8][1], analysis.i_lambda2, i8x8*4+1, 0 );
x264_me_refine_qpel_rd( h, &analysis.l0.me4x4[i8x8][2], analysis.i_lambda2, i8x8*4+2, 0 );
x264_me_refine_qpel_rd( h, &analysis.l0.me4x4[i8x8][3], analysis.i_lambda2, i8x8*4+3, 0 );
}
}
}
}
}
}
//} macroblock_analyse_P //} macroblock_analyse_P //} macroblock_analyse_P //} macroblock_analyse_P
dull_analyse_update_cache_P( h, &analysis );
}
void McDull_swataw( McDull_t* McDull )
{
x264_t* h = McDull->x264;
int i_mb_x = h->mb.i_mb_x;
int i_mb_y = h->mb.i_mb_y;
swataw_mode_t mode = swataw_get_mode(McDull->swataw, i_mb_x, i_mb_y);
h->mb.i_qp = x264_ratecontrol_mb_qp( h );
if (mode == swataw_MODE_P_SKIP)
if ( M32(h->mb.cache.pskip_mv) )
{
mode = swataw_MODE_P_FAST;
swataw_set_mode(McDull->swataw, mode, i_mb_x, i_mb_y);
}
if (mode == swataw_MODE_B_SKIP)
if ( M32(h->mb.cache.pskip_mv) )
{
mode = swataw_MODE_B_FAST;
swataw_set_mode(McDull->swataw, mode, i_mb_x, i_mb_y);
}
switch(mode)
{
case swataw_MODE_P_SKIP:
McDull_swataw_P_SKIP( McDull );
break;
case swataw_MODE_P_FAST:
//McDull_swataw_P_FAST( McDull );
//break;
case swataw_MODE_P_GOOD:
//McDull_swataw_P_GOOD( McDull );
//break;
case swataw_MODE_P_BEST:
McDull_swataw_P_BEST( McDull );
break;
case swataw_MODE_B_SKIP:
//McDull_swataw_B_SKIP( McDull );
//break;
case swataw_MODE_B_FAST:
//McDull_swataw_B_FAST( McDull );
//break;
case swataw_MODE_B_GOOD:
//McDull_swataw_B_GOOD( McDull );
//break;
case swataw_MODE_B_BEST:
//McDull_swataw_B_GOOD( McDull );
//break;
McDull_swataw_BEST( McDull );
break;
case swataw_MODE_I_FAST:
//McDull_swataw_I_FAST( McDull );
//break;
case swataw_MODE_I_BEST:
//McDull_swataw_I_BEST( McDull );
//break;
McDull_swataw_BEST( McDull );
break;
default:
assert( 0 );
break;
}
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
uint32_t u32TrimInit;
uint8_t Str[9];
/* Unlock protected registers */
SYS_UnlockReg();
SYS_Init();
UART0_Init();
printf("\n");
printf("+--------------------------------------------------------+\n");
printf("| NuMicro USB Composite Device Sample Code |\n");
printf("| USB Micro Printer + HID Transfer |\n");
printf("+--------------------------------------------------------+\n");
USBD_Open(&gsInfo, PTR_ClassRequest, NULL);
/* Endpoint configuration */
PTR_Init();
USBD_Start();
#if CRYSTAL_LESS
/* Backup init trim */
u32TrimInit = M32(TRIM_INIT);
/* Enable USB crystal-less */
SYS->HIRCTCTL = 0x201 | (31 << SYS_HIRCTCTL_BOUNDARY_Pos);
#endif
NVIC_EnableIRQ(USBD_IRQn);
PB->PMD = 0x5000; // PB.6, PB.7 output mode
while(1)
{
#if CRYSTAL_LESS
/* Re-start crystal-less when any error found */
if (SYS->HIRCTSTS & (SYS_HIRCTSTS_CLKERIF_Msk | SYS_HIRCTSTS_TFAILIF_Msk))
{
SYS->HIRCTSTS = SYS_HIRCTSTS_CLKERIF_Msk | SYS_HIRCTSTS_TFAILIF_Msk;
if((u32TrimInit < 0x1E6) || (u32TrimInit > 0x253))
/* Re-enable crystal-less */
SYS->HIRCTCTL = 0x201 | (1 << SYS_HIRCTCTL_BOUNDARY_Pos);
else
/* Re-enable crystal-less */
SYS->HIRCTCTL = 0x201 | (31 << SYS_HIRCTCTL_BOUNDARY_Pos);
//printf("USB trim fail. Just retry. SYS->HIRCTSTS = 0x%x, SYS->HIRCTCTL = 0x%x\n", SYS->HIRCTSTS, SYS->HIRCTCTL);
}
#endif
CLK_SysTickDelay(2000); // delay
if(++Str[1] > 0x39)
Str[1] = 0x30; // increase 1 to 10 than reset to 0
PB->DOUT ^= 0x40; // PB.6
}
}
//{ mb_analyse_inter_p16x16 //{ mb_analyse_inter_p16x16 //{ mb_analyse_inter_p16x16 //{ mb_analyse_inter_p16x16
static void dull_mb_analyse_inter_p16x16_2( x264_t *h, x264_mb_analysis_t *a )
{
int i_ref, i_mvc;
ALIGNED_4( int16_t mvc[8][2] );
int i_halfpel_thresh = INT_MAX;
int *p_halfpel_thresh = NULL;
x264_me_t m;
m.i_pixel = PIXEL_16x16;
LOAD_FENC( &m, h->mb.pic.p_fenc, 0, 0 );
a->l0.me16x16.cost = INT_MAX;
for( i_ref = 0; i_ref < h->mb.pic.i_fref[0]; i_ref++ )
{
m.i_ref_cost = REF_COST( 0, i_ref );
i_halfpel_thresh -= m.i_ref_cost;
/* search with ref */
LOAD_HPELS( &m, h->mb.pic.p_fref[0][i_ref], 0, i_ref, 0, 0 );
LOAD_WPELS( &m, h->mb.pic.p_fref_w[i_ref], 0, i_ref, 0, 0 );
x264_mb_predict_mv_16x16( h, 0, i_ref, m.mvp );
if( h->mb.ref_blind_dupe == i_ref )
{
CP32( m.mv, a->l0.mvc[0][0] );
x264_me_refine_qpel_refdupe( h, &m, p_halfpel_thresh );
}
else
{
x264_mb_predict_mv_ref16x16( h, 0, i_ref, mvc, &i_mvc );
x264_me_search_ref( h, &m, mvc, i_mvc, p_halfpel_thresh );
}
/* save mv for predicting neighbors */
CP32( h->mb.mvr[0][i_ref][h->mb.i_mb_xy], m.mv );
CP32( a->l0.mvc[i_ref][0], m.mv );
/* early termination
* SSD threshold would probably be better than SATD */
if( i_ref == 0
&& a->b_try_skip
&& m.cost-m.cost_mv < 300*a->i_lambda
&& abs(m.mv[0]-h->mb.cache.pskip_mv[0])
+ abs(m.mv[1]-h->mb.cache.pskip_mv[1]) <= 1
&& x264_macroblock_probe_pskip( h ) )
{
h->mb.i_type = P_SKIP;
x264_analyse_update_cache( h, a );
assert( h->mb.cache.pskip_mv[1] <= h->mb.mv_max_spel[1] || h->i_thread_frames == 1 );
return;
}
m.cost += m.i_ref_cost;
i_halfpel_thresh += m.i_ref_cost;
if( m.cost < a->l0.me16x16.cost )
h->mc.memcpy_aligned( &a->l0.me16x16, &m, sizeof(x264_me_t) );
}
x264_macroblock_cache_ref( h, 0, 0, 4, 4, 0, a->l0.me16x16.i_ref );
assert( a->l0.me16x16.mv[1] <= h->mb.mv_max_spel[1] || h->i_thread_frames == 1 );
h->mb.i_type = P_L0;
if( a->i_mbrd )
{
x264_mb_init_fenc_cache( h, a->i_mbrd >= 2 || h->param.analyse.inter & X264_ANALYSE_PSUB8x8 );
if( a->l0.me16x16.i_ref == 0 && M32( a->l0.me16x16.mv ) == M32( h->mb.cache.pskip_mv ) && !a->b_force_intra )
{
h->mb.i_partition = D_16x16;
x264_macroblock_cache_mv_ptr( h, 0, 0, 4, 4, 0, a->l0.me16x16.mv );
a->l0.i_rd16x16 = x264_rd_cost_mb( h, a->i_lambda2 );
if( !(h->mb.i_cbp_luma|h->mb.i_cbp_chroma) )
h->mb.i_type = P_SKIP;
}
}
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
uint32_t u32data;
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %d Hz\n", SystemCoreClock);
printf("+---------------------------------------+\n");
printf("| M451 System Driver Sample Code |\n");
printf("+---------------------------------------+\n");
if(M32(FLAG_ADDR) == SIGNATURE)
{
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = 0;
printf(" Press any key to continue ...\n");
getchar();
}
/*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/
/* Read Part Device ID */
printf("Product ID 0x%x\n", SYS->PDID);
/* Get reset source from last operation */
u32data = SYS->RSTSTS;
printf("Reset Source 0x%x\n", u32data);
/* Clear reset source */
SYS->RSTSTS = u32data;
/* Unlock protected registers for Brown-Out Detector settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if(SYS->REGLCTL != 0)
{
printf("Protected Address is Unlocked\n");
}
/* Enable Brown-Out Detector and Low Voltage Reset function, and set Brown-Out Detector voltage 2.7V */
SYS->BODCTL = SYS_BODCTL_BODEN_Msk | SYS_BODCTL_BODVL_2_7V | SYS_BODCTL_LVREN_Msk;
/* Enable BOD interrupt */
NVIC_EnableIRQ(BOD_IRQn);
/* Run PLL Test */
SYS_PLL_Test();
/* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n");
/* Wait for message send out */
while(!(UART0->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk));
/* Select HCLK clock source as HIRC and HCLK source divider as 1 */
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | CLK_CLKDIV0_HCLK(1);
/* Set PLL to Power down mode and HW will also clear PLLSTB bit in CLKSTATUS register */
CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
/* Reset CPU */
SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
}
/* This just improves encoder performance, it's not part of the spec */
void x264_mb_predict_mv_ref16x16( x264_t *h, int i_ref, int16_t mvc[9][2], int *i_mvc )
{
int16_t (*mvr)[2] = h->mb.mvr[i_ref];
int i = 0;
#define SET_MVP(mvp) \
{ \
CP32( mvc[i], mvp ); \
i++; \
}
#define SET_IMVP(xy) \
if( xy >= 0 ) \
{ \
int shift = 1 - h->mb.field[xy]; \
int16_t *mvp = h->mb.mvr[i_ref<<1>>shift][xy]; \
mvc[i][0] = mvp[0]; \
mvc[i][1] = mvp[1]<<1>>shift; \
i++; \
}
if( i_ref == 0 && h->frames.b_have_lowres )
{
int idx = h->fenc->i_frame-h->fref[0]->i_frame-1;
if( idx <= 0 )
{
int16_t (*lowres_mv)[2] = h->fenc->lowres_mvs[0][idx];
if( lowres_mv[0][0] != 0x7fff )
{
M32( mvc[i] ) = (M32( lowres_mv[h->mb.i_mb_xy] )*2)&0xfffeffff;
i++;
}
}
}
/* spatial predictors */
{
SET_MVP( mvr[h->mb.i_mb_left_xy[0]] );
SET_MVP( mvr[h->mb.i_mb_top_xy] );
SET_MVP( mvr[h->mb.i_mb_topleft_xy] );
SET_MVP( mvr[h->mb.i_mb_topright_xy] );
}
#undef SET_IMVP
#undef SET_MVP
/* temporal predictors */
if( h->fref[0]->i_ref > 0 )
{
x264_frame_t *l0 = h->fref[0];
int field = h->mb.i_mb_y&1;
int curpoc = h->fdec->i_poc + h->fdec->i_delta_poc[field];
int refpoc = h->fref[i_ref]->i_poc;
refpoc += l0->i_delta_poc[field^(i_ref&1)];
#define SET_TMVP( dx, dy ) \
{ \
int mb_index = h->mb.i_mb_xy + dx + dy*h->mb.i_mb_stride; \
int scale = (curpoc - refpoc) * l0->inv_ref_poc; \
mvc[i][0] = (l0->mv16x16[mb_index][0]*scale + 128) >> 8; \
mvc[i][1] = (l0->mv16x16[mb_index][1]*scale + 128) >> 8; \
i++; \
}
SET_TMVP(0,0);
if( h->mb.i_mb_x < h->mb.i_mb_width-1 )
SET_TMVP(1,0);
if( h->mb.i_mb_y < h->mb.i_mb_height-1 )
SET_TMVP(0,1);
#undef SET_TMVP
}
*i_mvc = i;
}
static void emit_string(REgg *egg, const char *dstvar, const char *str, int j) {
char *p, *s, str2[64];
int i, len, oj = j;
len = strlen (str);
s = malloc (len+4);
if (!s) return;
memcpy (s, str, len);
memset (s+len, 0, 4);
/* XXX: Hack: Adjust offset in R_BP correctly for 64b addresses */
#define BPOFF R_SZ-4
#define M32(x) (unsigned int)((x) & 0xffffffff)
/* XXX: Assumes sizeof(ut32) == 4 */
for (i=4; i<=oj; i+=4) {
/* XXX endian issues (non-portable asm) */
ut32 *n = (ut32 *)(s+i-4);
p = r_egg_mkvar (egg, str2, dstvar, i+BPOFF);
if (attsyntax) r_egg_printf (egg, " movl $0x%x, %s\n", M32(*n), p);
else r_egg_printf (egg, " mov %s, 0x%x\n", p, M32(*n));
free (p);
j -= 4;
}
#undef M32
/* zero */
p = r_egg_mkvar (egg, str2, dstvar, i+BPOFF);
if (attsyntax) r_egg_printf (egg, " movl $0, %s\n", p);
else r_egg_printf (egg, " mov %s, 0\n", p);
free (p);
/* store pointer */
p = r_egg_mkvar (egg, str2, dstvar, j+4+BPOFF);
if (attsyntax) r_egg_printf (egg, " lea %s, %%"R_AX"\n", p);
else r_egg_printf (egg, " lea "R_AX", %s\n", p);
free (p);
p = r_egg_mkvar (egg, str2, dstvar, 0);
if (attsyntax) r_egg_printf (egg, " mov %%"R_AX", %s\n", p);
else r_egg_printf (egg, " mov %s, "R_AX"\n", p);
free (p);
#undef BPOFF
#if 0
char *p, str2[64];
int i, oj = j;
for (i=0; i<oj; i+=4) {
/* XXX endian and 32/64bit issues */
int *n = (int *)(str+i);
p = r_egg_mkvar (egg, str2, dstvar, j);
if (attsyntax) r_egg_printf (egg, " movl $0x%x, %s\n", *n, p);
else r_egg_printf (egg, " mov %s, 0x%x\n", p, *n);
j -= 4;
}
p = r_egg_mkvar (egg, str2, dstvar, oj);
if (attsyntax) r_egg_printf (egg, " lea %s, %%"R_AX"\n", p);
else r_egg_printf (egg, " lea "R_AX", %s\n", p);
p = r_egg_mkvar (egg, str2, dstvar, 0);
if (attsyntax) r_egg_printf (egg, " mov %%"R_AX", %s\n", p);
else r_egg_printf (egg, " mov %s, "R_AX"\n", p);
#endif
free (s);
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
uint32_t u32TrimInit;
uint32_t au32Config[2];
/* Unlock protected registers */
SYS_UnlockReg();
SYS_Init();
UART0_Init();
printf("\n");
printf("+-------------------------------------------------------------+\n");
printf("| NuMicro USB Virtual COM and MassStorage Sample Code |\n");
printf("+-------------------------------------------------------------+\n");
/* Enable FMC ISP function */
FMC_Open();
/* Check if Data Flash Size is 64K. If not, to re-define Data Flash size and to enable Data Flash function */
if(FMC_ReadConfig(au32Config, 2) < 0)
return -1;
if(((au32Config[0] & 0x01) == 1) || (au32Config[1] != DATA_FLASH_BASE))
{
FMC_EnableConfigUpdate();
au32Config[0] &= ~0x1;
au32Config[1] = DATA_FLASH_BASE;
FMC_Erase(CONFIG_BASE);
if(FMC_WriteConfig(au32Config, 2) < 0)
return -1;
FMC_ReadConfig(au32Config, 2);
if(((au32Config[0] & 0x01) == 1) || (au32Config[1] != DATA_FLASH_BASE))
{
printf("Error: Program Config Failed!\n");
/* Disable FMC ISP function */
FMC_Close();
return -1;
}
/* Reset Chip to reload new CONFIG value */
SYS->IPRSTC1 = SYS_IPRSTC1_CHIP_RST_Msk;
}
printf("NuMicro USB MassStorage Start!\n");
/* Open USB controller */
USBD_Open(&gsInfo, VCOM_MSC_ClassRequest, NULL);
USBD_SetConfigCallback(MSC_SetConfig);
/* Endpoint configuration */
VCOM_MSC_Init();
USBD_Start();
#if CRYSTAL_LESS
/* Backup init trim */
u32TrimInit = M32(TRIM_INIT);
/* Enable USB crystal-less */
SYS->HIRCTCTL = 0x201 | (31 << SYS_HIRCTCTL_BOUNDARY_Pos);
#endif
NVIC_EnableIRQ(USBD_IRQn);
NVIC_EnableIRQ(UART02_IRQn);
while(1)
{
#if CRYSTAL_LESS
/* Re-start crystal-less when any error found */
if (SYS->HIRCTSTS & (SYS_HIRCTSTS_CLKERIF_Msk | SYS_HIRCTSTS_TFAILIF_Msk))
{
SYS->HIRCTSTS = SYS_HIRCTSTS_CLKERIF_Msk | SYS_HIRCTSTS_TFAILIF_Msk;
if((u32TrimInit < 0x1E6) || (u32TrimInit > 0x253))
/* Re-enable crystal-less */
SYS->HIRCTCTL = 0x201 | (1 << SYS_HIRCTCTL_BOUNDARY_Pos);
else
/* Re-enable crystal-less */
SYS->HIRCTCTL = 0x201 | (31 << SYS_HIRCTCTL_BOUNDARY_Pos);
//printf("USB trim fail. Just retry. SYS->HIRCTSTS = 0x%x, SYS->HIRCTCTL = 0x%x\n", SYS->HIRCTSTS, SYS->HIRCTCTL);
}
#endif
VCOM_TransferData();
MSC_ProcessCmd();
}
}
int32_t main (void)
{
uint32_t u32data;
/* HCLK will be set to 42MHz in SYS_Init(void)*/
if(SYS->RegLockAddr == 1) // In end of main function, program issued CPU reset and write-protection will be disabled.
SYS_LockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init(); //In the end of SYS_Init() will issue SYS_LockReg() to lock protected register. If user want to write protected register, please issue SYS_UnlockReg() to unlock protected register.
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
/*
This sample code will show some function about system manager controller and clock controller:
1. Read PDID
2. Get and clear reset source
3. Setting about BOD
4. Output system clock from CKO pin, and the output frequency = system clock / 4
*/
printf("+----------------------------------------+\n");
printf("| Nano100 System Driver Sample Code |\n");
printf("+----------------------------------------+\n");
if (M32(FLAG_ADDR) == SIGNATURE)
{
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = 0;
printf(" Press any key to continue ...\n");
GetChar();
}
/*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/
/* Read Part Device ID */
printf("Product ID 0x%x\n", SYS->PDID);
/* Get reset source from last operation */
u32data = SYS_GetResetSrc();
printf("Reset Source 0x%x\n", u32data);
/* Clear reset source */
SYS_ClearResetSrc(u32data);
/* Unlock protected registers for Brown-Out Detector and power down settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if (SYS->RegLockAddr != 0)
{
printf("Protected Address is Unlocked\n");
}
/* Enable Brown-Out Detector and Low Voltage Reset function, and set Brown-Out Detector voltage 2.5V ,
Enable Brown-Out Interrupt function */
SYS_EnableBOD(SYS_BODCTL_BOD25_INT_EN_Msk,SYS_BODCTL_BOD25_EN_Msk);
/* Enable BOD IRQ */
NVIC_EnableIRQ(BOD_IRQn);
/* Waiting for message send out */
// _UART_WAIT_TX_EMPTY(UART0);
/* Enable CKO and output frequency = system clock / 4 */
CLK_EnableCKO(CLK_CLKSEL2_FRQDIV_S_HCLK,1);
/* Switch HCLK clock source to Internal 11.0592MHz */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC,CLK_HCLK_CLK_DIVIDER(1));
/* Enable WDT clock */
CLK_EnableModuleClock(WDT_MODULE);
/* Enable WDT and interrupt */
WDT->CTL = 0x00000050 | 0x00000004 | 0x00000008;
WDT->IER |= 0x00000001;
NVIC_EnableIRQ(WDT_IRQn);
CLK->PWRCTL |= CLK_PWRCTL_WAKEINT_EN; /* Enable wake up interrupt source */
NVIC_EnableIRQ(PDWU_IRQn); /* Enable IRQ request for PDWU interrupt */
printf("u32PWDU_WakeFlag = %x\n",u32PWDU_WakeFlag);
printf("Enter Power Down Mode >>>>>>>>>>>\n");
u32PWDU_WakeFlag = 0; /* clear software semaphore */
while(!(UART0->FSR & UART_FSR_TX_EMPTY_F_Msk)) ; /* waits for message send out */
CLK_PowerDown();
/* CPU Reset test */
printf("Waits for 5 times WDT interrupts.....\n");
while (u32WDT_Ticks <= 5);
printf("<<<<<<<<<< Program resumes execution.\n");
printf("u32PWDU_WakeFlag = %x\n",u32PWDU_WakeFlag);
/* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n");
/* Reset CPU */
SYS_ResetCPU();
}
//{ me_search_ref //{ me_search_ref //{ me_search_ref //{ me_search_ref
void dull_me_search_ref( x264_t *h, x264_me_t *m, int16_t (*mvc)[2], int i_mvc, int *p_halfpel_thresh )
{
const int bw = x264_pixel_size[m->i_pixel].w;
const int bh = x264_pixel_size[m->i_pixel].h;
const int i_pixel = m->i_pixel;
const int stride = m->i_stride[0];
int i_me_range = h->param.analyse.i_me_range;
int bmx, bmy, bcost;
int bpred_mx = 0, bpred_my = 0, bpred_cost = COST_MAX;
int pmx, pmy;
pixel *p_fenc = m->p_fenc[0];
pixel *p_fref_w = m->p_fref_w;
ALIGNED_ARRAY_16( pixel, pix,[16*16] );
int i;
int costs[16];
int mv_x_min = h->mb.mv_min_fpel[0];
int mv_y_min = h->mb.mv_min_fpel[1];
int mv_x_max = h->mb.mv_max_fpel[0];
int mv_y_max = h->mb.mv_max_fpel[1];
int mv_x_min_qpel = mv_x_min << 2;
int mv_y_min_qpel = mv_y_min << 2;
int mv_x_max_qpel = mv_x_max << 2;
int mv_y_max_qpel = mv_y_max << 2;
/* Special version of pack to allow shortcuts in CHECK_MVRANGE */
#define pack16to32_mask2(mx,my) ((mx<<16)|(my&0x7FFF))
uint32_t mv_min = pack16to32_mask2( -mv_x_min, -mv_y_min );
uint32_t mv_max = pack16to32_mask2( mv_x_max, mv_y_max )|0x8000;
#define CHECK_MVRANGE(mx,my) (!(((pack16to32_mask2(mx,my) + mv_min) | (mv_max - pack16to32_mask2(mx,my))) & 0x80004000))
const uint16_t *p_cost_mvx = m->p_cost_mv - m->mvp[0];
const uint16_t *p_cost_mvy = m->p_cost_mv - m->mvp[1];
uint32_t pmv;
bmx = x264_clip3( m->mvp[0], mv_x_min_qpel, mv_x_max_qpel );
bmy = x264_clip3( m->mvp[1], mv_y_min_qpel, mv_y_max_qpel );
pmx = ( bmx + 2 ) >> 2;
pmy = ( bmy + 2 ) >> 2;
bcost = COST_MAX;
/* try extra predictors if provided */
if( h->mb.i_subpel_refine >= 3 )
{
pmv = pack16to32_mask(bmx,bmy);
if( i_mvc )
COST_MV_HPEL( bmx, bmy );
for( i = 0; i < i_mvc; i++ )
{
if( M32( mvc[i] ) && (pmv != M32( mvc[i] )) )
{
int mx = x264_clip3( mvc[i][0], mv_x_min_qpel, mv_x_max_qpel );
int my = x264_clip3( mvc[i][1], mv_y_min_qpel, mv_y_max_qpel );
COST_MV_HPEL( mx, my );
}
}
bmx = ( bpred_mx + 2 ) >> 2;
bmy = ( bpred_my + 2 ) >> 2;
COST_MV( bmx, bmy );
}
/*---------------------------------------------------------------------------------------------------------*/
void SYS_Example (void)
{
uint32_t u32data;
/* Lock protected registers */
if(SYS->REGWRPROT == 1) // In end of main function, program issued CPU reset and write-protection will be disabled.
SYS_LockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init(); //In the end of SYS_Init() will issue SYS_LockReg() to lock protected register. If user want to write protected register, please issue SYS_UnlockReg() to unlock protected register.
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
/*
This sample code will show some function about system manager controller and clock controller:
1. Read PDID
2. Get and clear reset source
3. Setting about BOD
4. Change system clock depended on different PLL settings
5. Outout system clock from CKO pin, and the output frequency = system clock / 4
*/
printf("+---------------------------------------+\n");
printf("| NUC200 System Driver Sample Code |\n");
printf("+---------------------------------------+\n");
if (M32(FLAG_ADDR) == SIGNATURE)
{
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = 0;
printf(" Press any key to continue ...\n");
uart_getchar();
}
/*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/
/* Read Part Device ID */
printf("Product ID 0x%x\n", SYS->PDID);
/* Get reset source from last operation */
u32data = SYS->RSTSRC;
printf("Reset Source 0x%x\n", u32data);
/* Clear reset source */
SYS->RSTSRC = u32data;
/* Unlock protected registers for Brown-Out Detector settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if (SYS->REGWRPROT != 0)
{
printf("Protected Address is Unlocked\n");
}
/* Enable Brown-Out Detector and Low Voltage Reset function, and set Brown-Out Detector voltage 2.7V */
SYS->BODCR =SYS_BODCR_BOD_EN_Msk | SYS_BODCR_BOD_VL_2_7V | SYS_BODCR_LVR_EN_Msk;
/* Enable Brown-Out Interrupt function */
SYS->BODCR &= ~SYS_BODCR_BOD_RSTEN_Msk;
NVIC_EnableIRQ(BOD_IRQn);
/* Get system clock frequency and PLL clock frequency */
printf(" Change system clock to %d Hz and PLL clock is %d Hz\n", SystemCoreClock, PllClock);
/* Run PLL Test */
SYS_PLL_Test();
/* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n");
/* Waiting for message send out */
_UART_WAIT_TX_EMPTY(UART0);
/* Switch HCLK clock source to Internal 22MHz */
SYSCLK->CLKSEL0 = SYSCLK_CLKSEL0_HCLK_IRC22M;
/* Set PLL to Power down mode and HW will also clear PLL_STB bit in CLKSTATUS register */
SYSCLK->PLLCON |= SYSCLK_PLLCON_PD_Msk;
/* Reset CPU */
_SYS_RESET_CPU();
}
