static void interrupt_handler()
{
uint32_t recv_data;
uint32_t status;
status = MAP_SPIIntStatus(GSPI_BASE,true);
MAP_SPIIntClear(GSPI_BASE,SPI_INT_RX_FULL|SPI_INT_TX_EMPTY);
if(status & SPI_INT_TX_EMPTY)
{
MAP_SPIDataPut(GSPI_BASE,tx_buffer[tx_count % TR_BUFF_SIZE]);
tx_count++;
}
if(status & SPI_INT_RX_FULL)
{
MAP_SPIDataGetNonBlocking(GSPI_BASE,&recv_data);
rx_buffer[rx_count % TR_BUFF_SIZE] = recv_data;
rx_count++;
}
interrupt_count++;
if(interrupt_count % (TR_BUFF_SIZE * 2) == 0 && interrupt_count > 0)
{
transfer_count++;
}
}
/*
* ======== SPICC3200DMA_configDMA ========
* This functions configures the transmit and receive DMA channels for a given
* SPI_Handle and SPI_Transaction
*
* @pre Function assumes that the handle and transaction is not NULL
*/
static void SPICC3200DMA_configDMA(SPI_Handle handle, SPI_Transaction *transaction)
{
uintptr_t key;
SPIDataType dummy;
void *buf;
uint32_t channelControlOptions;
SPICC3200DMA_Object *object = handle->object;
SPICC3200DMA_HWAttrs const *hwAttrs = handle->hwAttrs;
/* Clear out the FIFO */
while (MAP_SPIDataGetNonBlocking(hwAttrs->baseAddr, &dummy)) {}
/* Configure DMA for RX */
MAP_uDMAChannelAssign(hwAttrs->rxChannelIndex);
MAP_uDMAChannelAttributeDisable(hwAttrs->rxChannelIndex, UDMA_ATTR_ALTSELECT);
if (transaction->rxBuf) {
channelControlOptions = dmaRxConfig[object->frameSize];
buf = transaction->rxBuf;
}
else {
channelControlOptions = dmaNullConfig[object->frameSize];
buf = hwAttrs->scratchBufPtr;
}
MAP_uDMAChannelControlSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT,
channelControlOptions);
MAP_uDMAChannelTransferSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *)(hwAttrs->baseAddr + MCSPI_O_RX0),
buf,
transaction->count);
/* Configure DMA for TX */
MAP_uDMAChannelAssign(hwAttrs->txChannelIndex);
MAP_uDMAChannelAttributeDisable(hwAttrs->txChannelIndex, UDMA_ATTR_ALTSELECT);
if (transaction->txBuf) {
channelControlOptions = dmaTxConfig[object->frameSize];
buf = transaction->txBuf;
}
else {
channelControlOptions = dmaNullConfig[object->frameSize];
*hwAttrs->scratchBufPtr = hwAttrs->defaultTxBufValue;
buf = hwAttrs->scratchBufPtr;
}
MAP_uDMAChannelControlSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT,
channelControlOptions);
MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
buf,
(void *)(hwAttrs->baseAddr + MCSPI_O_TX0),
transaction->count);
DebugP_log1("SPI:(%p) DMA transfer enabled", hwAttrs->baseAddr);
DebugP_log4("SPI: DMA transaction: %p, rxBuf: %p; txBuf: %p; Count: %d",
(uintptr_t)transaction, (uintptr_t)transaction->rxBuf,
(uintptr_t)transaction->txBuf, (uintptr_t)transaction->count);
key = HwiP_disable();
MAP_uDMAChannelEnable(hwAttrs->rxChannelIndex);
MAP_uDMAChannelEnable(hwAttrs->txChannelIndex);
HwiP_restore(key);
MAP_SPIWordCountSet(hwAttrs->baseAddr, transaction->count);
}
