//*****************************************************************************
//
//! Configures the uDMA channel
//!
//! \param uiChannel is the DMA channel to be selected
//! \param pfpAppCb is the application callback to be invoked on transfer
//!
//! This function
//! 1. Configures the uDMA channel
//!
//! \return None.
//
//*****************************************************************************
void cc_UDMAChannelSelect(unsigned int uiChannel)
{
if((uiChannel & 0xFF) > MAX_NUM_CH)
{
return;
}
MAP_uDMAChannelAssign(uiChannel);
MAP_uDMAChannelAttributeDisable(uiChannel,UDMA_ATTR_ALTSELECT);
}
//*****************************************************************************
//
//! Configures the uDMA channel
//!
//! \param uiChannel is the DMA channel to be selected
//! \param pfpAppCb is the application callback to be invoked on transfer
//!
//! This function
//! 1. Configures the uDMA channel
//!
//! \return None.
//
//*****************************************************************************
void UDMAChannelSelect(unsigned int uiChannel, tAppCallbackHndl pfpAppCb)
{
if((uiChannel & 0xFF) > MAX_NUM_CH)
{
return;
}
MAP_uDMAChannelAssign(uiChannel);
MAP_uDMAChannelAttributeDisable(uiChannel,UDMA_ATTR_ALTSELECT);
gfpAppCallbackHndl[(uiChannel & 0xFF)] = pfpAppCb;
}
//*****************************************************************************
//!
//! Initialize Scatter Gather DMA Transfer
//!
//! \param None
//!
//! \return None
//!
//*****************************************************************************
void
InitSGTransfer()
{
int i;
char * pvSrcBuf,*pvDstBuf;
//
// Source Buffer
//
pvSrcBuf=malloc(BUFF_SIZE);
if(pvSrcBuf == NULL)
{
UART_PRINT("Failed to allocate Src buffer\n\r");
return ;
}
for(i=0;i<BUFF_SIZE;i++)
*(pvSrcBuf+i)=i;
MAP_uDMAChannelAssign(UDMA_CH0_SW);
MAP_uDMAChannelAttributeDisable(UDMA_CH0_SW,UDMA_ATTR_ALTSELECT);
iDone=0;
pvDstBuf=malloc(BUFF_SIZE);
if(pvDstBuf == NULL)
{
UART_PRINT("Failed to allocate Dst buffer\n\r");
return ;
}
//
// Call to Set Up Scatter Gather Mode Transfer
//
SetupSGMemTransfer(UDMA_CH0_SW,pvSrcBuf,pvSrcBuf+BUFF_SIZE/2,
pvDstBuf,BUFF_SIZE/2);
MAP_uDMAChannelRequest(UDMA_CH0_SW);
//
// Checking for the Completion
//
while(!iDone);
//
// Checking Correctness of SG Transfer
//
if(memcmp(pvSrcBuf,pvDstBuf,BUFF_SIZE)==0)
UART_PRINT("SG Mode Memory to Memory Transfer Completed \n\r\n\r");
else
UART_PRINT("SG Mode Memory to Memory Transfer Failed! \n\r\n\r");
free(pvDstBuf);
}
void spi_init(void) {
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_GPIOPinConfigure(GPIO_PA2_SSI0CLK);
MAP_GPIOPinConfigure(GPIO_PA5_SSI0TX);
MAP_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_5);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
MAP_GPIOPinConfigure(GPIO_PF2_SSI1CLK);
MAP_GPIOPinConfigure(GPIO_PF1_SSI1TX);
MAP_GPIOPinTypeSSI(GPIO_PORTF_BASE, GPIO_PIN_2 | GPIO_PIN_1);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
MAP_GPIOPinConfigure(GPIO_PB4_SSI2CLK);
MAP_GPIOPinConfigure(GPIO_PB7_SSI2TX);
MAP_GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_7);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
MAP_GPIOPinConfigure(GPIO_PD0_SSI3CLK);
MAP_GPIOPinConfigure(GPIO_PD3_SSI3TX);
MAP_GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_3);
/* Configure SSI0..3 for the ws2801's SPI-like protocol */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2);
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3);
MAP_SSIConfigSetExpClk(SSI0_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16);
MAP_SSIConfigSetExpClk(SSI1_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16);
MAP_SSIConfigSetExpClk(SSI2_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16);
MAP_SSIConfigSetExpClk(SSI3_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SPI_SPEED, 16);
/* Configure the µDMA controller for use by the SPI interface */
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
MAP_SysCtlPeripheralSleepEnable(SYSCTL_PERIPH_UDMA);
// FIXME what do we need this for? IntEnable(INT_UDMAERR); // Enable µDMA error interrupt
MAP_uDMAEnable();
MAP_uDMAControlBaseSet(ucControlTable);
MAP_uDMAChannelAssign(UDMA_CH11_SSI0TX);
MAP_uDMAChannelAssign(UDMA_CH25_SSI1TX);
MAP_uDMAChannelAssign(UDMA_CH13_SSI2TX);
MAP_uDMAChannelAssign(UDMA_CH15_SSI3TX);
ssi_udma_channel_config(11);
ssi_udma_channel_config(25);
ssi_udma_channel_config(13);
ssi_udma_channel_config(15);
MAP_SSIDMAEnable(SSI0_BASE, SSI_DMA_TX);
MAP_SSIDMAEnable(SSI1_BASE, SSI_DMA_TX);
MAP_SSIDMAEnable(SSI2_BASE, SSI_DMA_TX);
MAP_SSIDMAEnable(SSI3_BASE, SSI_DMA_TX);
/* Enable the SSIs after configuring anything around them. */
MAP_SSIEnable(SSI0_BASE);
MAP_SSIEnable(SSI1_BASE);
MAP_SSIEnable(SSI2_BASE);
MAP_SSIEnable(SSI3_BASE);
}
//*****************************************************************************
//
//! Initializes the UART0 peripheral and sets up the TX and RX uDMA channels.
//! The UART is configured for loopback mode so that any data sent on TX will be
//! received on RX. The uDMA channels are configured so that the TX channel
//! will copy data from a buffer to the UART TX output. And the uDMA RX channel
//! will receive any incoming data into a pair of buffers in ping-pong mode.
//!
//! \param None
//!
//! \return None
//!
//*****************************************************************************
void
InitUART0Transfer(void)
{
unsigned int uIdx;
//
// Fill the TX buffer with a simple data pattern.
//
for(uIdx = 0; uIdx < UART_TXBUF_SIZE; uIdx++)
{
g_ucTxBuf[uIdx] = 65;
}
MAP_PRCMPeripheralReset(PRCM_UARTA0);
MAP_PRCMPeripheralClkEnable(PRCM_UARTA0,PRCM_RUN_MODE_CLK);
MAP_UARTConfigSetExpClk(CONSOLE,SYSCLK, UART_BAUD_RATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));
MAP_uDMAChannelAssign(UDMA_CH8_UARTA0_RX);
MAP_uDMAChannelAssign(UDMA_CH9_UARTA0_TX);
MAP_UARTIntRegister(UARTA0_BASE,UART0IntHandler);
//
// Set both the TX and RX trigger thresholds to 4. This will be used by
// the uDMA controller to signal when more data should be transferred. The
// uDMA TX and RX channels will be configured so that it can transfer 4
// bytes in a burst when the UART is ready to transfer more data.
//
MAP_UARTFIFOLevelSet(UARTA0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
//
// Enable the UART for operation, and enable the uDMA interface for both TX
// and RX channels.
//
MAP_UARTEnable(UARTA0_BASE);
//
// This register write will set the UART to operate in loopback mode. Any
// data sent on the TX output will be received on the RX input.
//
HWREG(UARTA0_BASE + UART_O_CTL) |= UART_CTL_LBE;
//
// Enable the UART peripheral interrupts. uDMA controller will cause an
// interrupt on the UART interrupt signal when a uDMA transfer is complete.
//
MAP_UARTIntEnable(UARTA0_BASE,UART_INT_DMATX);
MAP_UARTIntEnable(UARTA0_BASE,UART_INT_DMARX);
//
// Configure the control parameters for the UART TX. The uDMA UART TX
// channel is used to transfer a block of data from a buffer to the UART.
// The data size is 8 bits. The source address increment is 8-bit bytes
// since the data is coming from a buffer. The destination increment is
// none since the data is to be written to the UART data register. The
// arbitration size is set to 4, which matches the UART TX FIFO trigger
// threshold.
//
UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG,
sizeof(g_ucRxBufA),UDMA_SIZE_8, UDMA_ARB_4,
(void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE,
g_ucRxBufA, UDMA_DST_INC_8);
UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG,
sizeof(g_ucRxBufB),UDMA_SIZE_8, UDMA_ARB_4,
(void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE,
g_ucRxBufB, UDMA_DST_INC_8);
UDMASetupTransfer(UDMA_CH9_UARTA0_TX| UDMA_PRI_SELECT,
UDMA_MODE_BASIC,sizeof(g_ucTxBuf),UDMA_SIZE_8, UDMA_ARB_4,
g_ucTxBuf, UDMA_SRC_INC_8,(void *)(UARTA0_BASE + UART_O_DR),
UDMA_DST_INC_NONE);
MAP_UARTDMAEnable(UARTA0_BASE, UART_DMA_RX | UART_DMA_TX);
}
/*
* ======== SPICC3200DMA_configDMA ========
* This functions configures the transmit and receive DMA channels for a given
* SPI_Handle and SPI_Transaction
*
* @pre Function assumes that the handle and transaction is not NULL
*/
static void SPICC3200DMA_configDMA(SPI_Handle handle, SPI_Transaction *transaction)
{
uintptr_t key;
SPIDataType dummy;
void *buf;
uint32_t channelControlOptions;
SPICC3200DMA_Object *object = handle->object;
SPICC3200DMA_HWAttrs const *hwAttrs = handle->hwAttrs;
/* Clear out the FIFO */
while (MAP_SPIDataGetNonBlocking(hwAttrs->baseAddr, &dummy)) {}
/* Configure DMA for RX */
MAP_uDMAChannelAssign(hwAttrs->rxChannelIndex);
MAP_uDMAChannelAttributeDisable(hwAttrs->rxChannelIndex, UDMA_ATTR_ALTSELECT);
if (transaction->rxBuf) {
channelControlOptions = dmaRxConfig[object->frameSize];
buf = transaction->rxBuf;
}
else {
channelControlOptions = dmaNullConfig[object->frameSize];
buf = hwAttrs->scratchBufPtr;
}
MAP_uDMAChannelControlSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT,
channelControlOptions);
MAP_uDMAChannelTransferSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *)(hwAttrs->baseAddr + MCSPI_O_RX0),
buf,
transaction->count);
/* Configure DMA for TX */
MAP_uDMAChannelAssign(hwAttrs->txChannelIndex);
MAP_uDMAChannelAttributeDisable(hwAttrs->txChannelIndex, UDMA_ATTR_ALTSELECT);
if (transaction->txBuf) {
channelControlOptions = dmaTxConfig[object->frameSize];
buf = transaction->txBuf;
}
else {
channelControlOptions = dmaNullConfig[object->frameSize];
*hwAttrs->scratchBufPtr = hwAttrs->defaultTxBufValue;
buf = hwAttrs->scratchBufPtr;
}
MAP_uDMAChannelControlSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT,
channelControlOptions);
MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
buf,
(void *)(hwAttrs->baseAddr + MCSPI_O_TX0),
transaction->count);
DebugP_log1("SPI:(%p) DMA transfer enabled", hwAttrs->baseAddr);
DebugP_log4("SPI: DMA transaction: %p, rxBuf: %p; txBuf: %p; Count: %d",
(uintptr_t)transaction, (uintptr_t)transaction->rxBuf,
(uintptr_t)transaction->txBuf, (uintptr_t)transaction->count);
key = HwiP_disable();
MAP_uDMAChannelEnable(hwAttrs->rxChannelIndex);
MAP_uDMAChannelEnable(hwAttrs->txChannelIndex);
HwiP_restore(key);
MAP_SPIWordCountSet(hwAttrs->baseAddr, transaction->count);
}