static bool printSparcAliasInstr(MCInst *MI, SStream *O)
{
switch (MCInst_getOpcode(MI)) {
default: return false;
case SP_JMPLrr:
case SP_JMPLri:
if (MCInst_getNumOperands(MI) != 3)
return false;
if (!MCOperand_isReg(MCInst_getOperand(MI, 0)))
return false;
switch (MCOperand_getReg(MCInst_getOperand(MI, 0))) {
default: return false;
case SP_G0: // jmp $addr | ret | retl
if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
switch(MCOperand_getReg(MCInst_getOperand(MI, 1))) {
default: break;
case SP_I7: SStream_concat0(O, "ret"); MCInst_setOpcodePub(MI, SPARC_INS_RET); return true;
case SP_O7: SStream_concat0(O, "retl"); MCInst_setOpcodePub(MI, SPARC_INS_RETL); return true;
}
}
SStream_concat0(O, "jmp\t");
MCInst_setOpcodePub(MI, SPARC_INS_JMP);
printMemOperand(MI, 1, O, NULL);
return true;
case SP_O7: // call $addr
SStream_concat0(O, "call ");
MCInst_setOpcodePub(MI, SPARC_INS_CALL);
printMemOperand(MI, 1, O, NULL);
return true;
}
case SP_V9FCMPS:
case SP_V9FCMPD:
case SP_V9FCMPQ:
case SP_V9FCMPES:
case SP_V9FCMPED:
case SP_V9FCMPEQ:
if (MI->csh->mode & CS_MODE_V9 || (MCInst_getNumOperands(MI) != 3) ||
(!MCOperand_isReg(MCInst_getOperand(MI, 0))) ||
(MCOperand_getReg(MCInst_getOperand(MI, 0)) != SP_FCC0))
return false;
// if V8, skip printing %fcc0.
switch(MCInst_getOpcode(MI)) {
default:
case SP_V9FCMPS: SStream_concat0(O, "fcmps\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPS); break;
case SP_V9FCMPD: SStream_concat0(O, "fcmpd\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPD); break;
case SP_V9FCMPQ: SStream_concat0(O, "fcmpq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPQ); break;
case SP_V9FCMPES: SStream_concat0(O, "fcmpes\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPES); break;
case SP_V9FCMPED: SStream_concat0(O, "fcmped\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPED); break;
case SP_V9FCMPEQ: SStream_concat0(O, "fcmpeq\t"); MCInst_setOpcodePub(MI, SPARC_INS_FCMPEQ); break;
}
printOperand(MI, 1, O);
SStream_concat0(O, ", ");
printOperand(MI, 2, O);
return true;
}
}
static void printPostIncOperand(MCInst *MI, unsigned OpNo,
unsigned Imm, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned Reg = MCOperand_getReg(Op);
if (Reg == AArch64_XZR) {
printInt32Bang(O, Imm);
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm;
MI->flat_insn->detail->arm64.op_count++;
}
} else {
SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
MI->flat_insn->detail->arm64.op_count++;
}
}
}
//llvm_unreachable("unknown operand kind in printPostIncOperand64");
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
if (MI->detail) {
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_REG;
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].reg = MCOperand_getReg(Op);
MI->pub_insn.x86.op_count++;
}
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
} else {
if (imm <= -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
}
if (MI->detail) {
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].type = X86_OP_IMM;
MI->pub_insn.x86.operands[MI->pub_insn.x86.op_count].imm = imm;
MI->pub_insn.x86.op_count++;
}
}
}
static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier)
{
MCOperand *MO;
set_mem_access(MI, true);
printOperand(MI, opNum, O);
// If this is an ADD operand, emit it like normal operands.
if (Modifier && !strcmp(Modifier, "arith")) {
SStream_concat0(O, ", ");
printOperand(MI, opNum + 1, O);
set_mem_access(MI, false);
return;
}
MO = MCInst_getOperand(MI, opNum + 1);
if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) {
set_mem_access(MI, false);
return; // don't print "+%g0"
}
if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) {
set_mem_access(MI, false);
return; // don't print "+0"
}
SStream_concat0(O, "+"); // qq
printOperand(MI, opNum + 1, O);
set_mem_access(MI, false);
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = MCOperand_getReg(Op);
MI->flat_insn->detail->x86.op_count++;
}
} else if (MCOperand_isImm(Op)) {
// Print X86 immediates as signed values.
int64_t imm = MCOperand_getImm(Op);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "%s$0x%"PRIx64"%s", markup("<imm:"), imm, markup(">"));
else
SStream_concat(O, "%s$%"PRIu64"%s", markup("<imm:"), imm, markup(">"));
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "%s$-0x%"PRIx64"%s", markup("<imm:"), -imm, markup(">"));
else
SStream_concat(O, "%s$-%"PRIu64"%s", markup("<imm:"), -imm, markup(">"));
}
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
MI->flat_insn->detail->x86.op_count++;
}
}
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = reg;
} else {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg];
MI->flat_insn->detail->x86.op_count++;
}
}
} else if (MCOperand_isImm(Op)) {
// Print X86 immediates as signed values.
int64_t imm = MCOperand_getImm(Op);
switch(MI->flat_insn->id) {
default:
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "$0x%"PRIx64, imm);
else
SStream_concat(O, "$%"PRIu64, imm);
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "$-0x%"PRIx64, -imm);
else
SStream_concat(O, "$-%"PRIu64, -imm);
}
break;
case X86_INS_RET:
// RET imm16
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "$%u", imm);
else {
imm = 0xffff & imm;
SStream_concat(O, "$0x%x", imm);
}
break;
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
} else {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->has_imm = true;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
MI->flat_insn->detail->x86.op_count++;
}
}
}
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
reg = Mips_map_register(reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.base = reg;
} else {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_REG;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].reg = reg;
MI->flat_insn.mips.op_count++;
}
}
}
if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
if (MI->csh->doing_mem) {
if (imm) { // only print Imm offset if it is not 0
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
} else {
if (imm <= -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
}
}
if (MI->csh->detail)
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].mem.disp = imm;
} else {
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
} else {
if (imm <= -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
}
if (MI->csh->detail) {
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].type = MIPS_OP_IMM;
MI->flat_insn.mips.operands[MI->flat_insn.mips.op_count].imm = imm;
MI->flat_insn.mips.op_count++;
}
}
}
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned reg = MCOperand_getReg(Op);
#ifndef CAPSTONE_DIET
char *RegName = getRegisterName(reg);
#endif
// map to public register
reg = PPC_map_register(reg);
#ifndef CAPSTONE_DIET
// The linux and AIX assembler does not take register prefixes.
if (MI->csh->syntax == CS_OPT_SYNTAX_NOREGNAME)
RegName = stripRegisterPrefix(RegName);
SStream_concat0(O, RegName);
#endif
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg;
} else {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
MI->flat_insn->detail->ppc.op_count++;
}
}
return;
}
if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%" PRIx64, imm);
else
SStream_concat(O, "%" PRIu64 , imm);
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%" PRIx64 , -imm);
else
SStream_concat(O, "-%" PRIu64 , -imm);
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = imm;
} else {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
MI->flat_insn->detail->ppc.op_count++;
}
}
}
}
// local printOperand, without updating public operands
static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
printImm(MI->csh->syntax, O, imm, false);
}
}
static void printSaveRestore(MCInst *MI, SStream *O)
{
unsigned i, e;
for (i = 0, e = MCInst_getNumOperands(MI); i != e; ++i) {
if (i != 0)
SStream_concat(O, ", ");
if (MCOperand_isReg(MCInst_getOperand(MI, i)))
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, i)));
else
printUnsignedImm(MI, i, O);
}
}
static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
{
if (MCOperand_isReg(MO)) {
unsigned reg;
reg = MCOperand_getReg(MO);
SStream_concat0(O, getRegisterName(reg));
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base == ARM_REG_INVALID)
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = reg;
else
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = reg;
} else {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = reg;
MI->flat_insn->detail->xcore.op_count++;
}
}
} else if (MCOperand_isImm(MO)) {
int32_t Imm = (int32_t)MCOperand_getImm(MO);
if (Imm >= 0) {
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Imm);
else
SStream_concat(O, "%u", Imm);
} else {
if (Imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%x", -Imm);
else
SStream_concat(O, "-%u", -Imm);
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = Imm;
} else {
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_IMM;
MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].imm = Imm;
MI->flat_insn->detail->xcore.op_count++;
}
}
}
}
// local printOperand, without updating public operands
static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
} else if (MCOperand_isImm(Op)) {
uint8_t encsize;
uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize);
// Print X86 immediates as signed values.
int64_t imm = MCOperand_getImm(Op);
if (imm < 0) {
if (MI->csh->imm_unsigned) {
if (opsize) {
switch(opsize) {
default:
break;
case 1:
imm &= 0xff;
break;
case 2:
imm &= 0xffff;
break;
case 4:
imm &= 0xffffffff;
break;
}
}
SStream_concat(O, "$0x%"PRIx64, imm);
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "$-0x%"PRIx64, -imm);
else
SStream_concat(O, "$-%"PRIu64, -imm);
}
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "$0x%"PRIx64, imm);
else
SStream_concat(O, "$%"PRIu64, imm);
}
}
}
// local printOperand, without updating public operands
static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
if (imm < 0) {
if (imm <= -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
}
}
}
// local printOperand, without updating public operands
static void _printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
} else if (MCOperand_isImm(Op)) {
// Print X86 immediates as signed values.
int64_t imm = MCOperand_getImm(Op);
if (imm < 0) {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "$-0x%"PRIx64, -imm);
else
SStream_concat(O, "$-%"PRIu64, -imm);
} else {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "$0x%"PRIx64, imm);
else
SStream_concat(O, "$%"PRIu64, imm);
}
}
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned Reg = MCOperand_getReg(Op);
SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = Reg;
}
else if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index == ARM64_REG_INVALID) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg;
}
} else {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
MI->flat_insn->detail->arm64.op_count++;
}
}
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
if (MI->Opcode == AArch64_ADR) {
imm += MI->address;
printUInt64Bang(O, imm);
} else
printUInt64Bang(O, imm);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm;
} else {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
MI->flat_insn->detail->arm64.op_count++;
}
}
}
}
static void _printOperand(MCInst *MI, MCOperand *MO, SStream *O)
{
if (MCOperand_isReg(MO)) {
unsigned reg;
reg = MCOperand_getReg(MO);
SStream_concat(O, "%%%s", getRegisterName(reg));
reg = SystemZ_map_register(reg);
if (MI->csh->detail) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_REG;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].reg = reg;
MI->flat_insn->detail->sysz.op_count++;
}
} else if (MCOperand_isImm(MO)) {
int64_t Imm = MCOperand_getImm(MO);
if (Imm >= 0) {
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, Imm);
else
SStream_concat(O, "%"PRIu64, Imm);
} else {
if (Imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -Imm);
else
SStream_concat(O, "-%"PRIu64, -Imm);
}
if (MI->csh->detail) {
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM;
MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Imm;
MI->flat_insn->detail->sysz.op_count++;
}
}
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
int opsize = 0;
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = reg;
} else {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg];
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
MI->flat_insn->detail->x86.op_count++;
}
}
if (MI->op1_size == 0)
MI->op1_size = MI->csh->regsize_map[reg];
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
switch(MCInst_getOpcode(MI)) {
default:
break;
case X86_AAD8i8:
case X86_AAM8i8:
case X86_ADC8i8:
case X86_ADD8i8:
case X86_AND8i8:
case X86_CMP8i8:
case X86_OR8i8:
case X86_SBB8i8:
case X86_SUB8i8:
case X86_TEST8i8:
case X86_XOR8i8:
case X86_ROL8ri:
case X86_ADC8ri:
case X86_ADC8ri8:
case X86_ADD8ri:
case X86_ADD8ri8:
case X86_AND8ri:
case X86_AND8ri8:
case X86_CMP8ri:
case X86_CMP8ri8:
case X86_IN8ri:
case X86_MOV8ri:
case X86_MOV8ri_alt:
case X86_OR8ri:
case X86_OR8ri8:
case X86_RCL8ri:
case X86_RCR8ri:
case X86_ROR8ri:
case X86_SAL8ri:
case X86_SAR8ri:
case X86_SBB8ri:
case X86_SBB8ri8:
case X86_SHL8ri:
case X86_SHR8ri:
case X86_SUB8ri:
case X86_SUB8ri8:
case X86_TEST8ri:
case X86_TEST8ri_NOREX:
case X86_TEST8ri_alt:
case X86_XOR8ri:
case X86_XOR8ri8:
case X86_OUT8ir:
case X86_ADC8mi:
case X86_ADC8mi8:
case X86_ADD8mi:
case X86_ADD8mi8:
case X86_AND8mi:
case X86_AND8mi8:
case X86_CMP8mi:
case X86_CMP8mi8:
case X86_LOCK_ADD8mi:
case X86_LOCK_AND8mi:
case X86_LOCK_OR8mi:
case X86_LOCK_SUB8mi:
case X86_LOCK_XOR8mi:
case X86_MOV8mi:
case X86_OR8mi:
case X86_OR8mi8:
case X86_RCL8mi:
case X86_RCR8mi:
case X86_ROL8mi:
case X86_ROR8mi:
case X86_SAL8mi:
case X86_SAR8mi:
case X86_SBB8mi:
case X86_SBB8mi8:
case X86_SHL8mi:
case X86_SHR8mi:
case X86_SUB8mi:
case X86_SUB8mi8:
case X86_TEST8mi:
case X86_TEST8mi_alt:
case X86_XOR8mi:
case X86_XOR8mi8:
case X86_PUSH64i8:
case X86_CMP32ri8:
case X86_CMP64ri8:
imm = imm & 0xff;
opsize = 1; // immediate of 1 byte
break;
}
switch(MI->flat_insn->id) {
default:
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
}
break;
case X86_INS_INT:
// do not print number in negative form
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "%u", imm);
else
SStream_concat(O, "0x%x", imm & 0xff);
break;
case X86_INS_AND:
case X86_INS_OR:
case X86_INS_XOR:
// do not print number in negative form
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "%u", imm);
else
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->op1_size? MI->op1_size : MI->imm_size] & imm);
break;
case X86_INS_RET:
// RET imm16
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "%u", imm);
else {
imm = 0xffff & imm;
SStream_concat(O, "0x%x", 0xffff & imm);
}
break;
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
} else {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
if (opsize > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize;
else if (MI->flat_insn->detail->x86.op_count > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size;
else
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
MI->flat_insn->detail->x86.op_count++;
}
}
//if (MI->op1_size == 0)
// MI->op1_size = MI->imm_size;
}
}
static void printOperand(MCInst *MI, int opNum, SStream *O)
{
int Imm;
unsigned reg;
MCOperand *MO = MCInst_getOperand(MI, opNum);
if (MCOperand_isReg(MO)) {
reg = MCOperand_getReg(MO);
printRegName(O, reg);
reg = Sparc_map_register(reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
if (MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base)
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.index = reg;
else
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.base = reg;
} else {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg;
MI->flat_insn->detail->sparc.op_count++;
}
}
return;
}
if (MCOperand_isImm(MO)) {
Imm = (int)MCOperand_getImm(MO);
// Conditional branches displacements needs to be signextended to be
// able to jump backwards.
//
// Displacements are measured as the number of instructions forward or
// backward, so they need to be multiplied by 4
switch (MI->Opcode) {
case SP_CALL:
Imm = SignExtend32(Imm, 30);
Imm += (uint32_t)MI->address;
break;
// Branch on integer condition with prediction (BPcc)
// Branch on floating point condition with prediction (FBPfcc)
case SP_BPICC:
case SP_BPICCA:
case SP_BPICCANT:
case SP_BPICCNT:
case SP_BPXCC:
case SP_BPXCCA:
case SP_BPXCCANT:
case SP_BPXCCNT:
case SP_BPFCC:
case SP_BPFCCA:
case SP_BPFCCANT:
case SP_BPFCCNT:
Imm = SignExtend32(Imm, 19);
Imm = (uint32_t)MI->address + Imm * 4;
break;
// Branch on integer condition (Bicc)
// Branch on floating point condition (FBfcc)
case SP_BA:
case SP_BCOND:
case SP_BCONDA:
case SP_FBCOND:
case SP_FBCONDA:
Imm = SignExtend32(Imm, 22);
Imm = (uint32_t)MI->address + Imm * 4;
break;
// Branch on integer register with prediction (BPr)
case SP_BPGEZapn:
case SP_BPGEZapt:
case SP_BPGEZnapn:
case SP_BPGEZnapt:
case SP_BPGZapn:
case SP_BPGZapt:
case SP_BPGZnapn:
case SP_BPGZnapt:
case SP_BPLEZapn:
case SP_BPLEZapt:
case SP_BPLEZnapn:
case SP_BPLEZnapt:
case SP_BPLZapn:
case SP_BPLZapt:
case SP_BPLZnapn:
case SP_BPLZnapt:
case SP_BPNZapn:
case SP_BPNZapt:
case SP_BPNZnapn:
case SP_BPNZnapt:
case SP_BPZapn:
case SP_BPZapt:
case SP_BPZnapn:
case SP_BPZnapt:
Imm = SignExtend32(Imm, 16);
Imm = (uint32_t)MI->address + Imm * 4;
break;
}
if (Imm >= 0) {
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", Imm);
else
SStream_concat(O, "%u", Imm);
} else {
if (Imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%x", -Imm);
else
SStream_concat(O, "-%u", -Imm);
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].mem.disp = Imm;
} else {
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_IMM;
MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].imm = Imm;
MI->flat_insn->detail->sparc.op_count++;
}
}
}
return;
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = reg;
} else {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg];
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
MI->flat_insn->detail->x86.op_count++;
}
}
if (MI->op1_size == 0)
MI->op1_size = MI->csh->regsize_map[reg];
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
int opsize = X86_immediate_size(MCInst_getOpcode(MI));
if (opsize == 1) // print 1 byte immediate in positive form
imm = imm & 0xff;
switch(MI->flat_insn->id) {
default:
printImm(MI->csh->syntax, O, imm, false);
break;
case X86_INS_INT:
// do not print number in negative form
imm = imm & 0xff;
printImm(MI->csh->syntax, O, imm, true);
break;
case X86_INS_LCALL:
case X86_INS_LJMP:
// always print address in positive form
if (OpNo == 1) { // ptr16 part
imm = imm & 0xffff;
opsize = 2;
}
printImm(MI->csh->syntax, O, imm, true);
break;
case X86_INS_AND:
case X86_INS_OR:
case X86_INS_XOR:
// do not print number in negative form
if (imm >= 0 && imm <= HEX_THRESHOLD)
printImm(MI->csh->syntax, O, imm, true);
else {
imm = arch_masks[opsize? opsize : MI->imm_size] & imm;
printImm(MI->csh->syntax, O, imm, true);
}
break;
case X86_INS_RET:
// RET imm16
if (imm >= 0 && imm <= HEX_THRESHOLD)
printImm(MI->csh->syntax, O, imm, true);
else {
imm = 0xffff & imm;
printImm(MI->csh->syntax, O, imm, true);
}
break;
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
} else {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
if (opsize > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize;
else if (MI->flat_insn->detail->x86.op_count > 0) {
if (MI->flat_insn->id != X86_INS_LCALL && MI->flat_insn->id != X86_INS_LJMP) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size =
MI->flat_insn->detail->x86.operands[0].size;
} else
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
} else
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
MI->flat_insn->detail->x86.op_count++;
}
}
}
}
static bool isReg(MCInst *MI, unsigned OpNo, unsigned R)
{
return (MCOperand_isReg(MCInst_getOperand(MI, OpNo)) &&
MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R);
}
static char *printAliasInstrEx(MCInst *MI, SStream *OS, void *info)
{
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
SStream ss;
const char *opCode;
char *tmp, *AsmMnem, *AsmOps, *c;
int OpIdx, PrintMethodIdx;
int decCtr = false, needComma = false;
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
SStream_Init(&ss);
switch (MCInst_getOpcode(MI)) {
default: return NULL;
case PPC_gBC:
opCode = "b%s";
break;
case PPC_gBCA:
opCode = "b%sa";
break;
case PPC_gBCCTR:
opCode = "b%sctr";
break;
case PPC_gBCCTRL:
opCode = "b%sctrl";
break;
case PPC_gBCL:
opCode = "b%sl";
break;
case PPC_gBCLA:
opCode = "b%sla";
break;
case PPC_gBCLR:
opCode = "b%slr";
break;
case PPC_gBCLRL:
opCode = "b%slrl";
break;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 0) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 1)) {
SStream_concat(&ss, opCode, "dnzf");
decCtr = true;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 2) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 3)) {
SStream_concat(&ss, opCode, "dzf");
decCtr = true;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 4) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 7) &&
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
switch(cr) {
case CREQ:
SStream_concat(&ss, opCode, "ne");
break;
case CRGT:
SStream_concat(&ss, opCode, "le");
break;
case CRLT:
SStream_concat(&ss, opCode, "ge");
break;
case CRUN:
SStream_concat(&ss, opCode, "ns");
break;
}
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6)
SStream_concat0(&ss, "-");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7)
SStream_concat0(&ss, "+");
decCtr = false;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 8) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 9)) {
SStream_concat(&ss, opCode, "dnzt");
decCtr = true;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 10) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 11)) {
SStream_concat(&ss, opCode, "dzt");
decCtr = true;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 12) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 15) &&
MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
switch(cr) {
case CREQ:
SStream_concat(&ss, opCode, "eq");
break;
case CRGT:
SStream_concat(&ss, opCode, "gt");
break;
case CRLT:
SStream_concat(&ss, opCode, "lt");
break;
case CRUN:
SStream_concat(&ss, opCode, "so");
break;
}
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14)
SStream_concat0(&ss, "-");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15)
SStream_concat0(&ss, "+");
decCtr = false;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 16)) {
SStream_concat(&ss, opCode, "dnz");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24)
SStream_concat0(&ss, "-");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 25)
SStream_concat0(&ss, "+");
needComma = false;
}
if (MCInst_getNumOperands(MI) == 3 &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 18)) {
SStream_concat(&ss, opCode, "dz");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 26)
SStream_concat0(&ss, "-");
if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 27)
SStream_concat0(&ss, "+");
needComma = false;
}
if (MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
(MCOperand_getImm(MCInst_getOperand(MI, 0)) < 16)) {
int cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1)));
if (decCtr) {
needComma = true;
SStream_concat0(&ss, " ");
if (cr > PPC_CR0) {
SStream_concat(&ss, "4*cr%d+", cr - PPC_CR0);
}
cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
switch(cr) {
case CREQ:
SStream_concat0(&ss, "eq");
op_addBC(MI, PPC_BC_EQ);
break;
case CRGT:
SStream_concat0(&ss, "gt");
op_addBC(MI, PPC_BC_GT);
break;
case CRLT:
SStream_concat0(&ss, "lt");
op_addBC(MI, PPC_BC_LT);
break;
case CRUN:
SStream_concat0(&ss, "so");
op_addBC(MI, PPC_BC_SO);
break;
}
cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1)));
if (cr > PPC_CR0) {
if (MI->csh->detail) {
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_CRX;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.scale = 4;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.reg = PPC_REG_CR0 + cr - PPC_CR0;
MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].crx.cond = MI->flat_insn->detail->ppc.bc;
MI->flat_insn->detail->ppc.op_count++;
}
}
} else {
if (cr > PPC_CR0) {
needComma = true;
SStream_concat(&ss, " cr%d", cr - PPC_CR0);
op_addReg(MI, PPC_REG_CR0 + cr - PPC_CR0);
}
}
}
if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
MCOperand_getImm(MCInst_getOperand(MI, 2)) != 0) {
if (needComma)
SStream_concat0(&ss, ",");
SStream_concat0(&ss, " $\xFF\x03\x01");
}
tmp = cs_strdup(ss.buffer);
AsmMnem = tmp;
for(AsmOps = tmp; *AsmOps; AsmOps++) {
if (*AsmOps == ' ' || *AsmOps == '\t') {
*AsmOps = '\0';
AsmOps++;
break;
}
}
SStream_concat0(OS, AsmMnem);
if (*AsmOps) {
SStream_concat0(OS, "\t");
for (c = AsmOps; *c; c++) {
if (*c == '$') {
c += 1;
if (*c == (char)0xff) {
c += 1;
OpIdx = *c - 1;
c += 1;
PrintMethodIdx = *c - 1;
printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
} else
printOperand(MI, *c - 1, OS);
} else {
SStream_concat(OS, "%c", *c);
}
}
}
return tmp;
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = reg;
} else {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg];
MI->flat_insn->detail->x86.op_count++;
}
}
if (MI->op1_size == 0)
MI->op1_size = MI->csh->regsize_map[reg];
} else if (MCOperand_isImm(Op)) {
int64_t imm = MCOperand_getImm(Op);
switch(MI->flat_insn->id) {
default:
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%"PRIx64, imm);
else
SStream_concat(O, "%"PRIu64, imm);
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%"PRIx64, -imm);
else
SStream_concat(O, "-%"PRIu64, -imm);
}
break;
case X86_INS_AND:
case X86_INS_OR:
case X86_INS_XOR:
// do not print number in negative form
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "%u", imm);
else
SStream_concat(O, "0x%"PRIx64, arch_masks[MI->op1_size? MI->op1_size : MI->imm_size] & imm);
break;
case X86_INS_RET:
// RET imm16
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "%u", imm);
else {
imm = 0xffff & imm;
SStream_concat(O, "0x%x", 0xffff & imm);
}
break;
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
} else {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
if (MI->flat_insn->detail->x86.op_count > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->flat_insn->detail->x86.operands[0].size;
else
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
MI->flat_insn->detail->x86.op_count++;
}
}
//if (MI->op1_size == 0)
// MI->op1_size = MI->imm_size;
}
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
uint8_t opsize = 0;
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = reg;
} else {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg];
MI->flat_insn->detail->x86.op_count++;
}
}
} else if (MCOperand_isImm(Op)) {
// Print X86 immediates as signed values.
int64_t imm = MCOperand_getImm(Op);
switch(MCInst_getOpcode(MI)) {
default:
break;
case X86_AAD8i8:
case X86_AAM8i8:
case X86_ADC8i8:
case X86_ADD8i8:
case X86_AND8i8:
case X86_CMP8i8:
case X86_OR8i8:
case X86_SBB8i8:
case X86_SUB8i8:
case X86_TEST8i8:
case X86_XOR8i8:
case X86_ROL8ri:
case X86_ADC8ri:
case X86_ADD8ri:
case X86_ADD8ri8:
case X86_AND8ri:
case X86_AND8ri8:
case X86_CMP8ri:
case X86_MOV8ri:
case X86_MOV8ri_alt:
case X86_OR8ri:
case X86_OR8ri8:
case X86_RCL8ri:
case X86_RCR8ri:
case X86_ROR8ri:
case X86_SAL8ri:
case X86_SAR8ri:
case X86_SBB8ri:
case X86_SHL8ri:
case X86_SHR8ri:
case X86_SUB8ri:
case X86_SUB8ri8:
case X86_TEST8ri:
case X86_TEST8ri_NOREX:
case X86_TEST8ri_alt:
case X86_XOR8ri:
case X86_XOR8ri8:
case X86_OUT8ir:
case X86_ADC8mi:
case X86_ADD8mi:
case X86_AND8mi:
case X86_CMP8mi:
case X86_LOCK_ADD8mi:
case X86_LOCK_AND8mi:
case X86_LOCK_OR8mi:
case X86_LOCK_SUB8mi:
case X86_LOCK_XOR8mi:
case X86_MOV8mi:
case X86_OR8mi:
case X86_RCL8mi:
case X86_RCR8mi:
case X86_ROL8mi:
case X86_ROR8mi:
case X86_SAL8mi:
case X86_SAR8mi:
case X86_SBB8mi:
case X86_SHL8mi:
case X86_SHR8mi:
case X86_SUB8mi:
case X86_TEST8mi:
case X86_TEST8mi_alt:
case X86_XOR8mi:
case X86_PUSH64i8:
case X86_CMP32ri8:
case X86_CMP64ri8:
imm = imm & 0xff;
opsize = 1; // immediate of 1 byte
break;
}
switch(MI->flat_insn->id) {
default:
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "$0x%"PRIx64, imm);
else
SStream_concat(O, "$%"PRIu64, imm);
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "$-0x%"PRIx64, -imm);
else
SStream_concat(O, "$-%"PRIu64, -imm);
}
break;
case X86_INS_INT:
// do not print number in negative form
imm = imm & 0xff;
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "$%u", imm);
else {
SStream_concat(O, "$0x%x", imm);
}
break;
case X86_INS_LCALL:
case X86_INS_LJMP:
// always print address in positive form
if (OpNo == 1) { // selector is ptr16
imm = imm & 0xffff;
opsize = 2;
}
SStream_concat(O, "$0x%"PRIx64, imm);
break;
case X86_INS_AND:
case X86_INS_OR:
case X86_INS_XOR:
// do not print number in negative form
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "$%u", imm);
else {
imm = arch_masks[MI->op1_size? MI->op1_size : MI->imm_size] & imm;
SStream_concat(O, "$0x%"PRIx64, imm);
}
break;
case X86_INS_RET:
// RET imm16
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "$%u", imm);
else {
imm = 0xffff & imm;
SStream_concat(O, "$0x%x", imm);
}
break;
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
} else {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->has_imm = true;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
if (opsize > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize;
else if (MI->op1_size > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->op1_size;
else
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
MI->flat_insn->detail->x86.op_count++;
}
}
}
}
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned int reg = MCOperand_getReg(Op);
printRegName(O, reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = reg;
} else {
uint8_t access[6];
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = reg;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->csh->regsize_map[reg];
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
MI->flat_insn->detail->x86.op_count++;
}
}
} else if (MCOperand_isImm(Op)) {
// Print X86 immediates as signed values.
uint8_t encsize;
int64_t imm = MCOperand_getImm(Op);
uint8_t opsize = X86_immediate_size(MCInst_getOpcode(MI), &encsize);
if (opsize == 1) // print 1 byte immediate in positive form
imm = imm & 0xff;
switch(MI->flat_insn->id) {
default:
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "$0x%"PRIx64, imm);
else
SStream_concat(O, "$%"PRIu64, imm);
} else {
if (MI->csh->imm_unsigned) {
if (opsize) {
switch(opsize) {
default:
break;
case 1:
imm &= 0xff;
break;
case 2:
imm &= 0xffff;
break;
case 4:
imm &= 0xffffffff;
break;
}
}
SStream_concat(O, "$0x%"PRIx64, imm);
} else {
if (imm == 0x8000000000000000LL) // imm == -imm
SStream_concat0(O, "$0x8000000000000000");
else if (imm < -HEX_THRESHOLD)
SStream_concat(O, "$-0x%"PRIx64, -imm);
else
SStream_concat(O, "$-%"PRIu64, -imm);
}
}
break;
case X86_INS_MOVABS:
// do not print number in negative form
SStream_concat(O, "$0x%"PRIx64, imm);
break;
case X86_INS_IN:
case X86_INS_OUT:
case X86_INS_INT:
// do not print number in negative form
imm = imm & 0xff;
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "$%u", imm);
else {
SStream_concat(O, "$0x%x", imm);
}
break;
case X86_INS_LCALL:
case X86_INS_LJMP:
// always print address in positive form
if (OpNo == 1) { // selector is ptr16
imm = imm & 0xffff;
opsize = 2;
}
SStream_concat(O, "$0x%"PRIx64, imm);
break;
case X86_INS_AND:
case X86_INS_OR:
case X86_INS_XOR:
// do not print number in negative form
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "$%u", imm);
else {
imm = arch_masks[opsize? opsize : MI->imm_size] & imm;
SStream_concat(O, "$0x%"PRIx64, imm);
}
break;
case X86_INS_RET:
case X86_INS_RETF:
// RET imm16
if (imm >= 0 && imm <= HEX_THRESHOLD)
SStream_concat(O, "$%u", imm);
else {
imm = 0xffff & imm;
SStream_concat(O, "$0x%x", imm);
}
break;
}
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm;
} else {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM;
MI->has_imm = true;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].imm = imm;
if (opsize > 0) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = opsize;
MI->flat_insn->detail->x86.encoding.imm_size = encsize;
} else if (MI->op1_size > 0)
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->op1_size;
else
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->imm_size;
MI->flat_insn->detail->x86.op_count++;
}
}
}
}
