static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
{
//MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
//return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
return rc->RegsBegin[RegNo];
}
static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas, arm64_vess vess)
{
#define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg)
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
unsigned NumRegs = 1, FirstReg, i;
SStream_concat0(O, "{");
// Work out how many registers there are in the list (if there is an actual
// list).
if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) ||
GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg))
NumRegs = 2;
else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) ||
GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg))
NumRegs = 3;
else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) ||
GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg))
NumRegs = 4;
// Now forget about the list and find out what the first register is.
if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_dsub0)))
Reg = FirstReg;
else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0)))
Reg = FirstReg;
// If it's a D-reg, we need to promote it to the equivalent Q-reg before
// printing (otherwise getRegisterName fails).
if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) {
MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID);
Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC);
}
for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) {
SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix);
if (i + 1 != NumRegs)
SStream_concat0(O, ", ");
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg);
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vess = vess;
MI->flat_insn->detail->arm64.op_count++;
}
}
SStream_concat0(O, "}");
}
static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
{
MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
return rc->RegsBegin[RegNo];
}
