void MDrv_Sys_WholeChipReset( void )
{
MDrv_Write4Byte(0xEA0, 0x51685168);
MDrv_WriteRegBit(0xE52, 1, BIT7);
MDrv_WriteRegBit(0xE52, 1, BIT6);
#if defined(CONFIG_MSTAR_EAGLE) || \
defined(CONFIG_MSTAR_AMETHYST) || \
defined(CONFIG_MSTAR_EMERALD) || \
defined(CONFIG_MSTAR_KAISERIN) || \
defined(CONFIG_MSTAR_KRONUS) || \
defined(CONFIG_MSTAR_KAISER) || \
defined(CONFIG_MSTAR_NUGGET) || \
defined(CONFIG_MSTAR_KENYA) || \
defined(CONFIG_MSTAR_KERES)
_MDrv_WriteByte( 0xE5C, 0x79 ); //PM_SLEEP (Bank 0x000E) for T13, A1, A6, A7, Amethyst, Eagle
#elif defined(CONFIG_MSTAR_NIKON)
_MDrv_WriteByte( 0x2E5C, 0xFF );
udelay(1);
_MDrv_WriteByte( 0x2E5C, 0x79 );
#else
#if defined(CONFIG_MSTAR_ROM_BOOT_WITH_EMMC_FLASH)
eMMC_RST_L();
eMMC_hw_timer_delay(HW_TIMER_DELAY_1ms);
eMMC_RST_H();
#endif
_MDrv_WriteByte( 0x2E5C, 0x79 ); //0x2E for T12, J2, A5, A3
//MDrv_WriteByte( 0xE5C, 0x79 ); //0xE for T13, A1, A6, A7
#endif
while(1);
}
static void MDrv_MOD_PowerDown(void)
{
MDrv_WriteRegBit(0x1031d8, 1, 0x08);
MDrv_WriteRegBit(0x1031d8, 1, 0x10);
MDrv_WriteRegBit(0x103106, 1, 0x20);
MDrv_WriteRegBit(0x103166, 1, 0x20);
MDrv_WriteRegBit(0x1032F0, 1, 0x01);
}
static void MDrv_MPLL_PowerDown(void)
{
MDrv_WriteByte(0x100b2c, 0x00); // patch for power saving (MPLL disable issue)
MDrv_WriteRegBit(0x100b20, 0, BIT0); // patch for power saving (MPLL disable issue)
MDrv_WriteRegBit(0x000f40, 0, BIT7); // patch for power saving (MPLL disable issue)
MDrv_WriteRegBit(0x110c03, 1, 0x01);
MDrv_WriteRegBit(0x110c43, 1, 0x01);
}
void MDrv_Sys_WholeChipReset( void )
{
MDrv_Write4Byte(0xEA0, 0x51685168);
MDrv_WriteRegBit(0xE52, 1, BIT7);
MDrv_WriteRegBit(0xE52, 1, BIT6);
#if defined(CONFIG_MSTAR_EAGLE) || defined(CONFIG_MSTAR_AMETHYST)
_MDrv_WriteByte( 0xE5C, 0x79 ); //PM_SLEEP (Bank 0x000E) for T13, A1, A6, A7, Amethyst, Eagle
#else
_MDrv_WriteByte( 0x2E5C, 0x79 ); //0x2E for T12, J2, A5, A3
//MDrv_WriteByte( 0xE5C, 0x79 ); //0xE for T13, A1, A6, A7
#endif
while(1);
}
static void MDrv_USBPLL_PowerDown(void)
{
MDrv_WriteRegBit(0x103A88, 1, BIT7);
MDrv_WriteByte(0x103A82, 0x80);
MDrv_WriteByte(0x103A83, 0x90);
MDrv_WriteByte(0x103A80, 0xC7);
MDrv_WriteByte(0x103A81, 0xEF);
}
static void MDrv_DDRPLL_PowerDown(void)
{
MDrv_WriteRegBit(0x110d00, 1, 0x08);
MDrv_WriteRegBit(0x110d00, 1, 0x10);
MDrv_WriteRegBit(0x110d01, 0, 0x04); //invert=Y
MDrv_WriteRegBit(0x110d01, 0, 0x08); //invert=Y
MDrv_WriteRegBit(0x110d01, 1, 0x80);
MDrv_WriteRegBit(0x110d08, 0, 0x3F); //invert=Y
MDrv_WriteRegBit(0x110d60, 1, 0x02);
MDrv_WriteRegBit(0x110d33, 1, 0x80);
}
static void MDrv_DSPPLL_PowerDown(void)
{
MDrv_WriteRegBit(0x110C43, 1, BIT0);
MDrv_WriteRegBit(0x110C43, 1, BIT1);
MDrv_WriteRegBit(0x110C43, 1, BIT2);
}
static void MDrv_AUSDM_PowerDown(void)
{
MDrv_WriteRegBit(0x112C20, 1, 0x08);
MDrv_WriteRegBit(0x112CDA, 1, 0x02);
MDrv_WriteRegBit(0x112CDA, 1, 0x01);
MDrv_WriteRegBit(0x112CDD, 1, 0x20);
MDrv_WriteRegBit(0x112CDD, 1, 0x10);
MDrv_WriteRegBit(0x112CDD, 1, 0x08);
MDrv_WriteRegBit(0x112CDD, 1, 0x04);
MDrv_WriteRegBit(0x112CDD, 1, 0x02);
MDrv_WriteRegBit(0x112CDD, 1, 0x01);
MDrv_WriteRegBit(0x112CDC, 1, 0x80);
MDrv_WriteRegBit(0x112CDC, 1, 0x40);
MDrv_WriteRegBit(0x112CDC, 1, 0x20);
MDrv_WriteRegBit(0x112CDC, 1, 0x10);
MDrv_WriteRegBit(0x112CDE, 1, 0x80);
MDrv_WriteRegBit(0x112CDE, 1, 0x40);
MDrv_WriteRegBit(0x112CE3, 1, 0x03);
MDrv_WriteRegBit(0x112CE6, 1, 0x02);
MDrv_WriteRegBit(0x112CE6, 1, 0x01);
MDrv_WriteRegBit(0x112CE9, 1, 0x80);
MDrv_WriteRegBit(0x112CED, 1, 0x80);
MDrv_WriteRegBit(0x112CED, 1, 0x08);
}
static void MDrv_VideoAtop_PowerDown(void)
{
MDrv_WriteRegBit(0x102503, 0, 0x40);
MDrv_WriteRegBit(0x102509, 1, 0x04);
MDrv_WriteRegBit(0x102509, 1, 0x08);
MDrv_WriteRegBit(0x102509, 1, 0x10);
MDrv_WriteRegBit(0x10250a, 1, 0x04);
MDrv_WriteRegBit(0x10250A, 1, 0x08);
MDrv_WriteRegBit(0x10257E, 1, 0x01);
MDrv_WriteRegBit(0x10250A, 1, 0x10);
MDrv_WriteRegBit(0x10250A, 1, 0x20);
MDrv_WriteRegBit(0x10257e, 1, 0x02);
MDrv_WriteRegBit(0x102508, 1, 0x04);
MDrv_WriteRegBit(0x102508, 1, 0x08);
MDrv_WriteRegBit(0x102508, 1, 0x01);
MDrv_WriteRegBit(0x102508, 1, 0x02);
MDrv_WriteRegBit(0x102508, 1, 0x10);
MDrv_WriteRegBit(0x102505, 0, 0x01);
MDrv_WriteRegBit(0x102505, 0, 0x02);
MDrv_WriteRegBit(0x102570, 0, 0x02);
MDrv_WriteRegBit(0x102570, 0, 0x01);
MDrv_WriteRegBit(0x102590, 0, 0x08);
MDrv_WriteRegBit(0x102592, 0, 0x08);
MDrv_WriteRegBit(0x10250b, 1, 0x01);
MDrv_WriteRegBit(0x10250b, 1, 0x02);
MDrv_WriteRegBit(0x10250b, 1, 0x04);
MDrv_WriteRegBit(0x102509, 1, 0x02);
MDrv_WriteRegBit(0x10250A, 1, 0x02);
MDrv_WriteRegBit(0x10250B, 1, 0x08);
MDrv_WriteRegBit(0x102509, 1, 0x01);
MDrv_WriteRegBit(0x102508, 1, 0x20);
MDrv_WriteRegBit(0x102508, 1, 0x40);
MDrv_WriteRegBit(0x102508, 1, 0x80);
MDrv_WriteRegBit(0x102509, 1, 0x40);
MDrv_WriteRegBit(0x102580, 1, 0x40);
MDrv_WriteRegBit(0x1025A0, 1, 0x01);
MDrv_WriteRegBit(0x1025A4, 1, 0x01);
MDrv_WriteRegBit(0x1025BC, 1, 0x40);
MDrv_WriteRegBit(0x1025BC, 1, 0x80);
MDrv_WriteRegBit(0x1025BD, 1, 0x01);
MDrv_WriteRegBit(0x1025BD, 1, 0x02);
MDrv_WriteRegBit(0x1025BD, 1, 0x04);
MDrv_WriteRegBit(0x1025BD, 1, 0x08);
MDrv_WriteRegBit(0x1025BD, 1, 0x10);
MDrv_WriteRegBit(0x1025BD, 1, 0x20);
}
static void MDrv_Demod_PowerDown(void)
{
MDrv_WriteRegBit(0x112840, 1, 0x10);
MDrv_WriteRegBit(0x112818, 1, 0x04);
MDrv_WriteRegBit(0x11281E, 1, 0x80);
MDrv_WriteRegBit(0x112818, 1, 0x01);
MDrv_WriteRegBit(0x11286A, 1, 0x80);
MDrv_WriteRegBit(0x11286B, 1, 0x20);
MDrv_WriteRegBit(0x112860, 1, 0x02);
MDrv_WriteRegBit(0x112860, 1, 0x04);
MDrv_WriteRegBit(0x112860, 1, 0x08);
MDrv_WriteRegBit(0x112860, 1, 0x10);
MDrv_WriteRegBit(0x112860, 1, 0x20);
MDrv_WriteRegBit(0x112860, 1, 0x40);
MDrv_WriteRegBit(0x11286C, 0, 0x10); //invert=Y
MDrv_WriteRegBit(0x11286B, 0, 0x40);
MDrv_WriteRegBit(0x11286B, 0, 0x80);
MDrv_WriteRegBit(0x11286D, 0, 0x02);
}
static void MDrv_DVITOP_PowerDown(void)
{
MDrv_WriteRegBit( 0x000e98, 0, 0x01);
MDrv_WriteRegBit( 0x1109c0, 1, 0x20);
MDrv_WriteRegBit( 0x1109c0, 1, 0x80);
MDrv_WriteRegBit( 0x000e97, 0, 0x01);
MDrv_WriteRegBit( 0x000e97, 0, 0x02);
MDrv_WriteRegBit( 0x000e94, 0, 0x40);
MDrv_WriteRegBit( 0x1109BE, 1, 0x01);
MDrv_WriteRegBit( 0x1109C0, 1, 0x07);
MDrv_WriteRegBit( 0x1109C1, 1, 0x07);
MDrv_WriteRegBit( 0x1109C1, 1, 0x38);
MDrv_WriteRegBit( 0x000e97, 0, 0x08);
MDrv_WriteRegBit( 0x102711, 0, 0x02);
}
//***********************************************************
// Local Functions Definition
//***********************************************************
static void MDrv_Digital_PowerDown(void)
{
// Please follow IP clock gating flow
// 1. IP SW reset
// 2. MIU client ID mask
// 3. IP clock gate
{
// tsp and stc0
MDrv_Write2Byte(0x101588, MDrv_Read2Byte(0x101588) & ~(BIT2|BIT1|BIT0)); // IP reset
MDrv_Write2Byte(0x101246, MDrv_Read2Byte(0x101588) | (BIT14|BIT10|BIT9)); // g0
MDrv_WriteRegBit(0x100b54, 1, BIT0); // tsp clock gating
MDrv_WriteRegBit(0x100b55, 1, BIT0); // stc0 clock gating
}
{
// mvd
MDrv_Write2Byte(0x101100, MDrv_Read2Byte(0x101100) | BIT0); // IP reset
MDrv_Write2Byte(0x101246, MDrv_Read2Byte(0x101588) | BIT11); // g0
MDrv_Write2Byte(0x101286, MDrv_Read2Byte(0x101286) | BIT4); // g2
MDrv_WriteRegBit(0x100b72, 1, BIT0); // IP clock gating
MDrv_WriteRegBit(0x100b73, 1, BIT0);
MDrv_WriteRegBit(0x100b74, 1, BIT0);
MDrv_WriteRegBit(0x100b75, 1, BIT0);
MDrv_WriteRegBit(0x100b76, 1, BIT0);
MDrv_WriteRegBit(0x100b77, 1, BIT0);
MDrv_WriteRegBit(0x100b78, 1, BIT0);
MDrv_WriteRegBit(0x100b79, 1, BIT0);
}
{
// mvop
MDrv_Write2Byte(0x101422, MDrv_Read2Byte(0x101422) & ~(BIT0));
MDrv_Write2Byte(0x101266, MDrv_Read2Byte(0x101266) | BIT3); //g1
MDrv_WriteRegBit(0x100b4c, 1, BIT0);
MDrv_WriteRegBit(0x100b4d, 1, BIT0);
}
{
// gop
MDrv_Write2Byte(0x101ffe, MDrv_Read2Byte(0x101ffe) & ~(BIT3|BIT2|BIT1|BIT0)); // set gop bank
MDrv_Write2Byte(0x101f00, MDrv_Read2Byte(0x101f00) | BIT0);
MDrv_Write2Byte(0x101266, MDrv_Read2Byte(0x101266) | (BIT6|BIT5|BIT4)); //g1
MDrv_WriteRegBit(0x100b80, 1, BIT0);
MDrv_WriteRegBit(0x100b81, 1, BIT0);
MDrv_WriteRegBit(0x100b83, 1, BIT0);
}
{
// ge
MDrv_Write2Byte(0x102800, MDrv_Read2Byte(0x102800) & ~(BIT0));
MDrv_Write2Byte(0x101286, MDrv_Read2Byte(0x101286) | BIT1); //g2
MDrv_WriteRegBit(0x100b90, 1, BIT0);
}
{
// hvd
MDrv_Write2Byte(0x101b02, MDrv_Read2Byte(0x101b02) | BIT0);
MDrv_Write2Byte(0x101286, MDrv_Read2Byte(0x101286) | (BIT3|BIT5)); //g2
MDrv_WriteRegBit(0x100b62, 1, BIT0);
}
{
// usb
MDrv_WriteRegBit(0x103a88, 1, BIT7);
MDrv_WriteByte(0x103a82, 0x80);
MDrv_WriteByte(0x103a83, 0x90);
MDrv_WriteByte(0x103a80, 0xc7);
MDrv_WriteByte(0x103a81, 0xef);
MDrv_WriteByte(0x100700, 0x00);
MDrv_WriteByte(0x100702, 0x00);
MDrv_Write2Byte(0x102408, MDrv_Read2Byte(0x102408) | BIT1);
MDrv_Write2Byte(0x101286, MDrv_Read2Byte(0x101286) | BIT6); //g2
}
{
// jpd
MDrv_Write2Byte(0x101700, MDrv_Read2Byte(0x101700) & ~(BIT13));
MDrv_Write2Byte(0x101286, MDrv_Read2Byte(0x101286) | BIT8); //g2
MDrv_WriteRegBit(0x100b6a, 1, BIT0);
}
{
// dscrmb
MDrv_Write2Byte(0x100c00, MDrv_Read2Byte(0x100c00) | BIT7);
MDrv_Write2Byte(0x101286, MDrv_Read2Byte(0x101286) | BIT9); //g2
// clk gateing ??
}
{
// vd(comb)
MDrv_WriteRegBit(0x103613, 1, BIT6); // comb SW reset
MDrv_WriteRegBit(0x103770, 1, BIT3); // VBI SW reset
MDrv_WriteRegBit(0x103801, 1, BIT7); // SCM SW reset
MDrv_Write2Byte(0x101266, MDrv_Read2Byte(0x101266) | (BIT13|BIT12)); //g1
MDrv_Write2Byte(0x101246, MDrv_Read2Byte(0x101588) | BIT12); // g0
MDrv_Write2Byte(0x101286, MDrv_Read2Byte(0x101286) | BIT2); // g2
MDrv_WriteRegBit(0x100b41, 1, BIT0);
MDrv_WriteRegBit(0x100b46, 1, BIT0);
MDrv_WriteRegBit(0x100b43, 1, BIT0);
MDrv_WriteRegBit(0x100b47, 1, BIT0);
}
{
// mau0 & mau1
// g0,ID=5 mau0(hk_aeon) riu=0x100f
// g0,ID=6 mau1(codec_aeon) riu=0x1003
// g0,ID=8 unused
MDrv_WriteRegBit(0x100ff0, 0, BIT1);
MDrv_WriteRegBit(0x1003f0, 0, BIT1);
MDrv_Write2Byte(0x101246, MDrv_Read2Byte(0x101588) | (BIT6|BIT5)); // g0
MDrv_WriteRegBit(0x100b24, 1, BIT0);
MDrv_WriteRegBit(0x100b60, 1, BIT0);
}
{
// sc
MDrv_WriteByte(0x102f00, 0x00); // bank0
MDrv_WriteByte(0x103f04, 0x01); // SC SW reset
MDrv_Write2Byte(0x101266, MDrv_Read2Byte(0x101266) | (BIT10|BIT9|BIT8|BIT7)); //g1
MDrv_WriteRegBit(0x100ba8, 1, BIT0); // sc clock gate
MDrv_WriteRegBit(0x100baa, 1, BIT0);
MDrv_WriteRegBit(0x100bac, 1, BIT0);
MDrv_WriteRegBit(0x100bae, 1, BIT0);
MDrv_WriteRegBit(0x100ba5, 1, BIT0);
MDrv_WriteRegBit(0x100ba3, 1, BIT0);
}
{
// vivaldi9
MDrv_WriteByte(0x112c00, 0x03); // vivaldi reset
MDrv_Write2Byte(0x101246, MDrv_Read2Byte(0x101588) | (BIT5|BIT6)); // g0
MDrv_Write2Byte(0x101266, MDrv_Read2Byte(0x101266) | (BIT0|BIT1|BIT2)); //g1
MDrv_Write2Byte(0x101286, MDrv_Read2Byte(0x101286) | BIT0); // g2
MDrv_WriteByte(0x112caa, 0x00);
MDrv_WriteByte(0x112cab, 0x00);
}
MDrv_WriteRegBit(0x100b34, 1, BIT0);
MDrv_WriteRegBit(0x100b49, 1, BIT0);
MDrv_WriteRegBit(0x100b4c, 1, BIT0);
MDrv_WriteRegBit(0x100b4d, 1, BIT0);
MDrv_WriteRegBit(0x100b6a, 1, BIT0);
MDrv_WriteRegBit(0x103308, 1, BIT0);
MDrv_WriteRegBit(0x103309, 1, BIT0);
MDrv_WriteRegBit(0x103314, 1, BIT0);
MDrv_WriteRegBit(0x10331a, 1, BIT0);
MDrv_WriteRegBit(0x10331b, 1, BIT0);
MDrv_WriteRegBit(0x100b3e, 1, BIT0);
MDrv_WriteRegBit(0x100b27, 1, BIT0);
MDrv_WriteRegBit(0x100b28, 1, BIT0);
MDrv_WriteRegBit(0x100b29, 1, BIT0);
MDrv_WriteRegBit(0x100b3f, 1, BIT0);
MDrv_WriteRegBit(0x100b86, 1, BIT0);
MDrv_WriteRegBit(0x100b87, 1, BIT0);
MDrv_WriteRegBit(0x100ba6, 1, BIT0);
MDrv_WriteRegBit(0x100bae, 1, BIT0);
MDrv_WriteRegBit(0x100baf, 1, BIT0);
MDrv_WriteRegBit(0x100ba6, 1, BIT0);
MDrv_WriteRegBit(0x100b42, 1, BIT0);
MDrv_WriteRegBit(0x10331e, 1, BIT0);
MDrv_WriteRegBit(0x100b44, 1, BIT0);
MDrv_WriteRegBit(0x100b45, 1, BIT0);
MDrv_WriteRegBit(0x100b34, 1, BIT0);
MDrv_WriteRegBit(0x100b34, 1, BIT0);
MDrv_WriteRegBit(0x100ba7, 1, BIT0);
MDrv_WriteRegBit(0x100b60, 1, BIT0);
MDrv_WriteRegBit(0x103362, 1, BIT0);
}
