Ejemplo n.º 1
0
static void
handler_system_manager(void)
{
        static uint32_t offset = 0;

        /* We don't have much time in the critical section. Just
         * buffer the registers */
        uint32_t oreg;

        for (oreg = 0; oreg < SMPC_OREGS; oreg++, offset++) {
                OREG_SET(offset, MEMORY_READ(8, OREG(oreg)));
        }

        uint8_t sr;

        sr = MEMORY_READ(8, SMPC(SR));
        if ((sr & 0x80) == 0x80) {
                if ((sr & NPE) == 0x00) {
                        /* Mark that SMPC status and peripheral data
                         * collection is complete */
                        _collection_complete = true;

                        offset = 0;

                        /* Issue a "BREAK" for the "INTBACK" command */
                        MEMORY_WRITE(8, IREG(0), BR);
                        return;
                }
        }

        /* Issue a "CONTINUE" for the "INTBACK" command */
        MEMORY_WRITE(8, IREG(0), CONT);
}
void
cpu_dmac_channel_stop(void)
{
        uint32_t dmaor;
        uint32_t chcr0;
        uint32_t chcr1;

        /* When the AE bit is set to 1, DMA transfer cannot be enabled
         * even if the DE bit in the DMA channel control register is set
         *
         * When the NMIF bit is set to 1, DMA transfer cannot be enabled
         * even if the DE bit in the DMA channel control register is
         * set */
        dmaor = MEMORY_READ(32, CPU(DMAOR));
        dmaor &= ~0x0000000E;
        MEMORY_WRITE(32, CPU(DMAOR), dmaor);

        /* Immediately disable channels */
        chcr0 = MEMORY_READ(32, CPU(CHCR0));
        chcr0 &= ~0x00000001;
        MEMORY_WRITE(32, CPU(CHCR0), chcr0);

        chcr1 = MEMORY_READ(32, CPU(CHCR1));
        chcr1 &= ~0x00000001;
        MEMORY_WRITE(32, CPU(CHCR1), chcr1);
}
uint8_t
usb_cartridge_read_byte(void)
{
        uint8_t b;

        /* Blocks */
        while ((MEMORY_READ(8, USB_CARTRIDGE(FLAG)) & USB_RXF));

        b = MEMORY_READ(8, USB_CARTRIDGE(FIFO));

        return b;
}
Ejemplo n.º 4
0
uint8_t
smpc_smc_nmireq_call(void)
{
        /* Send "NMI" request to master "SH-2" */
        smpc_smc_call(SMPC_SMC_NMIREQ, SMPC_CMD_ISSUE_TYPE_A, NULL);

        return MEMORY_READ(8, OREG(31));
}
/* Command type: Non-resetable system management commands */
uint8_t
smpc_smc_setsmem_call(void)
{

        smpc_smc_call(SMPC_SMC_SETSMEM, SMPC_CMD_ISSUE_TYPE_C, NULL);

        return MEMORY_READ(8, OREG(31));
}
Ejemplo n.º 6
0
/* Command type: Resetable system management commands */
uint8_t
smpc_smc_sshon_call(void)
{
        /* Enable the "SH-2" master CPU */
        smpc_smc_call(SMPC_SMC_MSHON, SMPC_CMD_ISSUE_TYPE_A, NULL);

        return MEMORY_READ(8, OREG(31));
}
Ejemplo n.º 7
0
uint32_t
scu_ic_status_get(void)
{
        uint32_t ist;

        ist = MEMORY_READ(32, SCU(IST));
        return ist;
}
uint8_t
smpc_smc_ckchg320_call(void)
{
        /* Switch the SATURN system clock from 352 mode to 320 mode iff
         * not called from slave "SH-2" */
        smpc_smc_call(SMPC_SMC_CKCHG320, SMPC_CMD_ISSUE_TYPE_A, NULL);

        return MEMORY_READ(8, OREG(31));
}
Ejemplo n.º 9
0
int computer_readmem_byte(int cpu, int addr)
{
    int oldcpu = cpu_getactivecpu(), result;
    memory_set_context(cpu);
    result = MEMORY_READ(cpu, addr);
    if (oldcpu != cpu)
    	memory_set_context(oldcpu);
    return result;
}
void
vdp1_fbcr_interlace_set(enum fbcr_interlace_type mode)
{
        uint16_t modr;

        /* Only NTSC and PAL format is able to have interlace mode. */
        modr = MEMORY_READ(16, VDP1(MODR));
        if ((modr & 0x0006) == 0x0000)
                MEMORY_WRITE(16, VDP1(FBCR), mode);
}
Ejemplo n.º 11
0
void
vdp2_tvmd_display_set(void)
{
        uint16_t tvmd;

        tvmd = MEMORY_READ(16, VDP2(TVMD));
        tvmd |= 0x8000;

        MEMORY_WRITE(16, VDP2(TVMD), tvmd);
}
Ejemplo n.º 12
0
void
vdp1_fbcr_rotate_set(void)
{
        uint16_t tvmr;

        tvmr = MEMORY_READ(16, VDP1(MODR));

        /* Write to memory. */
        MEMORY_WRITE(16, VDP1(TVMR), (tvmr & 0x0007) | 0x0002);
}
Ejemplo n.º 13
0
void
scu_timer_all_disable(void)
{
        uint32_t t1md;

        t1md = MEMORY_READ(32, SCU(T1MD));
        t1md &= ~0x00000001;
        /* Write to memory */
        MEMORY_WRITE(32, SCU(T1MD), t1md);
}
Ejemplo n.º 14
0
void
vdp1_fbcr_bpp_set(uint8_t bpp)
{
        uint16_t tvmr;

        tvmr = MEMORY_READ(16, VDP1(MODR));

        /* Write to memory. */
        MEMORY_WRITE(16, VDP1(TVMR), (tvmr & 0x7) | ((bpp == 8) ? 1 : 0));
}
Ejemplo n.º 15
0
bool
arp_busy_status(void)
{
        uint8_t status;
        bool busy;

        status = MEMORY_READ(8, ARP(STATUS));
        status &= 0x01;
        /* Busy? */
        busy = (status == 0x00);

        return busy;
}
Ejemplo n.º 16
0
void
vdp2_tvmd_display_clear(void)
{
        uint16_t tvmd;

        tvmd = MEMORY_READ(16, VDP2(TVMD));
        tvmd &= 0x7FFF;

        /* Change the DISP bit during VBLANK */
        vdp2_tvmd_vblank_in_wait();

        MEMORY_WRITE(16, VDP2(TVMD), tvmd);
}
void
cpu_dmac_channel_start(uint8_t ch)
{
        uint32_t chcr0;
        uint32_t chcr1;
        uint32_t dmaor;

        cpu_dmac_channel_stop();

        /* Read after stopping all DMA channels */
        dmaor = MEMORY_READ(32, CPU(DMAOR));

        switch (ch) {
        case CPU_DMAC_CHANNEL(0):
                chcr0 = MEMORY_READ(32, CPU(CHCR0));
                chcr0 |= 0x00000201;

                /* DMA transfers enabled on all channels */
                dmaor |= 0x00000001;

                /* Write to memory */
                MEMORY_WRITE(32, CPU(CHCR0), chcr0);
                break;
        case CPU_DMAC_CHANNEL(1):
                chcr1 = MEMORY_READ(32, CPU(CHCR1));
                chcr1 |= 0x00000201;

                /* Write to memory */
                MEMORY_WRITE(32, CPU(CHCR1), chcr1);
                break;
        default:
                assert((ch == CPU_DMAC_CHANNEL(0)) ||
                    (ch == CPU_DMAC_CHANNEL(1)));
                /* NOTREACHED */
        }

        /* Write to memory */
        MEMORY_WRITE(32, CPU(DMAOR), dmaor);
}
void
vdp1_fbcr_erase_coordinates_set(uint16_t x1, uint16_t y1, uint16_t x3, uint16_t y3, uint16_t color)
{
        uint16_t bpp;
        uint16_t modr;

        /* Obtain the bit depth of the frame buffer. */
        modr = MEMORY_READ(16, VDP1(MODR));
        bpp = ((modr & 0x0001) == 0x0001) ? 4 : 3;

        /* Upper-left coordinates. */
        MEMORY_WRITE(16, VDP1(EWLR), ((x1 >> bpp) << 9) | (y1 - 1));

        /* Lower-right coordinates. */
        MEMORY_WRITE(16, VDP1(EWLR), ((x3 >> bpp) << 9) | (y3 - 1));

        MEMORY_WRITE(16, VDP1(EWDR), color);
}
void read_digital_pad(void)
{
	if (g_digital.connected == 1)
	{
		joyUp = g_digital.pressed.button.up;
		joyDown = g_digital.pressed.button.down;
		joyRight = g_digital.pressed.button.right;                            
		joyLeft = g_digital.pressed.button.left;
        joyA = g_digital.released.button.a;
        joyB = g_digital.released.button.b;
        joyL = g_digital.released.button.l;
        joyR = g_digital.released.button.r;    
        joyX = g_digital.released.button.x;  
        joyY = g_digital.released.button.y;     

		if (joyDown)
		{
				if(g_cc_NBG2 < 0x1F) g_cc_NBG2++;
		}
		else if (joyUp)
		{
				if(g_cc_NBG2 > 0x0) g_cc_NBG2--;
		}
		else if (joyRight)
		{
				if(g_cc_NBG0 > 0x0) g_cc_NBG0--;
		}
		else if (joyLeft)
		{
				if(g_cc_NBG0 < 0x1F) g_cc_NBG0++;    				
		}
  		else if (joyA)
		{
            MEMORY_WRITE(16, VDP2(CCCTL), 0x0);    
            MEMORY_WRITE(16, VDP2(CCCTL), (1 << 15) | (1 << 14) | (1 << 12) | 0x5);    
		} 
   		else if (joyB)
		{
            MEMORY_WRITE(16, VDP2(CCCTL), 0x0);    
            MEMORY_WRITE(16, VDP2(CCCTL), 0x5);    
		}   
   		else if (joyL)
		{
            MEMORY_WRITE(16, VDP2(CCCTL), 0x0);    
            MEMORY_WRITE(16, VDP2(CCCTL), (1 << 10) | 0x5);    
            
            g_ecc_NBG0 = (g_ecc_NBG0 + 1) & 0x3;
            MEMORY_WRITE(16, VDP2(SFCCMD), g_ecc_NBG0);  
		}    
        else if (joyR)
		{
            MEMORY_WRITE(16, VDP2(CCCTL), 0x0);    
            MEMORY_WRITE(16, VDP2(CCCTL), 0x5);    
		}
        else if (joyX)
		{
            uint16_t reg = MEMORY_READ(16, VDP2(CCCTL));    
            MEMORY_WRITE(16, VDP2(CCCTL), reg | (1 << 9));    
		}  
         else if (joyY)
		{
            uint16_t reg = MEMORY_READ(16, VDP2(CCCTL));    
            MEMORY_WRITE(16, VDP2(CCCTL), reg & (0xFDFF));    
		}   
		
		// exit
		if(g_digital.pressed.button.start) abort();		

		
		MEMORY_WRITE(16, VDP2(CCRNA), g_cc_NBG0 & 0x1F);
		MEMORY_WRITE(16, VDP2(CCRNB), g_cc_NBG2 & 0x1F);    
	}  
        
}