// Byte6Seed, Byte7Seed, ByteEccSeed) // Specifies the write leveling seed for a channel of a socket. // // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, // Byte6Seed, Byte7Seed, ByteEccSeed) // Speicifes the HW RXEN training seed for a channel of a socket // #define SEED_A 0x12 HW_RXEN_SEED( ANY_SOCKET, CHANNEL_A, ALL_DIMMS, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), MOTHER_BOARD_LAYERS (LAYERS_4), MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), PSO_END }; /* * These tables are optional and may be used to adjust memory timing settings */ #include "mm.h" #include "mn.h"
if (spdAddress == 0)
return AGESA_ERROR;
int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
if (err)
return AGESA_ERROR;
#endif
return AGESA_SUCCESS;
}
#ifdef __PRE_RAM__
const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
MOTHER_BOARD_LAYERS (LAYERS_6),
MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
PSO_END
};
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
if (board_id() == 'F') {
PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
}
}
#endif
