void ll_msc_irq(void) { unsigned int irq; MSCIC_READ(MSC01_IC_VEC, irq); if (irq < 64) do_IRQ(irq + irq_base); else { } }
/* * Interrupt handler for interrupts coming from SOC-it. */ void ll_msc_irq(void) { unsigned int irq; /* read the interrupt vector register */ MSCIC_READ(MSC01_IC_VEC, irq); if (irq < 64) do_IRQ(irq + irq_base); else { /* Ignore spurious interrupt */ } }
/* * Masks and ACKs an IRQ */ static void edge_mask_and_ack_msc_irq(unsigned int irq) { mask_msc_irq(irq); if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); else { u32 r; MSCIC_READ(MSC01_IC_SUP+irq*8, r); MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); } smtc_im_ack_irq(irq); }
/* * Masks and ACKs an IRQ */ static void edge_mask_and_ack_msc_irq(unsigned int irq) { mask_msc_irq(irq); if (!cpu_has_veic) MSCIC_WRITE(MSC01_IC_EOI, 0); else { u32 r; MSCIC_READ(MSC01_IC_SUP+irq*8, r); MSCIC_WRITE(MSC01_IC_SUP+irq*8, r | ~MSC01_IC_SUP_EDGE_BIT); MSCIC_WRITE(MSC01_IC_SUP+irq*8, r); } #ifdef CONFIG_MIPS_MT_SMTC if (irq_hwmask[irq] & ST0_IM) set_c0_status(irq_hwmask[irq] & ST0_IM); #endif /* CONFIG_MIPS_MT_SMTC */ }