int do_warmRst(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { int i, gbe, gatingReg; unsigned int base = simple_strtoul( argv[1], NULL, 16 ); /*Set all 4 cores in reset*/ for ( i=0; i<=3; i++){ MV_MEMIO32_WRITE((base | (MV_SW_RST_CONTROL_REG_CORE0 + 8*i)), (0x101)); } /*Fix only used GBE default value in RX queue control registers*/ gatingReg = MV_MEMIO32_READ(MV_CLOCK_GATING_CONTROL); for( gbe=0; gbe <=3; gbe++){ /*If Gbe powered down(bits 1,2,3,4) - skip.*/ if( (gatingReg>>(gbe+1) & 0x1) ){ continue; } for ( i=0; i<=7; i++){ MV_MEMIO32_WRITE((base | ( MV_GBEx_PORT_RXQ_CONFIG_REG[gbe] + 4*i)), (0x40)); } } /*Reset all units in Fabric*/ MV_MEMIO32_WRITE((base | (MV_FABRIC_RST_CONTROL_REG)), (0xFFFFFFFF)); /*Set Fabric control and config to defaults*/ MV_MEMIO32_WRITE((base | (MV_FABRIC_CONTROL_REG)), (0x2)); MV_MEMIO32_WRITE((base | (MV_FABRIC_CONFIG_REG)), (0x3)); /*Kick in Fabric units*/ MV_MEMIO32_WRITE((base | (MV_FABRIC_RST_CONTROL_REG)), (0x0)); /*Kick in Core0 to start boot process*/ MV_MEMIO32_WRITE((base | (MV_SW_RST_CONTROL_REG_CORE0)), (0x0)); return 1; }
MV_U32 mvPncAgingLogEntryRead(int group, int mostly) { MV_U32 va, w32; ERR_ON_OOR(group >= MV_PNC_AGING_MAX_GROUP); va = (MV_U32)mvPncVirtBase; va |= PNC_AGING_ACCESS_MASK; va |= PNC_AGING_SCANNER_ADDR_MASK; va |= ((MV_PNC_AGING_MAX_GROUP * mostly + group) << PNC_AGING_LOG_ADDR_OFFS); w32 = MV_MEMIO32_READ(va); return w32; }
MV_U32 mvPncAgingGroupCntrRead(int group) { MV_U32 va, w32; ERR_ON_OOR(group >= MV_PNC_AGING_MAX_GROUP); va = (MV_U32)mvPncVirtBase; va |= PNC_AGING_ACCESS_MASK; va |= PNC_AGING_GROUPS_ADDR_MASK; va |= (group << PNC_AGING_GROUP_ADDR_OFFS); w32 = MV_MEMIO32_READ(va); return w32; }
MV_U32 mvPncAgingCntrRead(int tid) { MV_U32 va, w32; ERR_ON_OOR(tid >= MV_ETH_TCAM_LINES); va = (MV_U32)mvPncVirtBase; va |= PNC_AGING_ACCESS_MASK; va |= PNC_AGING_CNTRS_ADDR_MASK; va |= (tid << PNC_AGING_CNTR_IDX_ADDR_OFFS); w32 = MV_MEMIO32_READ(va); /* mvOsPrintf("%s: tid=%d, va=0x%x, w32=0x%08x\n", __FUNCTION__, tid, va, w32); */ return w32; }
/******************************************************************************* * FUNCTION: commit cfgQ which contains BCM DHUB programming info to interrupt service routine * PARAMS: *cfgQ - cfgQ * cpcbID - cpcb ID which this cmdQ belongs to * intrType - interrupt type which this cmdQ belongs to: 0 - VBI, 1 - VDE * NOTE: this API is only called from VBI/VDE ISR. *******************************************************************************/ int THINVPP_BCMDHUB_CFGQ_Commit(DHUB_CFGQ *cfgQ, int cpcbID) { unsigned int sched_qid; unsigned int bcm_sched_cmd[2]; static int bcm_count = 0; bcm_count++; if (cfgQ->len <= 0) return MV_THINVPP_EBADPARAM; if (cpcbID == CPCB_1) sched_qid = BCM_SCHED_Q0; else if (cpcbID == CPCB_2) sched_qid = BCM_SCHED_Q1; else sched_qid = BCM_SCHED_Q2; { //check BCM Q status before use int sched_stat; BCM_SCHED_GetEmptySts(sched_qid, &sched_stat); if (sched_stat == 0) { printk("****************[VPP fastlogo]ERROR! Q%d SCHED QUEUE OVERFLOW!!!!*************\n", sched_qid); printk("[VPP fastlogo] BCM Q fulless status: %X\n", MV_MEMIO32_READ(MEMMAP_AVIO_BCM_REG_BASE+RA_AVIO_BCM_FULL_STS)); return MV_THINVPP_EIOFAIL; } } #if LOGO_USE_SHM dhub_channel_generate_cmd(&(VPP_dhubHandle.dhub), avioDhubChMap_vpp_BCM_R, cfgQ->phys, (int)cfgQ->len*8, 0, 0, 0, 1, bcm_sched_cmd); #else inner_outer_flush_dcache_area(cfgQ->addr, cfgQ->len*8); dhub_channel_generate_cmd(&(VPP_dhubHandle.dhub), avioDhubChMap_vpp_BCM_R, (int)virt_to_phys(cfgQ->addr), (int)cfgQ->len*8, 0, 0, 0, 1, bcm_sched_cmd); #endif while( !BCM_SCHED_PushCmd(sched_qid, bcm_sched_cmd, NULL)); return MV_THINVPP_OK; }
int do_warmRst(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { int i, gbe, gatingReg, core; unsigned int base = simple_strtoul( argv[1], NULL, 16 ); /*Set all 4 cores in reset*/ for ( i = 0; i < 4; i++ ){ MV_MEMIO32_WRITE((base | (MV_SW_RST_CONTROL_REG_CORE0 + 8*i)), (0xF01)); } /*Set all 4 core Clock gating control */ for ( i = 0; i < 4; i++ ){ MV_MEMIO32_WRITE((base | (MV_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i)), (0x01010101)); } /*Fix only used GBE default value in RX queue control registers*/ gatingReg = MV_MEMIO32_READ(MV_CLOCK_GATING_CONTROL); for( gbe = 0; gbe < 3; gbe++ ){ /*If Gbe powered down(bits 1,2,3,4) - skip.*/ /*Note: this skip may be false in some systems, so if warm reset hangs - try cancel it and fix only used GBEs*/ if( !(gatingReg>>(gbe+1) & 0x1) ){ continue; } for ( i=0; i < 8; i++){ MV_MEMIO32_WRITE((base | ( MV_GBEx_PORT_RXQ_CONFIG_REG[gbe] + 4*i)), (0x40)); } } /*Reset all units in Fabric*/ MV_MEMIO32_WRITE((base | (MV_FABRIC_RST_CONTROL_REG)), (0x11F0101)); /*Restore default Clock Gating values*/ for ( i = 0; i < 5; i++ ){ MV_MEMIO32_WRITE((base | (MV_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i)), (0x0)); } MV_MEMIO32_WRITE((base | (MV_CLOCK_GATING_CONTROL)), (0xDBFFA239)); /*Reset all interrupt control registers*/ for ( i=0; i < 115; i++ ){ MV_MEMIO32_WRITE((base | (MV_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i)), (0x0)); } /*Reset Timers control registers. per core*/ for( core = 0; core < 4; core++) for( i = 0; i < 8; i++) MV_MEMIO32_WRITE((base | ( MV_CORE_TIMER_REG + 0x100*core + 4*i)), (0x0)); /*Reset per core IRQ ack register*/ for( core = 0; core < 4; core++) MV_MEMIO32_WRITE((base | ( MV_IRQ_ACK_REG + 0x100*core)), (0x3FF)); /*Set Fabric control and config to defaults*/ MV_MEMIO32_WRITE((base | (MV_FABRIC_CONTROL_REG)), (0x2)); MV_MEMIO32_WRITE((base | (MV_FABRIC_CONFIG_REG)), (0x3)); /*Kick in Fabric units*/ MV_MEMIO32_WRITE((base | (MV_FABRIC_RST_CONTROL_REG)), (0x0)); /*Kick in Core0 to start boot process*/ MV_MEMIO32_WRITE((base | (MV_SW_RST_CONTROL_REG_CORE0)), (0xF00)); return 1; }