void Map4_Init()
{
MapperInit = Map4_Init;
MapperWrite = Map4_Write;
MapperSram = Map0_Sram;
MapperApu = Map0_Apu;
MapperReadApu = Map0_ReadApu;
MapperVSync = Map0_VSync;
MapperHSync = Map4_HSync;
MapperPPU = Map0_PPU;
MapperRenderScreen = Map0_RenderScreen;
MapperRestore = Map4_Restore;
W.SRAMBANK = S.SRAM;
/* Initialize State Registers */
memset(&MS4.Regs, 0, sizeof(MS4.Regs));
/* Set ROM Banks */
MS4.Prg0 = 0;
MS4.Prg1 = 1;
Map4_Set_CPU_Banks();
/* Set PPU Banks */
if ( S.NesHeader.VROMSize > 0 )
{
W.PPUBANK[0] = VROMPAGE(0);
W.PPUBANK[1] = VROMPAGE(1);
W.PPUBANK[2] = VROMPAGE(2);
W.PPUBANK[3] = VROMPAGE(3);
W.PPUBANK[4] = VROMPAGE(4);
W.PPUBANK[5] = VROMPAGE(5);
W.PPUBANK[6] = VROMPAGE(6);
W.PPUBANK[7] = VROMPAGE(7);
} else {
memset(&MS4.PPU, 0, sizeof(MS4.PPU));
}
M.state = &MS4;
M.size = sizeof(MS4);
}
void Map4_Write( word wAddr, byte bData )
{
dword dwBankNum;
switch ( wAddr & 0xe001 )
{
case 0x8000:
MS4.Regs[ 0 ] = bData;
Map4_Set_CPU_Banks();
break;
case 0x8001:
MS4.Regs[ 1 ] = bData;
dwBankNum = MS4.Regs[ 1 ];
switch ( MS4.Regs[ 0 ] & 0x07 )
{
/* Set PPU Banks */
case 0x00:
if ( S.NesHeader.VROMSize > 0 )
{
dwBankNum &= 0xfe;
MS4.PPU[0] = dwBankNum;
if ( Map4_Chr_Swap() )
{
W.PPUBANK[4] = VROMPAGE((MS4.PPU[0] ) % (Map4_Vsz));
W.PPUBANK[5] = VROMPAGE((MS4.PPU[0]+1) % (Map4_Vsz));
} else {
W.PPUBANK[0] = VROMPAGE((MS4.PPU[0] ) % (Map4_Vsz));
W.PPUBANK[1] = VROMPAGE((MS4.PPU[0]+1) % (Map4_Vsz));
}
NESCore_Develop_Character_Data();
}
break;
case 0x01:
if ( S.NesHeader.VROMSize > 0 )
{
dwBankNum &= 0xfe;
MS4.PPU[1] = dwBankNum;
if ( Map4_Chr_Swap() )
{
W.PPUBANK[6] = VROMPAGE((MS4.PPU[1] ) % (Map4_Vsz));
W.PPUBANK[7] = VROMPAGE((MS4.PPU[1]+1) % (Map4_Vsz));
} else {
W.PPUBANK[2] = VROMPAGE((MS4.PPU[1] ) % (Map4_Vsz));
W.PPUBANK[3] = VROMPAGE((MS4.PPU[1]+1) % (Map4_Vsz));
}
NESCore_Develop_Character_Data();
}
break;
case 0x02:
if ( S.NesHeader.VROMSize > 0 )
{
MS4.PPU[2] = dwBankNum;
if ( Map4_Chr_Swap() )
W.PPUBANK[0] = VROMPAGE( MS4.PPU[2] % ( Map4_Vsz ) );
else
W.PPUBANK[4] = VROMPAGE( MS4.PPU[2] % ( Map4_Vsz ) );
NESCore_Develop_Character_Data();
}
break;
case 0x03:
if ( S.NesHeader.VROMSize > 0 )
{
MS4.PPU[3] = dwBankNum;
if ( Map4_Chr_Swap() )
W.PPUBANK[1] = VROMPAGE( MS4.PPU[3] % ( Map4_Vsz ) );
else
W.PPUBANK[5] = VROMPAGE( MS4.PPU[3] % ( Map4_Vsz ) );
NESCore_Develop_Character_Data();
}
break;
case 0x04:
if ( S.NesHeader.VROMSize > 0 )
{
MS4.PPU[4] = dwBankNum;
if ( Map4_Chr_Swap() )
W.PPUBANK[2] = VROMPAGE( MS4.PPU[4] % ( Map4_Vsz ) );
else
W.PPUBANK[6] = VROMPAGE( MS4.PPU[4] % ( Map4_Vsz ) );
NESCore_Develop_Character_Data();
}
break;
case 0x05:
if ( S.NesHeader.VROMSize > 0 )
{
MS4.PPU[5] = dwBankNum;
if ( Map4_Chr_Swap() )
W.PPUBANK[3] = VROMPAGE( MS4.PPU[5] % ( Map4_Vsz ) );
else
W.PPUBANK[7] = VROMPAGE( MS4.PPU[5] % ( Map4_Vsz ) );
NESCore_Develop_Character_Data();
}
break;
/* Set ROM Banks */
case 0x06:
MS4.Prg0 = dwBankNum;
Map4_Set_CPU_Banks();
break;
case 0x07:
MS4.Prg1 = dwBankNum;
Map4_Set_CPU_Banks();
break;
}
break;
case 0xa000:
MS4.Regs[ 2 ] = bData & 1;
if (!S.ROM_FourScr)
{
if ( bData & 0x01 )
{
NESCore_Mirroring( 0 );
} else {
NESCore_Mirroring( 1 );
}
}
break;
case 0xa001:
MS4.Regs[ 3 ] = bData;
break;
case 0xe000: /* ACK IRQ */
MS4.IRQ_Enabled = 0;
break;
case 0xe001: /* Enable IRQ */
MS4.IRQ_Enabled = 1;
break;
}
/* Old IRQ Technique */
/*
if (wAddr >= 0xc000 && wAddr <= 0xdfff) {
if (wAddr % 2 == 0) {
MS4.IRQ_Counter = bData;
}
else {
MS4.IRQ_Latch = bData;
}
}
*/
if (wAddr >= 0xc000 && wAddr <= 0xdfff) {
if (wAddr % 2 == 0) {
MS4.IRQ_Latch = bData;
}
else {
MS4.IRQ_Counter = MS4.IRQ_Latch;
}
}
}
/*-------------------------------------------------------------------*/
void Map4_Write( WORD wAddr, BYTE byData )
{
DWORD dwBankNum;
switch ( wAddr & 0xe001 )
{
case 0x8000:
Map4_Regs[ 0 ] = byData;
Map4_Set_PPU_Banks();
Map4_Set_CPU_Banks();
break;
case 0x8001:
Map4_Regs[ 1 ] = byData;
dwBankNum = Map4_Regs[ 1 ];
switch ( Map4_Regs[ 0 ] & 0x07 )
{
/* Set PPU Banks */
case 0x00:
if ( NesHeader.byVRomSize > 0 )
{
dwBankNum &= 0xfe;
Map4_Chr01 = dwBankNum;
Map4_Set_PPU_Banks();
}
break;
case 0x01:
if ( NesHeader.byVRomSize > 0 )
{
dwBankNum &= 0xfe;
Map4_Chr23 = dwBankNum;
Map4_Set_PPU_Banks();
}
break;
case 0x02:
if ( NesHeader.byVRomSize > 0 )
{
Map4_Chr4 = dwBankNum;
Map4_Set_PPU_Banks();
}
break;
case 0x03:
if ( NesHeader.byVRomSize > 0 )
{
Map4_Chr5 = dwBankNum;
Map4_Set_PPU_Banks();
}
break;
case 0x04:
if ( NesHeader.byVRomSize > 0 )
{
Map4_Chr6 = dwBankNum;
Map4_Set_PPU_Banks();
}
break;
case 0x05:
if ( NesHeader.byVRomSize > 0 )
{
Map4_Chr7 = dwBankNum;
Map4_Set_PPU_Banks();
}
break;
/* Set ROM Banks */
case 0x06:
Map4_Prg0 = dwBankNum;
Map4_Set_CPU_Banks();
break;
case 0x07:
Map4_Prg1 = dwBankNum;
Map4_Set_CPU_Banks();
break;
}
break;
case 0xa000:
Map4_Regs[ 2 ] = byData;
if ( !ROM_FourScr )
{
if ( byData & 0x01 )
{
InfoNES_Mirroring( 0 );
} else {
InfoNES_Mirroring( 1 );
}
}
break;
case 0xa001:
Map4_Regs[ 3 ] = byData;
break;
case 0xc000:
Map4_Regs[ 4 ] = byData;
Map4_IRQ_Latch = byData;
break;
case 0xc001:
Map4_Regs[ 5 ] = byData;
if ( PPU_Scanline < 240 )
{
Map4_IRQ_Cnt |= 0x80;
Map4_IRQ_Present = 0xff;
} else {
Map4_IRQ_Cnt |= 0x80;
Map4_IRQ_Present_Vbl = 0xff;
Map4_IRQ_Present = 0;
}
break;
case 0xe000:
Map4_Regs[ 6 ] = byData;
Map4_IRQ_Enable = 0;
Map4_IRQ_Request = 0;
break;
case 0xe001:
Map4_Regs[ 7 ] = byData;
Map4_IRQ_Enable = 1;
Map4_IRQ_Request = 0;
break;
}
}
/*-------------------------------------------------------------------*/
void Map4_Init()
{
/* Initialize Mapper */
MapperInit = Map4_Init;
/* Write to Mapper */
MapperWrite = Map4_Write;
/* Write to SRAM */
MapperSram = Map0_Sram;
/* Write to APU */
MapperApu = Map0_Apu;
/* Read from APU */
MapperReadApu = Map0_ReadApu;
/* Callback at VSync */
MapperVSync = Map0_VSync;
/* Callback at HSync */
MapperHSync = Map4_HSync;
/* Callback at PPU */
MapperPPU = Map0_PPU;
/* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */
MapperRenderScreen = Map0_RenderScreen;
/* Set SRAM Banks */
SRAMBANK = SRAM;
/* Initialize State Registers */
for ( int nPage = 0; nPage < 8; nPage++ )
{
Map4_Regs[ nPage ] = 0x00;
}
/* Set ROM Banks */
Map4_Prg0 = 0;
Map4_Prg1 = 1;
Map4_Set_CPU_Banks();
/* Set PPU Banks */
if ( NesHeader.byVRomSize > 0 )
{
Map4_Chr01 = 0;
Map4_Chr23 = 2;
Map4_Chr4 = 4;
Map4_Chr5 = 5;
Map4_Chr6 = 6;
Map4_Chr7 = 7;
Map4_Set_PPU_Banks();
} else {
Map4_Chr01 = Map4_Chr23 = 0;
Map4_Chr4 = Map4_Chr5 = Map4_Chr6 = Map4_Chr7 = 0;
}
/* Initialize IRQ Registers */
Map4_IRQ_Enable = 0;
Map4_IRQ_Cnt = 0;
Map4_IRQ_Latch = 0;
Map4_IRQ_Request = 0;
Map4_IRQ_Present = 0;
Map4_IRQ_Present_Vbl = 0;
/* Set up wiring of the interrupt pin */
K6502_Set_Int_Wiring( 1, 1 );
}
