/*!
* @brief Function to invoke the APIs through ioctl.
*
* @param cmd Command for driver ioctl
* @param args Arguments for the ioctl command
*
* @sa
*/
Int
SharedRegionDrv_ioctl (UInt32 cmd, Ptr args)
{
Int status = SharedRegion_S_SUCCESS;
int osStatus = -1;
SharedRegionDrv_CmdArgs * cargs = (SharedRegionDrv_CmdArgs *) args;
SharedRegion_Region * regions = NULL;
SharedRegion_Config * config;
Memory_MapInfo mapInfo;
UInt16 i;
GT_2trace (curTrace, GT_ENTER, "SharedRegionDrv_ioctl", cmd, args);
/* TODO: SharedRegionDrv_refCount not defined in QNX build
* GT_assert (curTrace, (SharedRegionDrv_refCount > 0));
*/
switch (cmd) {
case CMD_SHAREDREGION_GETCONFIG:
{
SharedRegionDrv_CmdArgs *cargs = (SharedRegionDrv_CmdArgs *)args;
iov_t sharedregion_getconfig_iov[2];
SharedRegion_Config * shreg_config = cargs->args.getConfig.config;
SETIOV( &sharedregion_getconfig_iov[0], cargs, sizeof(SharedRegionDrv_CmdArgs) );
SETIOV( &sharedregion_getconfig_iov[1], cargs->args.getConfig.config, sizeof(SharedRegion_Config) );
/* the osal_drv handle is used instead of ipcdrv_handle as the ipcdrc_handle is not yet initialized */
osStatus = devctlv( OsalDrv_handle, DCMD_SHAREDREGION_GETCONFIG, 1, 2, sharedregion_getconfig_iov, sharedregion_getconfig_iov, NULL);
if ( osStatus == 0 ){
cargs->args.getConfig.config = shreg_config;
}
}
break;
case CMD_SHAREDREGION_SETUP:
{
SharedRegionDrv_CmdArgs *cargs = (SharedRegionDrv_CmdArgs *)args;
iov_t sharedregion_setup_iov[3];
SETIOV( &sharedregion_setup_iov[0], cargs, sizeof(SharedRegionDrv_CmdArgs) );
SETIOV( &sharedregion_setup_iov[1], cargs->args.setup.config, sizeof(SharedRegion_Config) );
SETIOV( &sharedregion_setup_iov[2], cargs->args.setup.regions, cargs->args.setup.config->numEntries * sizeof(SharedRegion_Region) );
osStatus = devctlv( IpcDrv_handle, DCMD_SHAREDREGION_SETUP, 2, 3, sharedregion_setup_iov, sharedregion_setup_iov, NULL);
}
break;
case CMD_SHAREDREGION_GETREGIONINFO:
{
SharedRegionDrv_CmdArgs *cargs = (SharedRegionDrv_CmdArgs *)args;
iov_t sharedregion_getregconfig_iov[2]; /* no of max shared region entries + 1 */
//UInt16 i=0;
SharedRegion_Config config;
SharedRegion_getConfig (&config);
SETIOV( &sharedregion_getregconfig_iov[0], cargs, sizeof(SharedRegionDrv_CmdArgs) );
SETIOV( &sharedregion_getregconfig_iov[1], cargs->args.getRegionInfo.regions, (sizeof(SharedRegion_Region) * config.numEntries));
//for (i = 1; i< cargs->args.getConfig.config->numEntries+1;i++) {
// SETIOV( &sharedregion_getregconfig_iov[i], &cargs->args.setup.regions[i-1], sizeof(SharedRegion_Region) );
//}
// SETIOV( &sharedregion_getregconfig_iov[1], cargs->args.setup.regions, (sizeof(SharedRegion_Region) * cargs->args.getConfig.config->numEntries));
//osStatus = devctlv( IpcDrv_handle, DCMD_SHAREDREGION_GETREGIONINFO, 1, cargs->args.getConfig.config->numEntries + 1, sharedregion_getregconfig_iov, sharedregion_getregconfig_iov, NULL);
osStatus = devctlv( IpcDrv_handle, DCMD_SHAREDREGION_GETREGIONINFO, 2, 2, sharedregion_getregconfig_iov, sharedregion_getregconfig_iov, NULL);
}
break;
case CMD_SHAREDREGION_DESTROY:
{
osStatus = devctl( IpcDrv_handle, DCMD_SHAREDREGION_DESTROY, cargs, sizeof(SharedRegionDrv_CmdArgs), NULL);
}
break;
case CMD_SHAREDREGION_START:
{
osStatus = devctl( IpcDrv_handle, DCMD_SHAREDREGION_START, cargs, sizeof(SharedRegionDrv_CmdArgs), NULL);
}
break;
case CMD_SHAREDREGION_STOP:
{
osStatus = devctl( IpcDrv_handle, DCMD_SHAREDREGION_STOP, cargs, sizeof(SharedRegionDrv_CmdArgs), NULL);
}
break;
case CMD_SHAREDREGION_ATTACH:
{
osStatus = devctl( IpcDrv_handle, DCMD_SHAREDREGION_ATTACH, cargs, sizeof(SharedRegionDrv_CmdArgs), NULL);
}
break;
case CMD_SHAREDREGION_DETACH:
{
osStatus = devctl( IpcDrv_handle, DCMD_SHAREDREGION_DETACH, cargs, sizeof(SharedRegionDrv_CmdArgs), NULL);
}
break;
case CMD_SHAREDREGION_SETENTRY:
{
SharedRegionDrv_CmdArgs *cargs = (SharedRegionDrv_CmdArgs *)args;
iov_t sharedregion_getregsetentry_iov[2];
SETIOV( &sharedregion_getregsetentry_iov[0], cargs, sizeof(SharedRegionDrv_CmdArgs) );
SETIOV( &sharedregion_getregsetentry_iov[1], &cargs->args.setEntry.entry, sizeof(SharedRegion_Entry) );
osStatus = devctlv( IpcDrv_handle, DCMD_SHAREDREGION_SETENTRY, 2, 1, sharedregion_getregsetentry_iov, sharedregion_getregsetentry_iov, NULL);
}
break;
case CMD_SHAREDREGION_CLEARENTRY:
{
osStatus = devctl( IpcDrv_handle, DCMD_SHAREDREGION_CLEARENTRY, cargs, sizeof(SharedRegionDrv_CmdArgs), NULL);
}
break;
case CMD_SHAREDREGION_GETHEAP:
{
osStatus = devctl( IpcDrv_handle, DCMD_SHAREDREGION_GETHEAP, cargs, sizeof(SharedRegionDrv_CmdArgs), NULL);
}
break;
case CMD_SHAREDREGION_RESERVEMEMORY:
{
osStatus = devctl( IpcDrv_handle, DCMD_SHAREDREGION_RESERVEMEMORY, cargs, sizeof(SharedRegionDrv_CmdArgs), NULL);
}
break;
case CMD_SHAREDREGION_CLEARRESERVEDMEMORY:
{
osStatus = devctl( IpcDrv_handle, DCMD_SHAREDREGION_CLEARRESERVEDMEMORY, cargs, sizeof(SharedRegionDrv_CmdArgs), NULL);
}
break;
default:
{
/* This does not impact return status of this function, so retVal
* comment is not used.
*/
status = SharedRegion_E_INVALIDARG;
GT_setFailureReason (curTrace,
GT_4CLASS,
"SharedRegionDrv_ioctl",
status,
"Unsupported ioctl command specified");
}
break;
}
if (osStatus != 0) {
/*! @retval SharedRegion_E_OSFAILURE Driver ioctl failed */
status = SharedRegion_E_OSFAILURE;
GT_setFailureReason (curTrace,
GT_4CLASS,
"SharedRegionDrv_ioctl",
status,
"Driver ioctl failed!");
}
else {
/* First field in the structure is the API status. */
status = ((SharedRegionDrv_CmdArgs *) cargs)->apiStatus;
/* Convert the base address to user virtual address */
if (cmd == CMD_SHAREDREGION_SETUP) {
config = cargs->args.setup.config;
for (i = 0u; ( (i < config->numEntries) && (status >= 0)); i++) {
regions = &(cargs->args.setup.regions [i]);
if (regions->entry.isValid == TRUE) {
mapInfo.src = (UInt32) regions->entry.base;
mapInfo.size = regions->entry.len;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"SharedRegionDrv_ioctl",
status,
"Memory_map failed!");
}
else {
regions->entry.base = (Ptr) mapInfo.dst;
}
}
}
}
else {
/* TBD: Need to do Memory_unmap in destroy. */
}
}
GT_1trace (curTrace, GT_LEAVE, "SharedRegionDrv_ioctl", status);
/*! @retval SharedRegion_S_SUCCESS Operation successfully completed. */
return status;
}
/*!
* @brief Function to initialize Shared Driver/device.
*
* @param halObj Pointer to the HAL object
*
* @sa VAYUDSP_phyShmemExit
* Memory_map
*/
Int
VAYUDSP_phyShmemInit (Ptr halObj)
{
Int status = PROCESSOR_SUCCESS;
VAYUDSP_HalObject * halObject = NULL;
Memory_MapInfo mapInfo;
GT_1trace (curTrace, GT_ENTER, "VAYUDSP_phyShmemInit", halObj);
GT_assert (curTrace,(halObj != NULL));
halObject = (VAYUDSP_HalObject *) halObj;
mapInfo.src = DSP_BOOT_ADDR;
mapInfo.size = DSP_BOOT_ADDR_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"VAYUDSP_phyShmemInit",
status,
"Failure in Memory_map for MMU base registers");
halObject->generalCtrlBase = 0;
}
else {
halObject->generalCtrlBase = mapInfo.dst;
}
mapInfo.src = DSP_BOOT_STAT;
mapInfo.size = DSP_BOOT_STAT_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"VAYUDSP_phyShmemInit",
status,
"Failure in Memory_map for MMU base registers");
halObject->bootStatBase = 0;
}
else {
halObject->bootStatBase = mapInfo.dst;
}
mapInfo.src = L2_RAM_CLK_ENABLE;
mapInfo.size = L2_RAM_CLK_ENABLE_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"VAYUDSP_phyShmemInit",
status,
"Failure in Memory_map for MMU base registers");
halObject->l2ClkBase = 0;
}
else {
halObject->l2ClkBase = mapInfo.dst;
}
mapInfo.src = CM_BASE_ADDR;
mapInfo.size = CM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"VAYUDSP_phyShmemInit",
status,
"Failure in Memory_map for MMU base registers");
halObject->cmBase = 0;
}
else {
halObject->cmBase = mapInfo.dst;
}
mapInfo.src = PRM_BASE_ADDR;
mapInfo.size = PRM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"VAYUDSP_phyShmemInit",
status,
"Failure in Memory_map for MMU base registers");
halObject->prmBase = 0;
}
else {
halObject->prmBase = mapInfo.dst;
}
mapInfo.src = MMU0_BASE;
mapInfo.size = MMU0_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"VAYUDSP_phyShmemInit",
status,
"Failure in Memory_map for MMU0 base registers");
halObject->mmu0Base = 0;
}
else {
halObject->mmu0Base = mapInfo.dst;
}
mapInfo.src = MMU1_BASE;
mapInfo.size = MMU1_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"VAYUDSP_phyShmemInit",
status,
"Failure in Memory_map for MMU1 base registers");
halObject->mmu1Base = 0;
}
else {
halObject->mmu1Base = mapInfo.dst;
}
mapInfo.src = DSP_SYS_MMU_CONFIG_BASE;
mapInfo.size = DSP_SYS_MMU_CONFIG_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"VAYUDSP_phyShmemInit",
status,
"Failure in Memory_map for SYS MMU base registers");
halObject->mmuSysBase = 0;
}
else {
halObject->mmuSysBase = mapInfo.dst;
}
mapInfo.src = CTRL_MODULE_BASE;
mapInfo.size = CTRL_MODULE_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"VAYUDSP_phyShmemInit",
status,
"Failure in Memory_map for Ctrl Module base registers");
halObject->ctrlModBase = 0;
}
else {
halObject->ctrlModBase = mapInfo.dst;
}
GT_1trace(curTrace, GT_LEAVE, "<-- VAYUDSP_phyShmemInit: 0x%x", status);
/*! @retval PROCESSOR_SUCCESS Operation successful */
return status;
}
/*!
* @brief Function to initialize the Omap3530IpcInt module.
*
* @param cfg Configuration for setup
*
* @sa Omap3530IpcInt_destroy
*/
Void
Omap3530IpcInt_setup (Omap3530IpcInt_Config * cfg)
{
Memory_MapInfo mapInfo;
Int32 status;
GT_1trace (curTrace, GT_ENTER, "Omap3530IpcInt_setup", cfg);
GT_assert (curTrace, (cfg != NULL));
/* The setup will be called only once, either from SysMgr or from
* archipcomap3530 module. Hence it does not need to be atomic.
*/
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if (cfg == NULL) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"Omap3530IpcInt_setup",
OMAP3530IPCINT_E_FAIL,
"config for driver specific setup can not be NULL");
}
else {
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
Omap3530IpcInt_state.procId = cfg->procId;
Omap3530IpcInt_state.recvIntId = cfg->recvIntId;
/* Map general control base */
mapInfo.src = CORE_CM_BASE;
mapInfo.size = CORE_CM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"Omap3530IpcInt_setup",
status,
"Failure in Memory_map for general ctrl base");
Omap3530IpcInt_state.archCoreCmBase = 0;
}
else {
Omap3530IpcInt_state.archCoreCmBase = mapInfo.dst;
/* Map mailboxBase */
mapInfo.src = MAILBOX_BASE;
mapInfo.size = MAILBOX_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"Omap3530IpcInt_setup",
status,
"Failure in Memory_map for mailboxBase");
Omap3530IpcInt_state.mailboxBase = 0;
}
else {
Omap3530IpcInt_state.mailboxBase = mapInfo.dst;
}
}
if (status >= 0) {
ArchIpcInt_object.fxnTable = &Omap3530IpcInt_fxnTable;
ArchIpcInt_object.obj = &Omap3530IpcInt_state;
ArchIpcInt_object.isSetup = TRUE;
}
#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
GT_0trace (curTrace, GT_LEAVE, "Omap3530IpcInt_setup");
}
/*!
* @brief Function to initialize Shared Driver/device.
*
* @param halObj Pointer to the HAL object
*
* @sa DM8168DSP_phyShmemExit
* Memory_map
*/
Int
DM8168DSP_phyShmemInit (Ptr halObj)
{
Int status = PROCESSOR_SUCCESS;
DM8168DSP_HalObject * halObject = NULL;
Memory_MapInfo mapInfo;
GT_1trace(curTrace, GT_ENTER,
"--> DM8168DSP_phyShmemInit: halObj=0x%x", halObj);
GT_assert (curTrace,(halObj != NULL));
halObject = (DM8168DSP_HalObject *) halObj;
mapInfo.src = DSP_BOOT_ADDR;
mapInfo.size = DSP_BOOT_ADDR_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"DM8168DSP_phyShmemInit",
status,
"Failure in Memory_map for MMU base registers");
halObject->generalCtrlBase = 0;
}
else {
halObject->generalCtrlBase = mapInfo.dst;
}
mapInfo.src = DSP_BOOT_STAT;
mapInfo.size = DSP_BOOT_STAT_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"DM8168DSP_phyShmemInit",
status,
"Failure in Memory_map for MMU base registers");
halObject->bootStatBase = 0;
}
else {
halObject->bootStatBase = mapInfo.dst;
}
mapInfo.src = L2_RAM_CLK_ENABLE;
mapInfo.size = L2_RAM_CLK_ENABLE_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"DM8168DSP_phyShmemInit",
status,
"Failure in Memory_map for MMU base registers");
halObject->l2ClkBase = 0;
}
else {
halObject->l2ClkBase = mapInfo.dst;
}
mapInfo.src = PRCM_BASE_ADDR;
mapInfo.size = PRCM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"DM8168DSP_phyShmemInit",
status,
"Failure in Memory_map for MMU base registers");
halObject->prcmBase = 0;
}
else {
halObject->prcmBase = mapInfo.dst;
}
/* TO BE IMPLEMENTED
mapInfo.src = MMU_BASE;
mapInfo.size = MMU_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"DM8168DSP_phyShmemInit",
status,
"Failure in Memory_map for MMU base registers");
halObject->mmuBase = 0;
}
else {
halObject->mmuBase = mapInfo.dst;
}
*/
GT_1trace(curTrace, GT_LEAVE, "<-- DM8168DSP_phyShmemInit: 0x%x", status);
/*! @retval PROCESSOR_SUCCESS Operation successful */
return status;
}
/*!
* @brief Function to initialize the Dm8168IpcInt module.
*
* @param cfg Configuration for setup
*
* @sa Dm8168IpcInt_destroy
*/
Void
Dm8168IpcInt_setup (Dm8168IpcInt_Config * cfg)
{
#if !defined(SYSLINK_BUILD_OPTIMIZE)
Int status = DM8168IPCINT_SUCCESS;
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
Int i = 0;
Memory_MapInfo mapInfo;
GT_1trace (curTrace, GT_ENTER, "Dm8168IpcInt_setup", cfg);
GT_assert (curTrace, (cfg != NULL));
/* The setup will be called only once, either from SysMgr or from
* archipcdm8168 module. Hence it does not need to be atomic.
*/
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if (cfg == NULL) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"Dm8168IpcInt_setup",
DM8168IPCINT_E_FAIL,
"config for driver specific setup can not be NULL");
}
else {
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
/* Map general control base */
mapInfo.src = AINTC_BASE_ADDR;
mapInfo.size = AINTC_BASE_SIZE;
mapInfo.isCached = FALSE;
#if !defined(SYSLINK_BUILD_OPTIMIZE)
status =
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
Memory_map (&mapInfo);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"Dm8168IpcInt_setup",
status,
"Failure in Memory_map for general ctrl base");
Dm8168IpcInt_state.archCoreCmBase = 0;
}
else {
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
Dm8168IpcInt_state.archCoreCmBase = mapInfo.dst;
/* Map mailboxBase */
mapInfo.src = MAILBOX_BASE;
mapInfo.size = MAILBOX_SIZE;
mapInfo.isCached = FALSE;
#if !defined(SYSLINK_BUILD_OPTIMIZE)
status =
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
Memory_map (&mapInfo);
#if !defined(SYSLINK_BUILD_OPTIMIZE)
if (status < 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"Dm8168IpcInt_setup",
status,
"Failure in Memory_map for mailboxBase");
Dm8168IpcInt_state.mailboxBase = 0;
}
else {
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
Dm8168IpcInt_state.mailboxBase = mapInfo.dst;
#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
}
if (status >= 0) {
/*Registering dm8168 platform with ArchIpcInt*/
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
ArchIpcInt_object.fxnTable = &Dm8168IpcInt_fxnTable;
ArchIpcInt_object.obj = &Dm8168IpcInt_state;
for (i = 0; i < MultiProc_getNumProcessors(); i++ ) {
Atomic_set (&(Dm8168IpcInt_state.isrObjects [i].asserted), 0);
}
/* Calling MultiProc APIs here in setup save time in ISR and makes
* it small and fast with less overhead.
*/
Dm8168IpcInt_state.procIds [DM8168_INDEX_DSP] = MultiProc_getId ("DSP");
Dm8168IpcInt_state.procIds [DM8168_INDEX_VIDEOM3] =
MultiProc_getId ("VIDEO-M3");
Dm8168IpcInt_state.procIds [DM8168_INDEX_VPSSM3] =
MultiProc_getId ("VPSS-M3");
Dm8168IpcInt_state.maxProcessors = MultiProc_getNumProcessors();
ArchIpcInt_object.isSetup = TRUE;
#if !defined(SYSLINK_BUILD_OPTIMIZE)
}
}
#endif /* if !defined(SYSLINK_BUILD_OPTIMIZE) */
GT_0trace (curTrace, GT_LEAVE, "Dm8168IpcInt_setup");
}
/*!
* @brief Function to attach to the PwrMgr.
*
* @param handle Handle to the PwrMgr instance
* @param params Attach parameters
*
* @sa DM8168DUCATIPWR_detach
*/
Int
DM8168DUCATIPWR_attach (PwrMgr_Handle handle, PwrMgr_AttachParams * params)
{
Int status = PWRMGR_SUCCESS;
PwrMgr_Object * pwrMgrHandle = (PwrMgr_Object *) handle;
DM8168DUCATIPWR_Object * object = NULL;
Memory_MapInfo mapInfo;
/* Mapping for prcm base is done in DM8168VIDEOM3_phyShmemInit */
GT_2trace (curTrace, GT_ENTER, "DM8168DUCATIPWR_attach", handle, params);
GT_assert (curTrace, (handle != NULL));
GT_assert (curTrace, (params != NULL));
GT_assert (curTrace, (DM8168DUCATIPWR_state.refCount != 0));
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
if (DM8168DUCATIPWR_state.refCount == 0) {
GT_setFailureReason (curTrace,
GT_4CLASS,
"DM8168DUCATIPWR_attach",
DM8168DUCATIPWR_E_INVALIDSTATE,
"Module was not initialized!");
}
else if (handle == NULL) {
/*! @retval PWRMGR_E_HANDLE Invalid argument */
status = PWRMGR_E_HANDLE;
GT_setFailureReason (curTrace,
GT_4CLASS,
"DM8168DUCATIPWR_attach",
status,
"Invalid handle specified");
}
else {
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined(SYSLINK_BUILD_HLOS) */
object = (DM8168DUCATIPWR_Object *) pwrMgrHandle->object;
GT_assert (curTrace, (object != NULL));
/* Map and get the virtual address for system control module */
mapInfo.src = DM8168M3_PRCM_BASE_ADDR;
mapInfo.size = DM8168M3_PRCM_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
if (status < 0) {
status = DM8168DUCATIPWR_E_FAIL;
GT_setFailureReason (curTrace,
GT_4CLASS,
"DM8168DUCATIPWR_attach",
status,
"Failure in mapping prcm module");
}
else {
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined(SYSLINK_BUILD_HLOS) */
object->prcmVA = mapInfo.dst;
/* Map and get the virtual address for system control module */
mapInfo.src = DUCATI_MMU_CFG;
mapInfo.size = DUCATI_MMU_CFG_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
if (status < 0) {
status = DM8168DUCATIPWR_E_FAIL;
GT_setFailureReason (curTrace,
GT_4CLASS,
"DM8168DUCATIPWR_attach",
status,
"Failure in mapping ducatimmu module");
}
else {
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined(SYSLINK_BUILD_HLOS) */
object->ducatiMmuVA = mapInfo.dst;
/* Map and get the virtual address for system control module */
mapInfo.src = DUCATI_BASE_ADDR;
mapInfo.size = DUCATI_BASE_ADDR_SIZE;
mapInfo.isCached = FALSE;
status = Memory_map (&mapInfo);
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
if (status < 0) {
status = DM8168DUCATIPWR_E_FAIL;
GT_setFailureReason (curTrace,
GT_4CLASS,
"DM8168DUCATIPWR_attach",
status,
"Failure in mapping ducatibase module");
}
else {
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined(SYSLINK_BUILD_HLOS) */
object->ducatibaseVA = mapInfo.dst;
#if !defined(SYSLINK_BUILD_OPTIMIZE) && defined (SYSLINK_BUILD_HLOS)
}
}
}
}
#endif /* #if !defined(SYSLINK_BUILD_OPTIMIZE) && defined(SYSLINK_BUILD_HLOS) */
GT_1trace (curTrace, GT_LEAVE, "DM8168DUCATIPWR_attach", status);
/*! @retval PWRMGR_SUCCESS Operation successful */
return (status);
}
Void printRemoteTraces (Void *args)
{
Int status = 0;
Memory_MapInfo traceinfo;
UInt32 numOfBytesInBuffer = 0;
volatile UInt32 * readPointer;
volatile UInt32 * writePointer;
UInt32 writePos;
Char * traceBuffer;
UInt32 numBytesToCopy;
UInt32 printStart;
UInt32 i;
traceBufferParams * params = (traceBufferParams*)args;
UInt32 coreNameSize = strlen(params->coreName);
Char saveChar;
Osal_printf ("Creating trace thread for %s\n", params->coreName);
/* Get the user virtual address of the buffer */
traceinfo.src = params->bufferAddress;
traceinfo.size = TRACE_BUFFER_SIZE;
status = Memory_map (&traceinfo);
readPointer = (volatile UInt32 *)traceinfo.dst;
writePointer = (volatile UInt32 *)(traceinfo.dst + 0x4);
traceBuffer = (Char *)(traceinfo.dst + 0x8);
/* Initialze read indexes to zero */
*readPointer = 0;
*writePointer = 0;
do {
do {
usleep (TIMEOUT_USECS);
} while (*readPointer == *writePointer);
sem_wait (&semPrint); /* Acquire exclusive access to printing */
/* Copy the trace buffer contents to the scratch buffer. */
memcpy (tempBuffer, params->coreName, coreNameSize);
numOfBytesInBuffer = coreNameSize;
writePos = *writePointer;
if (*readPointer < writePos) {
numBytesToCopy = writePos - (*readPointer);
memcpy (&tempBuffer [numOfBytesInBuffer],
&traceBuffer [*readPointer], numBytesToCopy);
numOfBytesInBuffer += numBytesToCopy;
}
else {
numBytesToCopy = ((TRACE_BUFFER_SIZE - 8) - (*readPointer));
memcpy (&tempBuffer [numOfBytesInBuffer],
&traceBuffer [*readPointer], numBytesToCopy);
numOfBytesInBuffer += numBytesToCopy;
numBytesToCopy = writePos;
memcpy (&tempBuffer [numOfBytesInBuffer], traceBuffer,
numBytesToCopy);
numOfBytesInBuffer += numBytesToCopy;
}
/* Update the read position in shared memory. */
*readPointer = writePos;
/* Print the traces one line at time. */
printStart = 0;
i = coreNameSize;
while ( i < numOfBytesInBuffer ) {
/* Search for a newline */
while (tempBuffer [i] != '\n' && i < numOfBytesInBuffer ) {
i++;
}
/* Pretty print truncated traces at the end of the buffer. */
if (tempBuffer [i] != '\n') {
tempBuffer [i] = '\n';
}
/* Temporarily replace the char after newline with '\0', */
/* print trace, then prefix next trace with core name. */
saveChar = tempBuffer [i + 1];
tempBuffer [i + 1] = 0;
if (log == NULL) {
Osal_printf ("%s", &tempBuffer [printStart]);
}
else {
fprintf (log,"%s", &tempBuffer [printStart]);
}
tempBuffer [i + 1] = saveChar;
i++;
printStart = i - coreNameSize;
memcpy (&tempBuffer [printStart], params->coreName, coreNameSize );
}
if (log != NULL ) {
fflush (log);
}
sem_post (&semPrint); /* Release exclusive access to printing */
} while (1);
Osal_printf ("Leaving %s thread function \n", params->coreName);
return;
}
/*
*========exceptionDumpRegisters=========
*/
static Void exceptionDumpRegisters (Void)
{
Int status;
UInt32 i;
volatile ExcContext * excContext;
Memory_MapInfo traceinfo;
Char * ttype;
traceinfo.src = CONTEXTBUFFERADD;
traceinfo.size = 0x80;
status = Memory_map (&traceinfo);
if (status!= MEMORYOS_SUCCESS) {
Osal_printf ("Memory_map failed\n");
}
else {
Osal_printf ("\nContext traceinfo.dst = 0x%x traceinfo.size = 0x%x\n",
traceinfo.dst, traceinfo.size);
}
/* Fill the Structure with data from memory */
excContext = (volatile ExcContext *) traceinfo.dst;
Osal_printf ("========================================================\n");
Osal_printf ("===================== CONTEXT DUMP =====================\n");
Osal_printf ("========================================================\n");
switch (excContext->threadType) {
case BIOS_ThreadType_Task:
ttype = "Task";
break;
case BIOS_ThreadType_Swi:
ttype = "Swi";
break;
case BIOS_ThreadType_Hwi:
ttype = "Hwi";
break;
case BIOS_ThreadType_Main:
ttype = "Main";
break;
default:
ttype = "Unknown_thread";
}
Osal_printf ("Exception occurred in ThreadType_%s.\n", ttype);
Osal_printf ("%s handle: 0x%x.\n", ttype, excContext->threadHandle);
Osal_printf ("%s stack base: 0x%x.\n", ttype, excContext->threadStack);
Osal_printf ("%s stack size: 0x%x.\n", ttype, excContext->threadStackSize);
Osal_printf ("R0 = %08x R8 = %08x\n", excContext->r0, excContext->r8);
Osal_printf ("R1 = %08x R9 = %08x\n", excContext->r1, excContext->r9);
Osal_printf ("R2 = %08x R10 = %08x\n", excContext->r2, excContext->r10);
Osal_printf ("R3 = %08x R11 = %08x\n", excContext->r3, excContext->r11);
Osal_printf ("R4 = %08x R12 = %08x\n", excContext->r4, excContext->r12);
Osal_printf ("R5 = %08x SP(R13) = %08x\n", excContext->r5, excContext->sp);
Osal_printf ("R6 = %08x LR(R14) = %08x\n", excContext->r6, excContext->lr);
Osal_printf ("R7 = %08x PC(R15) = %08x\n", excContext->r7, excContext->pc);
Osal_printf ("PSR = %08x\n", excContext->psr);
Osal_printf ("ICSR = %08x\n", excContext->ICSR);
Osal_printf ("MMFSR = %02x\n", excContext->MMFSR);
Osal_printf ("BFSR = %02x\n", excContext->BFSR);
Osal_printf ("UFSR = %04x\n", excContext->UFSR);
Osal_printf ("HFSR = %08x\n", excContext->HFSR);
Osal_printf ("DFSR = %08x\n", excContext->DFSR);
Osal_printf ("MMAR = %08x\n", excContext->MMAR);
Osal_printf ("BFAR = %08x\n", excContext->BFAR);
Osal_printf ("AFSR = %08x\n", excContext->AFSR);
Osal_printf ("\n");
traceinfo.src = STACKBUFFERADD;
traceinfo.size = excContext->threadStackSize + 4;
if (traceinfo.size > STACKBUFFERSZE - 4) {
Osal_printf ("ERROR: Stack size larger than allocated space. Limiting "
"to 12KB\n");
traceinfo.size = STACKBUFFERSZE;
}
status = Memory_map (&traceinfo);
if (status!= MEMORYOS_SUCCESS) {
Osal_printf ("Memory_map failed\n");
}
else {
Osal_printf ("Stack traceinfo.dst = 0x%x traceinfo.size = 0x%x\n",
traceinfo.dst, traceinfo.size);
}
Osal_printf ("========================================================\n");
Osal_printf ("====================== STACK DUMP ======================\n");
Osal_printf ("========================================================\n");
for (i = traceinfo.dst; i < traceinfo.dst + traceinfo.size ; i=i + 4) {
Osal_printf ("[%04d]:%08x\n", (i - traceinfo.dst)/4 ,
*((volatile UInt32 *) i));
}
}
