Ejemplo n.º 1
0
void ni_tio_init_counter(struct ni_gpct *counter)
{
	struct ni_gpct_device *counter_dev = counter->counter_dev;

	ni_tio_reset_count_and_disarm(counter);
	/* initialize counter registers */
	counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] =
	    0x0;
	write_register(counter,
		       counter_dev->
		       regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)],
		       NITIO_Gi_Autoincrement_Reg(counter->counter_index));
	ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
			~0, Gi_Synchronize_Gate_Bit);
	ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index), ~0,
			0);
	counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0;
	write_register(counter,
		       counter_dev->
		       regs[NITIO_Gi_LoadA_Reg(counter->counter_index)],
		       NITIO_Gi_LoadA_Reg(counter->counter_index));
	counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = 0x0;
	write_register(counter,
		       counter_dev->
		       regs[NITIO_Gi_LoadB_Reg(counter->counter_index)],
		       NITIO_Gi_LoadB_Reg(counter->counter_index));
	ni_tio_set_bits(counter,
			NITIO_Gi_Input_Select_Reg(counter->counter_index), ~0,
			0);
	if (ni_tio_counting_mode_registers_present(counter_dev)) {
		ni_tio_set_bits(counter,
				NITIO_Gi_Counting_Mode_Reg(counter->
							   counter_index), ~0,
				0);
	}
	if (ni_tio_second_gate_registers_present(counter_dev)) {
		counter_dev->
		    regs[NITIO_Gi_Second_Gate_Reg(counter->counter_index)] =
		    0x0;
		write_register(counter,
			       counter_dev->
			       regs[NITIO_Gi_Second_Gate_Reg
				    (counter->counter_index)],
			       NITIO_Gi_Second_Gate_Reg(counter->
							counter_index));
	}
	ni_tio_set_bits(counter,
			NITIO_Gi_DMA_Config_Reg(counter->counter_index), ~0,
			0x0);
	ni_tio_set_bits(counter,
			NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
			~0, 0x0);
}
Ejemplo n.º 2
0
static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
{
	const unsigned bits = read_register(counter,
		NITIO_Gxx_Status_Reg(counter->counter_index));

	if (bits & Gi_Next_Load_Source_Bit(counter->counter_index)) {
		return NITIO_Gi_LoadB_Reg(counter->counter_index);
	} else {
		return NITIO_Gi_LoadA_Reg(counter->counter_index);
	}
}
Ejemplo n.º 3
0
int ni_tio_rinsn(struct ni_gpct *counter, struct comedi_insn *insn,
		 unsigned int *data)
{
	struct ni_gpct_device *counter_dev = counter->counter_dev;
	const unsigned channel = CR_CHAN(insn->chanspec);
	unsigned first_read;
	unsigned second_read;
	unsigned correct_read;

	if (insn->n < 1)
		return 0;
	switch (channel) {
	case 0:
		ni_tio_set_bits(counter,
				NITIO_Gi_Command_Reg(counter->counter_index),
				Gi_Save_Trace_Bit, 0);
		ni_tio_set_bits(counter,
				NITIO_Gi_Command_Reg(counter->counter_index),
				Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
		/* The count doesn't get latched until the next clock edge, so it is possible the count
		   may change (once) while we are reading.  Since the read of the SW_Save_Reg isn't
		   atomic (apparently even when it's a 32 bit register according to 660x docs),
		   we need to read twice and make sure the reading hasn't changed.  If it has,
		   a third read will be correct since the count value will definitely have latched by then. */
		first_read =
		    read_register(counter,
				  NITIO_Gi_SW_Save_Reg(counter->counter_index));
		second_read =
		    read_register(counter,
				  NITIO_Gi_SW_Save_Reg(counter->counter_index));
		if (first_read != second_read)
			correct_read =
			    read_register(counter,
					  NITIO_Gi_SW_Save_Reg(counter->
							       counter_index));
		else
			correct_read = first_read;
		data[0] = correct_read;
		return 0;
		break;
	case 1:
		data[0] =
		    counter_dev->
		    regs[NITIO_Gi_LoadA_Reg(counter->counter_index)];
		break;
	case 2:
		data[0] =
		    counter_dev->
		    regs[NITIO_Gi_LoadB_Reg(counter->counter_index)];
		break;
	}
	return 0;
}
Ejemplo n.º 4
0
int ni_tio_winsn(struct ni_gpct *counter, struct comedi_insn *insn,
		 unsigned int *data)
{
	struct ni_gpct_device *counter_dev = counter->counter_dev;
	const unsigned channel = CR_CHAN(insn->chanspec);
	unsigned load_reg;

	if (insn->n < 1)
		return 0;
	switch (channel) {
	case 0:
		/* Unsafe if counter is armed.  Should probably check status and return -EBUSY if armed. */
		/* Don't disturb load source select, just use whichever load register is already selected. */
		load_reg = ni_tio_next_load_register(counter);
		write_register(counter, data[0], load_reg);
		ni_tio_set_bits_transient(counter,
					  NITIO_Gi_Command_Reg(counter->
							       counter_index),
					  0, 0, Gi_Load_Bit);
		/* restore state of load reg to whatever the user set last set it to */
		write_register(counter, counter_dev->regs[load_reg], load_reg);
		break;
	case 1:
		counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] =
		    data[0];
		write_register(counter, data[0],
			       NITIO_Gi_LoadA_Reg(counter->counter_index));
		break;
	case 2:
		counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] =
		    data[0];
		write_register(counter, data[0],
			       NITIO_Gi_LoadB_Reg(counter->counter_index));
		break;
	default:
		return -EINVAL;
		break;
	}
	return 0;
}
Ejemplo n.º 5
0
int ni_tio_winsn(struct ni_gpct *counter, struct comedi_insn *insn,
		 unsigned int *data)
{
	struct ni_gpct_device *counter_dev = counter->counter_dev;
	const unsigned channel = CR_CHAN(insn->chanspec);
	unsigned load_reg;

	if (insn->n < 1)
		return 0;
	switch (channel) {
	case 0:
		
		
		load_reg = ni_tio_next_load_register(counter);
		write_register(counter, data[0], load_reg);
		ni_tio_set_bits_transient(counter,
					  NITIO_Gi_Command_Reg(counter->
							       counter_index),
					  0, 0, Gi_Load_Bit);
		
		write_register(counter, counter_dev->regs[load_reg], load_reg);
		break;
	case 1:
		counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] =
		    data[0];
		write_register(counter, data[0],
			       NITIO_Gi_LoadA_Reg(counter->counter_index));
		break;
	case 2:
		counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] =
		    data[0];
		write_register(counter, data[0],
			       NITIO_Gi_LoadB_Reg(counter->counter_index));
		break;
	default:
		return -EINVAL;
		break;
	}
	return 0;
}
Ejemplo n.º 6
0
int ni_tio_rinsn(struct ni_gpct *counter, struct comedi_insn *insn,
		 unsigned int *data)
{
	struct ni_gpct_device *counter_dev = counter->counter_dev;
	const unsigned channel = CR_CHAN(insn->chanspec);
	unsigned first_read;
	unsigned second_read;
	unsigned correct_read;

	if (insn->n < 1)
		return 0;
	switch (channel) {
	case 0:
		ni_tio_set_bits(counter,
				NITIO_Gi_Command_Reg(counter->counter_index),
				Gi_Save_Trace_Bit, 0);
		ni_tio_set_bits(counter,
				NITIO_Gi_Command_Reg(counter->counter_index),
				Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
		
		first_read =
		    read_register(counter,
				  NITIO_Gi_SW_Save_Reg(counter->counter_index));
		second_read =
		    read_register(counter,
				  NITIO_Gi_SW_Save_Reg(counter->counter_index));
		if (first_read != second_read)
			correct_read =
			    read_register(counter,
					  NITIO_Gi_SW_Save_Reg(counter->
							       counter_index));
		else
			correct_read = first_read;
		data[0] = correct_read;
		return 0;
		break;
	case 1:
		data[0] =
		    counter_dev->
		    regs[NITIO_Gi_LoadA_Reg(counter->counter_index)];
		break;
	case 2:
		data[0] =
		    counter_dev->
		    regs[NITIO_Gi_LoadB_Reg(counter->counter_index)];
		break;
	};
	return 0;
}