void expand_time(struct time_exp_t *xt, uint64_t wall_clock)
{
uint32_t time = NS_TO_SECS(wall_clock);
unsigned long dayclock, dayno;
int year = EPOCH_YR;
dayclock = (unsigned long)time % SECS_DAY;
dayno = (unsigned long)time / SECS_DAY;
xt->tm_usec = NS_TO_US(wall_clock) % 1000000ULL;
xt->tm_sec = dayclock % 60;
xt->tm_min = (dayclock % 3600) / 60;
xt->tm_hour = dayclock / 3600;
xt->tm_wday = (dayno + 4) % 7; /* day 0 was a thursday */
while (dayno >= YEARSIZE(year)) {
dayno -= YEARSIZE(year);
year++;
}
xt->tm_year = year - YEAR0;
xt->tm_yday = dayno;
xt->tm_mon = 0;
while (dayno >= _ytab[LEAPYEAR(year)][xt->tm_mon]) {
dayno -= _ytab[LEAPYEAR(year)][xt->tm_mon];
xt->tm_mon++;
}
xt->tm_mday = dayno + 1;
xt->tm_isdst = 0;
xt->tm_gmtoff = 0;
}
/** Initializes a QH structure.
*
* @param[in] _hcd The HCD state structure for the DWC OTG controller.
* @param[in] _qh The QH to init.
* @param[in] _urb Holds the information about the device/endpoint that we need
* to initialize the QH. */
#define SCHEDULE_SLOP 10
#define SCHEDULE_SPLIT_SLOP 10 /* 1 == 125us, 10 -> 1.25ms, 20 -> 2.5ms, */
void dwc_otg_hcd_qh_init(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh,
struct urb *_urb)
{
memset(_qh, 0, sizeof(dwc_otg_qh_t));
/* Initialize QH */
switch (usb_pipetype(_urb->pipe)) {
case PIPE_CONTROL:
_qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
break;
case PIPE_BULK:
_qh->ep_type = USB_ENDPOINT_XFER_BULK;
break;
case PIPE_ISOCHRONOUS:
_qh->ep_type = USB_ENDPOINT_XFER_ISOC;
break;
case PIPE_INTERRUPT:
_qh->ep_type = USB_ENDPOINT_XFER_INT;
break;
}
_qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0;
_qh->data_toggle = DWC_OTG_HC_PID_DATA0;
_qh->maxp =
usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe)));
INIT_LIST_HEAD(&_qh->qtd_list);
INIT_LIST_HEAD(&_qh->qh_list_entry);
_qh->channel = NULL;
/* FS/LS Enpoint on HS Hub
* NOT virtual root hub */
_qh->do_split = 0;
if (((_urb->dev->speed == USB_SPEED_LOW) ||
(_urb->dev->speed == USB_SPEED_FULL)) &&
(_urb->dev->tt) && (_urb->dev->tt->hub)
&& (_urb->dev->tt->hub->devnum != 1)) {
DWC_DEBUGPL(DBG_HCD,
"QH init: EP %d: TT found at hub addr %d, for port %d\n",
usb_pipeendpoint(_urb->pipe),
_urb->dev->tt->hub->devnum, _urb->dev->ttport);
_qh->do_split = 1;
}
if (_qh->ep_type == USB_ENDPOINT_XFER_INT ||
_qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
/* Compute scheduling parameters once and save them. */
hprt0_data_t hprt;
/** @todo Account for split transfers in the bus time. */
int bytecount =
dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp);
int usecs = /*FIXME: hardcode to highspeed, to fix Full/Low speed device via Hub*/
usb_calc_bus_time(/*_urb->dev->speed*/USB_SPEED_HIGH, usb_pipein(_urb->pipe),
(_qh->ep_type == USB_ENDPOINT_XFER_ISOC),
bytecount);
_qh->usecs = NS_TO_US(usecs);
/* Start in a slightly future (micro)frame. */
_qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number,
SCHEDULE_SLOP);
_qh->interval = _urb->interval;
#if 0
/* Increase interrupt polling rate for debugging. */
if (_qh->ep_type == USB_ENDPOINT_XFER_INT) {
_qh->interval = 8;
}
#endif
hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0);
if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
((_urb->dev->speed == USB_SPEED_LOW) ||
(_urb->dev->speed == USB_SPEED_FULL))) {
_qh->interval *= 8;
_qh->sched_frame |= 0x7;
_qh->start_split_frame = _qh->sched_frame;
}
}else{
if(_qh->do_split){
_qh->interval = SCHEDULE_SPLIT_SLOP;
_qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number,
_qh->interval);
};
}
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
_urb->dev->devnum);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
usb_pipeendpoint(_urb->pipe),
usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", ( {
char *speed;
switch(_urb->dev->speed) {
case USB_SPEED_LOW:
speed = "low"; break;
case USB_SPEED_FULL:
speed = "full"; break;
case USB_SPEED_HIGH:
speed = "high"; break;
default:
speed = "?"; break;};
speed;})) ;
void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, struct urb *urb)
{
char *speed, *type;
memset (qh, 0, sizeof (dwc_otg_qh_t));
/* Initialize QH */
switch (usb_pipetype(urb->pipe)) {
case PIPE_CONTROL:
qh->ep_type = USB_ENDPOINT_XFER_CONTROL;
break;
case PIPE_BULK:
qh->ep_type = USB_ENDPOINT_XFER_BULK;
break;
case PIPE_ISOCHRONOUS:
qh->ep_type = USB_ENDPOINT_XFER_ISOC;
break;
case PIPE_INTERRUPT:
qh->ep_type = USB_ENDPOINT_XFER_INT;
break;
}
qh->ep_is_in = usb_pipein(urb->pipe) ? 1 : 0;
qh->data_toggle = DWC_OTG_HC_PID_DATA0;
qh->maxp = usb_maxpacket(urb->dev, urb->pipe, !(usb_pipein(urb->pipe)));
INIT_LIST_HEAD(&qh->qtd_list);
INIT_LIST_HEAD(&qh->qh_list_entry);
qh->channel = NULL;
/* FS/LS Enpoint on HS Hub
* NOT virtual root hub */
qh->do_split = 0;
if (((urb->dev->speed == USB_SPEED_LOW) ||
(urb->dev->speed == USB_SPEED_FULL)) &&
(urb->dev->tt) && (urb->dev->tt->hub) && (urb->dev->tt->hub->devnum != 1))
{
DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n",
usb_pipeendpoint(urb->pipe), urb->dev->tt->hub->devnum,
urb->dev->ttport);
qh->do_split = 1;
}
if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
/* Compute scheduling parameters once and save them. */
hprt0_data_t hprt;
/** @todo Account for split transfers in the bus time. */
int bytecount = dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
/* FIXME: work-around patch by Steven */
qh->usecs = NS_TO_US(usb_calc_bus_time(urb->dev->speed,
usb_pipein(urb->pipe),
(qh->ep_type == USB_ENDPOINT_XFER_ISOC),
bytecount));
/* Start in a slightly future (micro)frame. */
qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
SCHEDULE_SLOP);
qh->interval = urb->interval;
#if 0
/* Increase interrupt polling rate for debugging. */
if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
qh->interval = 8;
}
#endif
hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
((urb->dev->speed == USB_SPEED_LOW) ||
(urb->dev->speed == USB_SPEED_FULL))) {
qh->interval *= 8;
qh->sched_frame |= 0x7;
qh->start_split_frame = qh->sched_frame;
}
}
DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n",
urb->dev->devnum);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n",
usb_pipeendpoint(urb->pipe),
usb_pipein(urb->pipe) == USB_DIR_IN ? "IN" : "OUT");
switch(urb->dev->speed) {
case USB_SPEED_LOW:
speed = "low";
break;
case USB_SPEED_FULL:
speed = "full";
break;
case USB_SPEED_HIGH:
speed = "high";
break;
default:
speed = "?";
break;
}
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed);
switch (qh->ep_type) {
case USB_ENDPOINT_XFER_ISOC:
type = "isochronous";
break;
case USB_ENDPOINT_XFER_INT:
type = "interrupt";
break;
case USB_ENDPOINT_XFER_CONTROL:
type = "control";
break;
case USB_ENDPOINT_XFER_BULK:
type = "bulk";
break;
default:
type = "?";
break;
}
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n",type);
#ifdef DEBUG
if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
qh->usecs);
DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
qh->interval);
}
#endif
qh->dw_align_buf = NULL;
return;
}
static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
struct dwc2_hcd_urb *urb)
{
int dev_speed, hub_addr, hub_port;
char *speed, *type;
dev_vdbg(hsotg->dev, "%s()\n", __func__);
/* Initialize QH */
qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
qh->data_toggle = DWC2_HC_PID_DATA0;
qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info);
INIT_LIST_HEAD(&qh->qtd_list);
INIT_LIST_HEAD(&qh->qh_list_entry);
/* FS/LS Endpoint on HS Hub, NOT virtual root hub */
dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) &&
hub_addr != 0 && hub_addr != 1) {
dev_vdbg(hsotg->dev,
"QH init: EP %d: TT found at hub addr %d, for port %d\n",
dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr,
hub_port);
qh->do_split = 1;
}
if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
/* Compute scheduling parameters once and save them */
u32 hprt, prtspd;
/* Todo: Account for split transfers in the bus time */
int bytecount =
dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
qh->usecs = NS_TO_US(usb_calc_bus_time(qh->do_split ?
USB_SPEED_HIGH : dev_speed, qh->ep_is_in,
qh->ep_type == USB_ENDPOINT_XFER_ISOC,
bytecount));
/* Start in a slightly future (micro)frame */
qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
SCHEDULE_SLOP);
qh->interval = urb->interval;
#if 0
/* Increase interrupt polling rate for debugging */
if (qh->ep_type == USB_ENDPOINT_XFER_INT)
qh->interval = 8;
#endif
hprt = readl(hsotg->regs + HPRT0);
prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
if (prtspd == HPRT0_SPD_HIGH_SPEED &&
(dev_speed == USB_SPEED_LOW ||
dev_speed == USB_SPEED_FULL)) {
qh->interval *= 8;
qh->sched_frame |= 0x7;
qh->start_split_frame = qh->sched_frame;
}
dev_dbg(hsotg->dev, "interval=%d\n", qh->interval);
}
