/**
* NTRXRxReceive:
*
* NTRXRxReceive() read out the payload of a received message and
* calls the upper layer/application
*
* Returns: none
*
*/
void NTRXRxReceive (void)
{
MyByte8T status;
MyByte8T *rxPayload;
MyByte8T len = 0;
MyByte8T value;
MyByte8T source[DIMADDRESS];
MyByte8T dest[DIMADDRESS];
MyByte8T reg[2];
MyWord16T id;
NTRXReadSPI (NA_RxCrc2Stat_O, &status, 1);
/* check if data is valid */
if ((status & (1 << NA_RxCrc2Stat_B)) == (1 << NA_RxCrc2Stat_B))
{
rxPayload = buff_rx;
NTRXSetIndexReg (0);
/* read destination address */
NTRXReadSPI (NA_RamRxDstAddr_O, dest, sizeof(MyAddressT));
/* read source address */
NTRXReadSPI (NA_RamRxSrcAddr_O, source, sizeof(MyAddressT));
/* read length plus additionl bits */
NTRXReadSPI (NA_RamRxLength_O, reg, 2);
rState = reg[1]>>5;
len = (reg[0] | (reg[1] & 0x1F) << 8);
if (len > 128)
{
len = 0;
}
else
{
NTRXSetIndexReg (2);
/* read user data*/
NTRXReadSPI ((NA_RamRxBuffer_O & 0xFF), rxPayload, len);
}
}
/**
* NTRXTxHeader:
*
* @addr: -input- data to be transmitted to destination
* @len: -input- length of payload to be written into transmit buffer
* @rsvd: -input- reserved for future use
* @seq_n: -input- sequence bit for detecting dublicated messages
* @flush: -input- flush bit for syncronizing with peer
*
* NTRXTxData() writes len bytes of payload to transmit buffer of nanoNET TRX chip
*
* Returns: none
*
*/
void NTRXTxHeader (MyByte8T *addr, MyWord16T len, MyByte8T rsvd, MyByte8T seq_n, MyByte8T flush)
{
MyByte8T txLen[8];
NTRXSetIndexReg (0);
/* copy the destination address to temp buffer */
NTRXWriteSPI (NA_RamTxDstAddr_O, addr, 6);
/* merge the three bits into the temp buffer */
txLen[0] = (MyByte8T)len;
txLen[1] = (len & 0x1F00) >> 8;
txLen[1] |= (rsvd == 1) ? 0x20 : 0;
txLen[1] |= (seq_n == 1) ? 0x40 : 0;
txLen[1] |= (flush == 1) ? 0x80 : 0;
NTRXWriteSPI (NA_RamTxLength_O, txLen, 2);
}
void PDCallback (void)
/****************************************************************************/
{
MyByte8T status;
MyByte8T reg[2];
/*
* use 1 led to indicate message reception on the devBoard
* The led will stay on for a 50 ms.
*/
# ifdef CONFIG_TRAFFIC_LED
TRIGGER_LED_RX ();
# endif /* CONFIG_TRAFFIC_LED */
/*
* read the crc2 status register
*/
NTRXSPIReadByte (NA_RxCrc2Stat_O, &status);
rxIrq = 0;
/* check if data is valid */
if ((status & (1 << NA_RxCrc2Stat_B)) != 0)
{
NTRXSetIndexReg (0);
/* read source address */
NTRXSPIRead (NA_RamRxSrcAddr_O, upMsg.addr, 6);
/* read length plus additionl bits */
NTRXSPIRead (NA_RamRxLength_O, reg, 2);
rState = reg[1]>>5;
/* read destination address */
# ifdef CONFIG_NTRX_SNIFFER
NTRXSPIRead (NA_RamRxDstAddr_O, upMsg.rxAddr, 6);
upMsg.count++;
upMsg.extBits = rState;
upMsg.frameType = (status & 0x0f);
# endif
upMsg.len = reg[0];
if (upMsg.len > PHY_PACKET_SIZE)
{
/* restart receiver */
if (phyPIB.rxState == PHY_RX_ON)
{
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B)
| (0x03 << NA_RxBufferCmd_LSB));
}
}
else
{
if (buffSwapped == TRUE)
{
buffSwapped = FALSE;
/* SWAP BUFFER for receive*/
ntrxShadowReg[NA_SwapBbBuffers_O] &= ~(1 << NA_SwapBbBuffers_B);
NTRXSPIWriteByte (NA_SwapBbBuffers_O, ntrxShadowReg[NA_SwapBbBuffers_O]);
NTRXSetIndexReg (3);
}
else
{
buffSwapped = TRUE;
/* SWAP BUFFER for receive*/
ntrxShadowReg[NA_SwapBbBuffers_O] |= (1 << NA_SwapBbBuffers_B);
NTRXSPIWriteByte (NA_SwapBbBuffers_O, ntrxShadowReg[NA_SwapBbBuffers_O]);
NTRXSetIndexReg (2);
}
tiPhyRxTimeout_once = FALSE;
tiPhyRxTimeout = hwclock() + phyPIB.phyRxTimeout;
/*
* restart receiver and than read rx buffer. This is ok because we use
* buffer swapping.
*/
if (phyPIB.rxState == PHY_RX_ON)
{
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B)
| (0x03 << NA_RxBufferCmd_LSB));
}
NTRXSPIRead ((MyByte8T)(NA_RamRxBuffer_O & 0xFF), upMsg.data, upMsg.len);
NTRXSetIndexReg (0);
#ifdef CONFIG_NTRX_SNIFFER
upMsg.value = 0xff;
upMsg.prim = PD_DATA_INDICATION;
SendMsgUp (&upMsg);
#else
/*
* if address matching off, ignore rangingstates
* this path is used for normal data reception
* ranging is handled in the else path
*/
if (((ntrxShadowReg[NA_RxAddrMode_O] & (1<<NA_RxAddrMode_B)) == 0) ||
(lState == RANGING_READY && rState == RANGING_READY))
{
upMsg.value = 0xff;
upMsg.prim = PD_DATA_INDICATION;
SendMsgUp (&upMsg);
}
else if((lState == RANGING_READY) && (rState == RANGING_START || rState == RANGING_FAST_START))
{
memcpy(rDest, upMsg.addr, 6);
RangingCallback_Rx(upMsg.data, upMsg.len);
if(rState == RANGING_START)
{
lState = RANGING_ANSWER1;
/* send ranging packet */
RangingMode(RANGING_ANSWER1, rDest);
}else if (rState == RANGING_FAST_START)
{
lState = RANGING_FAST_ANSWER1;
/* send ranging packet */
RangingMode(RANGING_FAST_ANSWER1, rDest);
}
}
else if((memcmp(rDest, upMsg.addr, 6) == 0) && lState == RANGING_ANSWER1 && rState == RANGING_ANSWER1)
{
/* received ranging data to RangingCallback_Rx
* (without protocol header stuff)
*/
RangingCallback_Rx(upMsg.data, upMsg.len);
lState = RANGING_ANSWER2;
}
else if((memcmp(rDest, upMsg.addr, 6) == 0) &&
((lState == RANGING_ANSWER2 && rState == RANGING_ANSWER2) ||
(lState == RANGING_FAST_ANSWER1 && rState == RANGING_FAST_ANSWER1)))
{
/* ranging was successfull, stop timeout */
NTRXStopBbTimer();
/* received ranging data to RangingCallback_Rx
*(without protocol header stuff)
*/
RangingCallback_Rx(upMsg.data, upMsg.len);
/* calculate the distance */
rangingPIB.distance = getDistance();
rangingPIB.rssi = getRSSI();
if (rangingPIB.distance < 0.0)
rangingPIB.error = STAT_RANGING_VALUE_ERROR;
upMsg.value = 0xff;
memcpy(upMsg.data, (MyByte8T*) &rangingPIB, sizeof(RangingPIB));
upMsg.len = sizeof(RangingPIB);
if (rState == RANGING_ANSWER2)
upMsg.prim = PD_RANGING_INDICATION;
else if (rState == RANGING_FAST_ANSWER1)
upMsg.prim = PD_RANGING_FAST_INDICATION;
/* set ready for new ranging */
lState = RANGING_READY;
SendMsgUp (&upMsg);
}
# endif
}
}
void PLMESap (MyMsgT *msg)
/****************************************************************************/
{
MyByte8T bw = 0, sd = 0, br = 0, cf = 0;
switch (msg->prim)
{
case PLME_GET_REQUEST: msg->prim = PLME_GET_CONFIRM;
msg->status = PHY_SUCCESS;
switch (msg->attribute)
{
case PHY_CURRENT_CHANNEL: msg->value = phyPIB.currentChannel;
break;
case PHY_TRX_MODE: msg->value = phyPIB.trxMode;
break;
case PHY_LOG_CHANNEL: msg->value = phyPIB.logChannel;
break;
case PHY_TX_POWER: msg->value = phyPIB.txPower;
break;
case PHY_ARQ: msg->value = phyPIB.arqMode;
break;
case PHY_ARQ_MAX: msg->value = phyPIB.arqMax;
break;
case PHY_FEC: msg->value = phyPIB.fec;
break;
case PHY_MAC_ADDRESS1: memcpy (msg->data, phyPIB.macAddr0, 6);
break;
case PHY_MAC_ADDRESS2: memcpy (msg->data, phyPIB.macAddr0, 6);
break;
case PHY_TX_ADDR_SELECT: msg->value = phyPIB.txAddrSel;
break;
case PHY_ADDR_MATCHING: msg->value = phyPIB.addrMatch;
break;
case PHY_PWR_DOWN_MODE: msg->value = phyPIB.pwrDownMode;
break;
case PHY_RECALIBRATION: msg->value = phyPIB.recalInterval / 1000;
break;
case PHY_FRAME_TYPE: msg->value = phyPIB.frameType;
break;
case PHY_TESTMODE: msg->value = phyPIB.testmode;
break;
case PHY_RX_STATE: msg->value = phyPIB.rxState;
break;
default: msg->status = PHY_UNSUPPORTED_ATTRIBUTE;
break;
}
SendCfgUp (msg);
break;
case PLME_SET_REQUEST: msg->prim = PLME_SET_CONFIRM;
msg->status = PHY_SUCCESS;
switch (msg->attribute)
{
case PHY_CURRENT_CHANNEL: if (msg->value > 16)
{
msg->status = PHY_INVALID_PARAMETER;
}
else
{
phyPIB.currentChannel = msg->value;
switch (phyPIB.currentChannel)
{
case 0: bw = NA_80MHz; sd = NA_1us; br = NA_1M_S;
break;
default:bw = NA_22MHz; sd = NA_4us; br = NA_250k_S;
break;
}
NTRXSetChannel (phyPIB.currentChannel);
NTRXSetupTrxMode (bw, sd, br);
}
break;
case PHY_LOG_CHANNEL: if (msg->value > CONFIG_MAX_LOG_CHANNEL - 1)
{
msg->status = PHY_INVALID_PARAMETER;
}
else
{
phyPIB.logChannel = msg->value;
switch (phyPIB.logChannel)
{
case 1: bw = NA_22MHz; sd = NA_4us; br = NA_250k_S;
cf = 1;
ntrxShadowReg[NA_UseFec_O] &= ~(1 << NA_UseFec_B);
break;
case 2: bw = NA_22MHz; sd = NA_4us; br = NA_250k_S;
cf = 7;
ntrxShadowReg[NA_UseFec_O] &= ~(1 << NA_UseFec_B);
break;
case 3: bw = NA_22MHz; sd = NA_4us; br = NA_250k_S;
cf = 13;
ntrxShadowReg[NA_UseFec_O] &= ~(1 << NA_UseFec_B);
break;
default: bw = NA_80MHz; sd = NA_1us; br = NA_1M_S;
cf = 0;
ntrxShadowReg[NA_UseFec_O] &= ~(1 << NA_UseFec_B);
break;
}
NTRXSPIWriteByte (NA_UseFec_O, ntrxShadowReg[NA_UseFec_O]);
NTRXSetChannel (cf);
NTRXSetupTrxMode (bw, sd, br);
}
break;
case PHY_TRX_MODE:
phyPIB.trxMode = msg->value;
switch (msg->value)
{
# ifdef CONFIG_NTRX_80MHZ_500NS
case 10: bw = NA_80MHz; sd = NA_500ns; br = NA_125k_S; break;
case 11: bw = NA_80MHz; sd = NA_500ns; br = NA_1M_S; break;
case 12: bw = NA_80MHz; sd = NA_500ns; br = NA_2M_S; break;
# endif /* CONFIG_NTRX_80MHZ_500NS */
# ifdef CONFIG_NTRX_80MHZ_1000NS
case 20: bw = NA_80MHz; sd = NA_1us; br = NA_500k_S; break;
case 21: bw = NA_80MHz; sd = NA_1us; br = NA_1M_S; break;
# endif /* CONFIG_NTRX_80MHZ_1000NS */
# ifdef CONFIG_NTRX_80MHZ_2000NS
case 30: bw = NA_80MHz; sd = NA_2us; br = NA_125k_S; break;
case 31: bw = NA_80MHz; sd = NA_2us; br = NA_250k_S; break;
case 32: bw = NA_80MHz; sd = NA_2us; br = NA_500k_S; break;
# endif /* CONFIG_NTRX_80MHZ_2000NS */
# ifdef CONFIG_NTRX_80MHZ_4000NS
case 40: bw = NA_80MHz; sd = NA_4us; br = NA_125k_S; break;
case 41: bw = NA_80MHz; sd = NA_4us; br = NA_250k_S; break;
# endif /* CONFIG_NTRX_80MHZ_4000NS */
# ifdef CONFIG_NTRX_22MHZ_1000NS
case 50: bw = NA_22MHz; sd = NA_1us; br = NA_1M_S; break;
# endif /* CONFIG_NTRX_22MHZ_1000NS */
# ifdef CONFIG_NTRX_22MHZ_2000NS
case 60: bw = NA_22MHz; sd = NA_2us; br = NA_125k_S; break;
case 61: bw = NA_22MHz; sd = NA_2us; br = NA_250k_S; break;
case 62: bw = NA_22MHz; sd = NA_2us; br = NA_500k_S; break;
# endif /* CONFIG_NTRX_22MHZ_2000NS */
# ifdef CONFIG_NTRX_22MHZ_4000NS
case 70: bw = NA_22MHz; sd = NA_4us; br = NA_125k_S; break;
case 71: bw = NA_22MHz; sd = NA_4us; br = NA_250k_S; break;
# endif /* CONFIG_NTRX_22MHZ_4000NS */
default: printf ("Valid modes: 10-43 (80Mhz) 50-84 (22Mhz) 90-93 (22HR)\n");
msg->status = PHY_INVALID_PARAMETER;
SendCfgUp (msg);
return;
}
NTRXSetupTrxMode (bw, sd, br);
switch (bw)
{
case NA_80MHz: printf ("New Mode 80 Mhz "); break;
case NA_22MHz: printf ("New Mode 22 Mhz "); break;
default: printf ("Unknown mode ??? ");
}
switch (sd)
{
case NA_500ns: printf ("500 ns, "); break;
case NA_1us: printf ("1 us, "); break;
case NA_2us: printf ("2 us, "); break;
case NA_4us: printf ("4 us, "); break;
default: break;
}
switch (br)
{
case NA_125k_S: printf ("125 kSym\n"); break;
case NA_250k_S: printf ("250 kSym\n"); break;
case NA_500k_S: printf ("500 kSym\n"); break;
case NA_1M_S: printf ("1 MSym\n"); break;
case NA_2M_S: printf ("2 MSym\n"); break;
default: break;
}
break;
case PHY_TX_POWER: if (msg->value > 63)
{
msg->status = PHY_INVALID_PARAMETER;
}
else
{
phyPIB.txPower = ((MyByte8T)(msg->value) & 0x3f);
ntrxShadowReg[NA_TxOutputPower0_O] &= ~(0x3f << NA_TxOutputPower0_LSB);
ntrxShadowReg[NA_TxOutputPower0_O] |= (phyPIB.txPower << NA_TxOutputPower0_LSB);
if (phyPIB.txPower != 0x3f)
{ /* This way no table for the transmission output power is necessary */
ntrxShadowReg[NA_TxOutputPower0_O] &= ~(1 << NA_TxOutputPower0_LSB);
}
NTRXSPIWriteByte (NA_TxOutputPower0_O, ntrxShadowReg[NA_TxOutputPower0_O]);
ntrxShadowReg[NA_TxOutputPower1_O] &= ~(0x3f << NA_TxOutputPower1_LSB);
ntrxShadowReg[NA_TxOutputPower1_O] |= (phyPIB.txPower << NA_TxOutputPower1_LSB);
if (phyPIB.txPower != 0x3f)
{ /* This way no table for the transmission output power is necessary */
ntrxShadowReg[NA_TxOutputPower1_O] &= ~(1 << NA_TxOutputPower1_LSB);
}
NTRXSPIWriteByte (NA_TxOutputPower1_O, ntrxShadowReg[NA_TxOutputPower1_O]);
}
break;
case PHY_ARQ: phyPIB.rxOn = FALSE;
NTRXSPIWriteByte (NA_RxCmdStop_O, ntrxShadowReg[NA_RxCmdStop_O] | (1 << NA_RxCmdStop_B));
if( msg->value == 0 )
{
ntrxShadowReg[NA_TxArq_O] &= ~(1 << NA_TxArq_B);
ntrxShadowReg[NA_RxArqMode_O] &= ~((0x03 << NA_RxArqMode_LSB)
| (1 << NA_RxCrc2Mode_B));
}
else
{
ntrxShadowReg[NA_TxArq_O] |= (1 << NA_TxArq_B);
ntrxShadowReg[NA_RxArqMode_O] |= ((NA_RxArqModeCrc2_VC_C << NA_RxArqMode_LSB)
| (NA_RxCrc2ModeTrigOn_BC_C << NA_RxCrc2Mode_B));
}
NTRXSPIWriteByte (NA_TxArq_O, ntrxShadowReg[NA_TxArq_O]);
NTRXSPIWriteByte (NA_RxArqMode_O, ntrxShadowReg[NA_RxArqMode_O]);
if (phyPIB.rxState == PHY_RX_ON)
{
phyPIB.rxOn = TRUE;
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B)
| (0x03 << NA_RxBufferCmd_LSB));
}
break;
case PHY_ARQ_MAX: if (msg->value > 14)
{
msg->status = PHY_INVALID_PARAMETER;
}
else
{
NTRXSPIWriteByte (NA_RxCmdStop_O, ntrxShadowReg[NA_RxCmdStop_O] | (1 << NA_RxCmdStop_B));
phyPIB.arqMax = (MyByte8T)(msg->value);
if (phyPIB.arqMax == 0)
{
ntrxShadowReg[NA_TxArqMax_O] &= ~(0x0f << NA_TxArqMax_LSB);
}
else
{
ntrxShadowReg[NA_TxArqMax_O] &= ~(0x0f << NA_TxArqMax_LSB);
ntrxShadowReg[NA_TxArqMax_O] |= ((MyByte8T)(msg->value << NA_TxArqMax_LSB));
}
NTRXSPIWriteByte (NA_TxArqMax_O, ntrxShadowReg[NA_TxArqMax_O]);
if (phyPIB.rxState == PHY_RX_ON)
{
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B)
| (0x03 << NA_RxBufferCmd_LSB));
}
}
break;
case PHY_FEC: NTRXSPIWriteByte (NA_RxCmdStop_O, ntrxShadowReg[NA_RxCmdStop_O] | (1 << NA_RxCmdStop_B));
if (msg->value == TRUE)
{
ntrxShadowReg[NA_UseFec_O] |= (1 << NA_UseFec_B);
}
else
{
ntrxShadowReg[NA_UseFec_O] &= ~(1 << NA_UseFec_B);
}
NTRXSPIWriteByte (NA_UseFec_O, ntrxShadowReg[NA_UseFec_O]);
phyPIB.fec = msg->value;
modeSet.fec = msg->value;
if (phyPIB.rxState == PHY_RX_ON)
{
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B)
| (0x03 << NA_RxBufferCmd_LSB));
}
break;
case PHY_MAC_ADDRESS1: NTRXSPIWriteByte (NA_RxCmdStop_O, ntrxShadowReg[NA_RxCmdStop_O] | (1 << NA_RxCmdStop_B));
memcpy (phyPIB.macAddr0, msg->data, 6);
NTRXSetIndexReg (0);
NTRXSPIWrite (NA_RamStaAddr0_O, msg->data , 6);
if (phyPIB.rxState == PHY_RX_ON)
{
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B)
| (0x03 << NA_RxBufferCmd_LSB));
}
break;
case PHY_MAC_ADDRESS2: NTRXSPIWriteByte (NA_RxCmdStop_O, ntrxShadowReg[NA_RxCmdStop_O] | (1 << NA_RxCmdStop_B));
memcpy (phyPIB.macAddr1, msg->data, 6);
NTRXSetIndexReg (0);
NTRXSPIWrite (NA_RamStaAddr1_O, msg->data, 6);
if (phyPIB.rxState == PHY_RX_ON)
{
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B)
| (0x03 << NA_RxBufferCmd_LSB));
}
break;
case PHY_TX_ADDR_SELECT: NTRXSPIWriteByte (NA_RxCmdStop_O, ntrxShadowReg[NA_RxCmdStop_O] | (1 << NA_RxCmdStop_B));
phyPIB.txAddrSel = (MyByte8T)(msg->value);
if (msg->value == 0)
{
ntrxShadowReg[NA_TxAddrSlct_O] &= ~(1 << NA_TxAddrSlct_B);
}
else
{
ntrxShadowReg[NA_TxAddrSlct_O] |= (1 << NA_TxAddrSlct_B);
}
NTRXSPIWriteByte (NA_TxAddrSlct_O, ntrxShadowReg[NA_TxAddrSlct_O]);
if (phyPIB.rxState == PHY_RX_ON)
{
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B)
| (0x03 << NA_RxBufferCmd_LSB));
}
break;
case PHY_ADDR_MATCHING: NTRXSPIWriteByte (NA_RxCmdStop_O, ntrxShadowReg[NA_RxCmdStop_O] | (1 << NA_RxCmdStop_B));
phyPIB.addrMatch = (MyByte8T)(msg->value);
if (msg->value == 0)
{
/* promiscuous mode */
ntrxShadowReg[NA_RxAddrMode_O] &= ~(1 << NA_RxAddrMode_B);
}
else
{
ntrxShadowReg[NA_RxAddrMode_O] |= (1 << NA_RxAddrMode_B);
}
NTRXSPIWriteByte (NA_RxAddrMode_O, ntrxShadowReg[NA_RxAddrMode_O]);
if (phyPIB.rxState == PHY_RX_ON)
{
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B)
| (0x03 << NA_RxBufferCmd_LSB));
}
break;
case PHY_RECALIBRATION: /* delay time for recalibration */
phyPIB.recalInterval = msg->value * 1000;
break;
case PHY_PWR_DOWN_MODE: if (msg->value > 1)
{
msg->status = PHY_INVALID_PARAMETER;
}
else
{
trxPollMode = (phyPIB.recalInterval == 0) ? FALSE : TRUE;
phyPIB.pwrDownMode = msg->value;
NTRXResetSettings ();
NTRXPowerdownMode (msg->value, *(MyDword32T*)(msg->data));
}
break;
case PHY_FRAME_TYPE: phyPIB.frameType = ( msg->value & 0x07 );
ntrxShadowReg[NA_RxDataEn_O] = ~( 0x07 );
ntrxShadowReg[NA_RxDataEn_O] |= phyPIB.frameType;
NTRXSPIWriteByte (NA_RxDataEn_O , ntrxShadowReg[NA_RxDataEn_O]);
break;
case PHY_TESTMODE: if (msg->value > 2)
{
msg->status = PHY_INVALID_PARAMETER;
}
else
{
switch (msg->value)
{
case 1: TestmodeOff ();
NTRXSetTestChirpMode (TRUE);
/* this blocks the transmission path of the PDSap */
txSendMsg = &upMsg;
break;
case 2: TestmodeOff ();
NTRXSetTestCarrierMode (TRUE);
/* this blocks the transmission path of the PDSap */
txSendMsg = &upMsg;
break;
default:/* this enables the transmission path of the PDSap */
TestmodeOff ();
txSendMsg = NULL;
}
phyPIB.testmode = msg->value;
}
break;
case PHY_RX_CMD:
switch (msg->value)
{
case PHY_TRX_OFF:
case PHY_RX_ON:
phyPIB.rxState = msg->value;
/*stop the receiver and clear the buffers */
NTRXSPIWriteByte (NA_RxCmdStop_O, ntrxShadowReg[NA_RxCmdStop_O]
| (1 << NA_RxCmdStop_B)
| (0x03 << NA_RxBufferCmd_LSB));
/* clear interrupts */
NTRXSPIWriteByte (NA_RxIntsReset_O, 0x7F);
rxIrq = 0;
# ifdef CONFIG_NTRX_SNIFFER
upMsg.count=0;
# endif
if (msg->value == PHY_RX_ON)
{
/*start the receiver*/
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B));
}
break;
default: msg->status = PHY_INVALID_PARAMETER;
break;
}
break;
case PHY_RX_STATE: switch (msg->value)
{
case PHY_RX_ON:
case PHY_TRX_OFF: phyPIB.rxState = msg->value;
break;
default: msg->status = PHY_INVALID_PARAMETER;
break;
}
break;
case PHY_SYNCWORD: NTRXSPIWriteByte (NA_RxCmdStop_O, ntrxShadowReg[NA_RxCmdStop_O] | (1 << NA_RxCmdStop_B));
memcpy (phyPIB.syncword, (MyByte8T *)(msg->value), 8);
NTRXSetSyncWord(phyPIB.syncword);
if (phyPIB.rxState == PHY_RX_ON)
{
NTRXSPIWriteByte (NA_RxCmdStart_O, ntrxShadowReg[NA_RxCmdStart_O]
| (1 << NA_RxCmdStart_B)
| (0x03 << NA_RxBufferCmd_LSB));
}
break;
default: msg->status = PHY_UNSUPPORTED_ATTRIBUTE;
break;
}
SendCfgUp (msg);
break;
default: break;
}
/* ieee config stuff */
}
void PDSap (MyMsgT *msg)
/****************************************************************************/
{
MyByte8T txLen[2];
static MyAddressT cacheAddr;
/*
* check the message length. If the message length is bigger than
* the allowed buffer size the packet will be rejected.
*/
if (msg->len > PHY_PACKET_SIZE)
{
msg->prim = PD_DATA_CONFIRM;
msg->status = PHY_BUSY_TX;
SendMsgUp (msg);
return;
}
switch(msg->prim)
{
case PD_DATA_REQUEST :
/* transmitter still busy */
if (txSendMsg != NULL)
{
msg->prim = PD_DATA_CONFIRM;
msg->status = PHY_BUSY_TX;
SendMsgUp (msg);
return;
}
/*
* there is no break here !!!
* This is intentional and not a mistake.
*/
case PD_RANGING_ANSWER1_EXECUTE :
case PD_RANGING_ANSWER2_EXECUTE :
case PD_RANGING_REQUEST_EXECUTE :
case PD_RANGING_FAST_REQUEST_EXECUTE :
case PD_RANGING_FAST_ANSWER1_EXECUTE :
# ifdef CONFIG_NTRX_AUTO_RECALIB
if (phyPIB.recalInterval != 0)
{
if( tiRecal < hwclock() )
{
/* INFO: If the TRX sends a packet, calibration failes!
* In this case rcwd is not reset, but tiRecal is.
*/
/* normal operation mode */
if (phyPIB.testmode == 0)
{
if (NTRXAllCalibration ())
{
tiRecal = hwclock() + phyPIB.recalInterval;
rcwd = 0;
TRIGGER_LED_CAL();
}
}
}
}
# endif /* CONFIG_NTRX_AUTO_RECALIB */
/* check which buffer is free to transmit data */
if (buffSwapped ==TRUE)
{
/* write user data to transmit buffer in ntrx chip */
NTRXSetIndexReg (2);
NTRXSPIWrite ((MyByte8T)(NA_RamTxBuffer_O & 0xff), msg->data, (MyByte8T)(msg->len & 0xff));
}else
{
/* write user data to transmit buffer in ntrx chip */
NTRXSetIndexReg (3);
NTRXSPIWrite ((MyByte8T)(NA_RamTxBuffer_O & 0xff), msg->data, (MyByte8T)(msg->len & 0xff));
}
NTRXSetIndexReg (0);
/* copy the destination address to temp buffer */
if (memcmp (cacheAddr, msg->addr, 6) != 0)
{
memcpy (cacheAddr, msg->addr, 6);
NTRXSPIWrite (NA_RamTxDstAddr_O, cacheAddr, 6);
}
/* merge the three bits into the temp buffer */
txLen[0] = msg->len;
// txLen[1] = (len & 0x1F00) >> 8;
txLen[1] = (lState & 0x01) ? 0x20 : 0;
txLen[1] |= (lState & 0x02) ? 0x40 : 0;
txLen[1] |= (lState & 0x04) ? 0x80 : 0;
NTRXSPIWrite (NA_RamTxLength_O, txLen, 2);
ntrxState = TxSEND;
/* mark buffers as valid and start transmission */
NTRXSPIWriteByte (NA_TxBufferCmd_O, (1 << NA_TxCmdStart_B) | (0x03 << NA_TxBufferCmd_LSB));
TRIGGER_LED_TX();
txSendMsg = msg;
break;
case PD_RANGING_REQUEST :
case PD_RANGING_FAST_REQUEST :
/* transmitter still busy */
rangingPIB.distance = -1.0;
rangingPIB.error = STAT_NO_ERROR;
if (txSendMsg != NULL)
{
msg->prim = PD_RANGING_CONFIRM;
msg->status = PHY_BUSY_TX;
memcpy(msg->data, (MyByte8T*) &rangingPIB, sizeof(RangingPIB));
msg->len = sizeof(RangingPIB);
SendMsgUp (msg);
return;
}
if (lState != RANGING_READY)
{
txSendMsg = NULL;
msg->prim = PD_RANGING_CONFIRM;
msg->status = PHY_BUSY;
memcpy(msg->data, (MyByte8T*) &rangingPIB, sizeof(RangingPIB));
msg->len = sizeof(RangingPIB);
SendMsgUp (msg);
return;
}
memcpy(rDest, msg->addr, 6);
if (msg->prim == PD_RANGING_REQUEST)
{
lState = RANGING_START;
RangingMode(RANGING_START, msg->addr);
}
else if (msg->prim == PD_RANGING_FAST_REQUEST)
{
lState = RANGING_FAST_START;
RangingMode(RANGING_FAST_START, msg->addr);
}
break;
default:
break;
}
}
/**
* NTRXTxData:
*
* @payload: -input- data to be transmitted to destination
* @len: -input- length of payload to be written into transmit buffer
*
* NTRXTxData() writes len bytes of payload to transmit buffer of nanoNET TRX chip
*
* Returns: none
*
*/
void NTRXTxData (MyPtrT payload, MyWord16T len)
{
NTRXSetIndexReg (3);
NTRXWriteSPI (NA_RamTxBuffer_O & 0xff, (MyByte8T *)payload, (MyByte8T)(len & 0xff));
}
