void intSerialIOInit(void) {
/* On reset (i.e., before calling mcgInit), the processor clocking
* starts in FEI (FLL Engaged Internal) mode. In FEI mode and with
* default settings (DRST_DRS = 00, DMX32 = 0), the MCGFLLCLK, the
* MCGOUTCLK (MCG (Multipurpose Clock Generator) clock), and the Bus
* (peripheral) clock are all set to 640 * IRC. IRC is the Internal
* Reference Clock which runs at 32 KHz. [See K70 Sub-Family
* Reference Manual, Rev. 2, Section 25.4.1.1, Table 25-22 on
* page 657 and MCG Control 4 Register (MCG_C4) Section 25.3.4 on
* page 641] */
/* After calling mcgInit, MCGOUTCLK is set to 120 MHz and the Bus
* (peripheral) clock is set to 60 MHz.*/
/* Table 5-2 on page 221 indicates that the clock used by UART0 and
* UART1 is the System clock (i.e., MCGOUTCLK) and that the clock
* used by UART2-5 is the Bus clock. */
/* This function assumes that mcgInit has been called and
* that the uart device has been initialized */
/* Enable the receiver full interrupt for UART2 using the UART2_C2 register
* (UART Control Register 2) (See 57.3.4 on page 1909 of the K70 Sub-Family Reference
* Manual, Rev. 2, Dec 2011) */
UART2_C2 |= UART_C2_RIE_MASK;
/* Enable interrupts from UART2 status sources and set its interrupt priority */
NVICEnableIRQ(UART2_STATUS_IRQ_NUMBER, UART2_STATUS_INTERRUPT_PRIORITY);
}
/**
* initialize PDB 0 hardware
*
* count is the number of 1/16384 second time periods
* continuous is a boolean value which determines if the counter will work in one-shot or
* continuous mode
*/
void PDB0Init(uint16_t count, int continuous) {
/* Enable the clock for PDB0 (PDBTimer 0) using the SIM_SCGC6 register
* (System Clock Gating Control Register 6) (See 12.2.14 on page 344 of
* the K70 Sub-Family Reference Manual, Rev. 2, Dec 2011) */
SIM_SCGC6 |= SIM_SCGC6_PDB_MASK;
/* Disable PDBTimer 0 and clear any pending PDB Interrupt Flag using
* the PDB0_SC register (Status and Control register for PDBTimer 0)
* (See 43.3.1 on page 1199 of the K70 Sub-Family Reference Manual,
* Rev. 2, Dec 2011) */
PDB0_SC = 0;
/* With the MCGOUTCLK = FLL_Factor*IRC (which is 32768*640), and with the
* peripheral clock divider set to 10, we end up with a peripheral clock of
* 2,097,152 Hz. Setting the prescaler to divide by 128 yields a counter
* frequency of 16384 Hz */
/* Set the Clock 2 (peripheral clock) output divider value to 10 using
* the SIM_CLKDIV1 register (System Clock Divider Register 1)
* (See 12.2.16 on page 347 of the K70 Sub-Family Reference Manual,
* Rev. 2, Dec 2011) */
SIM_CLKDIV1 = (SIM_CLKDIV1 & ~SIM_CLKDIV1_OUTDIV2_MASK) |
SIM_CLKDIV1_OUTDIV2(SIM_CLKDIV1_OUTDIV_DIVIDE_BY_10);
/* Load timer count (16-bit value) into the modulo register */
PDB0_MOD = count;
/* Load timer count (16-bit value) into the interrupt delay register */
PDB0_IDLY = count;
/* Prescaler to divide by 128, Software trigger is selected,
* PDB interrupt enabled, Multiplication factor is 1,
* Continuous mode, Load OK, Enable the PDB */
PDB0_SC = PDB_SC_PRESCALER(PDB_SC_PRESCALER_DIVIDE_BY_128) |
PDB_SC_TRGSEL(PDB_SC_TRGSEL_SOFTWARE_TRIGGER) |
PDB_SC_PDBIE_MASK |
PDB_SC_MULT(PDB_SC_MULT_BY_1) |
(continuous ? PDB_SC_CONT_MASK : 0) |
PDB_SC_LDOK_MASK | PDB_SC_PDBEN_MASK;
/* Set the counter value (16-bit value) in the counter register */
PDB0_CNT = 0;
/* Enable interrupts from PDB0 and set its interrupt priority */
NVICEnableIRQ(PDB0_IRQ_NUMBER, PDB0_INTERRUPT_PRIORITY);
}
