/* ===================================================================*/
LDD_TDeviceData* CI2C1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate HAL device structure */
CI2C1_TDeviceData *DeviceDataPrv;
/* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
/* Allocate interrupt vector */
/* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */
/* Note: Exception handler for interrupt is not saved, because it is not modified */
DeviceDataPrv->SavedISRSettings.isrData = _int_get_isr_data(LDD_ivIndex_INT_I2C0);
DeviceDataPrv->SavedISRSettings.isrFunction = _int_install_isr(LDD_ivIndex_INT_I2C0, CI2C1_Interrupt, DeviceDataPrv);
DeviceDataPrv->SerFlag = 0x00U; /* Reset all flags */
DeviceDataPrv->SendStop = LDD_I2C_SEND_STOP; /* Set variable for sending stop condition (for master mode) */
DeviceDataPrv->InpLenM = 0x00U; /* Set zero counter of data of reception */
DeviceDataPrv->OutLenM = 0x00U; /* Set zero counter of data of transmission */
/* SIM_SCGC4: I2C0=1 */
SIM_SCGC4 |= SIM_SCGC4_I2C0_MASK;
/* I2C0_C1: IICEN=0,IICIE=0,MST=0,TX=0,TXAK=0,RSTA=0,WUEN=0,DMAEN=0 */
I2C0_C1 = 0x00U; /* Clear control register */
/* I2C0_S: TCF=0,IAAS=0,BUSY=0,ARBL=0,RAM=0,SRW=0,IICIF=1,RXAK=0 */
I2C0_S = I2C_S_IICIF_MASK; /* Clear interrupt flag */
/* PORTB_PCR1: ISF=0,MUX=2 */
PORTB_PCR1 = (uint32_t)((PORTB_PCR1 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
PORT_PDD_SetPinOpenDrain(PORTB_BASE_PTR, 0x01u, PORT_PDD_OPEN_DRAIN_ENABLE); /* Set SDA pin as open drain */
/* PORTB_PCR0: ISF=0,MUX=2 */
PORTB_PCR0 = (uint32_t)((PORTB_PCR0 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
PORT_PDD_SetPinOpenDrain(PORTB_BASE_PTR, 0x00u, PORT_PDD_OPEN_DRAIN_ENABLE); /* Set SCL pin as open drain */
/* NVICIP24: PRI24=0x80 */
NVICIP24 = NVIC_IP_PRI24(0x80);
/* NVICISER0: SETENA|=0x01000000 */
NVICISER0 |= NVIC_ISER_SETENA(0x01000000);
/* I2C0_C2: GCAEN=0,ADEXT=0,HDRS=0,SBRC=0,RMEN=0,AD=0 */
I2C0_C2 = I2C_C2_AD(0x00);
/* I2C0_FLT: ??=0,??=0,??=0,FLT=0 */
I2C0_FLT = I2C_FLT_FLT(0x00); /* Set glitch filter register */
/* I2C0_SMB: FACK=0,ALERTEN=0,SIICAEN=0,TCKSEL=0,SLTF=1,SHTF1=0,SHTF2=0,SHTF2IE=0 */
I2C0_SMB = I2C_SMB_SLTF_MASK;
/* I2C0_F: MULT=1,ICR=0x17 */
I2C0_F = (I2C_F_MULT(0x01) | I2C_F_ICR(0x17)); /* Set prescaler bits */
I2C_PDD_EnableDevice(I2C0_BASE_PTR, PDD_ENABLE); /* Enable device */
I2C_PDD_EnableInterrupt(I2C0_BASE_PTR); /* Enable interrupt */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_CI2C1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
/* ===================================================================*/
LDD_TDeviceData* IntI2cLdd1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate HAL device structure */
IntI2cLdd1_TDeviceData *DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
/* Allocate interrupt vector */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_I2C0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
DeviceDataPrv->SerFlag = ADDR_7; /* Reset all flags start with 7-bit address mode */
DeviceDataPrv->SlaveAddr = 0x3AU; /* Set variable for slave address */
DeviceDataPrv->SendStop = LDD_I2C_SEND_STOP; /* Set variable for sending stop condition (for master mode) */
DeviceDataPrv->InpByteMNum = 0x00U; /* Set zero number of input bufer's content */
DeviceDataPrv->InpLenM = 0x00U; /* Set zero counter of data of reception */
DeviceDataPrv->OutByteMNum = 0x00U; /* Set zero length of output bufer's content */
DeviceDataPrv->OutLenM = 0x00U; /* Set zero counter of data of transmission */
/* SIM_SCGC4: I2C0=1 */
SIM_SCGC4 |= SIM_SCGC4_I2C0_MASK;
/* I2C0_C1: IICEN=0,IICIE=0,MST=0,TX=0,TXAK=0,RSTA=0,WUEN=0,DMAEN=0 */
I2C0_C1 = 0x00U; /* Clear control register */
/* I2C0_FLT: SHEN=0,STOPF=1,SSIE=0,STARTF=1,FLT=0 */
I2C0_FLT = (I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_FLT(0x00)); /* Clear bus status interrupt flags */
/* I2C0_S: TCF=0,IAAS=0,BUSY=0,ARBL=0,RAM=0,SRW=0,IICIF=1,RXAK=0 */
I2C0_S = I2C_S_IICIF_MASK; /* Clear interrupt flag */
/* SIM_SCGC5: PORTE=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;
/* PORTE_PCR25: ISF=0,MUX=5 */
PORTE_PCR25 = (uint32_t)((PORTE_PCR25 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x02)
)) | (uint32_t)(
PORT_PCR_MUX(0x05)
));
/* PORTE_PCR24: ISF=0,MUX=5 */
PORTE_PCR24 = (uint32_t)((PORTE_PCR24 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x02)
)) | (uint32_t)(
PORT_PCR_MUX(0x05)
));
/* NVICIP24: PRI24=0x70 */
NVICIP24 = NVIC_IP_PRI24(0x70);
/* NVICISER0: SETENA|=0x01000000 */
NVICISER0 |= NVIC_ISER_SETENA(0x01000000);
/* I2C0_C2: GCAEN=0,ADEXT=0,HDRS=0,SBRC=0,RMEN=0,AD=0 */
I2C0_C2 = I2C_C2_AD(0x00);
/* I2C0_FLT: SHEN=0,STOPF=0,SSIE=0,STARTF=0,FLT=0 */
I2C0_FLT = I2C_FLT_FLT(0x00); /* Set glitch filter register */
/* I2C0_SMB: FACK=0,ALERTEN=0,SIICAEN=0,TCKSEL=0,SLTF=1,SHTF1=0,SHTF2=0,SHTF2IE=0 */
I2C0_SMB = I2C_SMB_SLTF_MASK;
/* I2C0_F: MULT=0,ICR=0x27 */
I2C0_F = (I2C_F_MULT(0x00) | I2C_F_ICR(0x27)); /* Set prescaler bits */
I2C_PDD_EnableDevice(I2C0_BASE_PTR, PDD_ENABLE); /* Enable device */
I2C_PDD_EnableInterrupt(I2C0_BASE_PTR); /* Enable interrupt */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_IntI2cLdd1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
