}, &nv40_perfctr_func }, { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, {} }; struct nvkm_oclass * gt215_pm_oclass = &(struct nv40_pm_oclass) { .base.handle = NV_ENGINE(PM, 0xa3), .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_pm_ctor, .dtor = _nvkm_pm_dtor, .init = _nvkm_pm_init, .fini = _nvkm_pm_fini, }, .doms = gt215_pm, }.base;
static int nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { struct nv04_sw_priv *priv; int ret; ret = nvkm_sw_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_engine(priv)->cclass = &nv04_sw_cclass; nv_engine(priv)->sclass = nv04_sw_sclass; nv_subdev(priv)->intr = nv04_sw_intr; return 0; } struct nvkm_oclass * nv04_sw_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(SW, 0x04), .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_sw_ctor, .dtor = _nvkm_sw_dtor, .init = _nvkm_sw_init, .fini = _nvkm_sw_fini, }, };
priv->sor.power = nv50_sor_power; priv->sor.hdmi = nv84_hdmi_ctrl; priv->pior.power = nv50_pior_power; return 0; } struct nouveau_oclass * nv94_disp_outp_sclass[] = { &nv50_pior_dp_impl.base.base, &nv94_sor_dp_impl.base.base, NULL }; struct nouveau_oclass * nv94_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x88), .base.base.ofuncs = &(struct nouveau_ofuncs) { .ctor = nv94_disp_ctor, .dtor = _nouveau_disp_dtor, .init = _nouveau_disp_init, .fini = _nouveau_disp_fini, }, .base.vblank = &nv50_disp_vblank_func, .base.outp = nv94_disp_outp_sclass, .mthd.core = &nv94_disp_mast_mthd_chan, .mthd.base = &nv84_disp_sync_mthd_chan, .mthd.ovly = &nv84_disp_ovly_mthd_chan, .mthd.prev = 0x000004, .head.scanoutpos = nv50_disp_base_scanoutpos, }.base.base;
* the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs */ #include "gk104.h" struct nvkm_oclass * gk208_fifo_oclass = &(struct gk104_fifo_impl) { .base.handle = NV_ENGINE(FIFO, 0x08), .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gk104_fifo_ctor, .dtor = gk104_fifo_dtor, .init = gk104_fifo_init, .fini = _nvkm_fifo_fini, }, .channels = 1024, }.base;
.data.data = gk110_grhub_data, .data.size = sizeof(gk110_grhub_data), }; #include "fuc/gpcgk110.fuc3.h" struct gf100_gr_ucode gk110_gr_gpccs_ucode = { .code.data = gk110_grgpc_code, .code.size = sizeof(gk110_grgpc_code), .data.data = gk110_grgpc_data, .data.size = sizeof(gk110_grgpc_data), }; struct nvkm_oclass * gk110_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xf0), .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gk104_gr_ctor, .dtor = gf100_gr_dtor, .init = gk104_gr_init, .fini = _nvkm_gr_fini, }, .cclass = &gk110_grctx_oclass, .sclass = gk110_gr_sclass, .mmio = gk110_gr_pack_mmio, .fecs.ucode = &gk110_gr_fecs_ucode, .gpccs.ucode = &gk110_gr_gpccs_ucode, .ppc_nr = 2, } .base;
} static int nv84_crypt_init(struct nouveau_object *object) { struct nv84_crypt_priv *priv = (void *)object; int ret; nv_warn(object, "[%s]\n", __PRETTY_FUNCTION__); ret = nouveau_engine_init(&priv->base); if (ret) return ret; nv_wr32(priv, 0x102130, 0xffffffff); nv_wr32(priv, 0x102140, 0xffffffbf); nv_wr32(priv, 0x10200c, 0x00000010); return 0; } struct nouveau_oclass nv84_crypt_oclass = { .handle = NV_ENGINE(CRYPT, 0x84), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv84_crypt_ctor, .dtor = _nouveau_engine_dtor, .init = nv84_crypt_init, .fini = _nouveau_engine_fini, }, };
int ret; ret = nouveau_graph_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; ret = nouveau_gpuobj_new(parent, NULL, 32 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; nv_subdev(priv)->intr = nv20_graph_intr; nv_engine(priv)->cclass = &nv25_graph_cclass; nv_engine(priv)->sclass = nv25_graph_sclass; nv_engine(priv)->tile_prog = nv20_graph_tile_prog; return 0; } struct nouveau_oclass nv25_graph_oclass = { .handle = NV_ENGINE(GR, 0x25), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv25_graph_ctor, .dtor = nv20_graph_dtor, .init = nv20_graph_init, .fini = _nouveau_graph_fini, }, };
* The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs <*****@*****.**> */ #include "gf100.h" #include "ctxgf100.h" struct nvkm_oclass * gm206_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0x26), .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gf100_gr_ctor, .dtor = gf100_gr_dtor, .init = gm204_gr_init, .fini = _nvkm_gr_fini, }, .cclass = &gm206_grctx_oclass, .sclass = gm204_gr_sclass, .mmio = gm204_gr_pack_mmio, .ppc_nr = 2, }.base;
int ret; ret = nvkm_gr_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; nv_subdev(priv)->intr = nv20_gr_intr; nv_engine(priv)->cclass = &nv35_gr_cclass; nv_engine(priv)->sclass = nv35_gr_sclass; nv_engine(priv)->tile_prog = nv20_gr_tile_prog; return 0; } struct nvkm_oclass nv35_gr_oclass = { .handle = NV_ENGINE(GR, 0x35), .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv35_gr_ctor, .dtor = nv20_gr_dtor, .init = nv30_gr_init, .fini = _nvkm_gr_fini, }, };
static int nv98_ppp_init(struct nouveau_object *object) { struct nv98_ppp_priv *priv = (void *)object; int ret; ret = nouveau_ppp_init(&priv->base); if (ret) return ret; return 0; } static int nv98_ppp_fini(struct nouveau_object *object, bool suspend) { struct nv98_ppp_priv *priv = (void *)object; return nouveau_ppp_fini(&priv->base, suspend); } struct nouveau_oclass nv98_ppp_oclass = { .handle = NV_ENGINE(PPP, 0x98), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv98_ppp_ctor, .dtor = nv98_ppp_dtor, .init = nv98_ppp_init, .fini = nv98_ppp_fini, }, };
for (i = 0; i < pfb->tile.regions; i++) engine->tile_prog(engine, i); nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); nv_wr32(priv, 0x0040075c , 0x00000001); /* begin RAM config */ /* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */ nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); if (nv_device(priv)->chipset != 0x34) { nv_wr32(priv, 0x400750, 0x00EA0000); nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200)); nv_wr32(priv, 0x400750, 0x00EA0004); nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204)); } return 0; } struct nouveau_oclass nv30_graph_oclass = { .handle = NV_ENGINE(GR, 0x30), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv30_graph_ctor, .dtor = nv20_graph_dtor, .init = nv30_graph_init, .fini = _nouveau_graph_fini, }, };
int ret; ret = nouveau_graph_create(parent, engine, oclass, true, &priv); *pobject = nv_object(priv); if (ret) return ret; ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); if (ret) return ret; nv_subdev(priv)->unit = 0x00001000; nv_subdev(priv)->intr = nv20_graph_intr; nv_engine(priv)->cclass = &nv2a_graph_cclass; nv_engine(priv)->sclass = nv25_graph_sclass; nv_engine(priv)->tile_prog = nv20_graph_tile_prog; return 0; } struct nouveau_oclass nv2a_graph_oclass = { .handle = NV_ENGINE(GR, 0x2a), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv2a_graph_ctor, .dtor = nv20_graph_dtor, .init = nv20_graph_init, .fini = _nouveau_graph_fini, }, };
struct nouveau_object **pobject) { struct nvc0_perfmon_priv *priv; int ret; ret = nouveau_perfmon_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, nve0_perfmon_pwr); if (ret) return ret; nv_engine(priv)->cclass = &nouveau_perfmon_cclass; nv_engine(priv)->sclass = nouveau_perfmon_sclass; return 0; } struct nouveau_oclass nvf0_perfmon_oclass = { .handle = NV_ENGINE(PERFMON, 0xf0), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nvf0_perfmon_ctor, .dtor = _nouveau_perfmon_dtor, .init = _nouveau_perfmon_init, .fini = nvc0_perfmon_fini, }, };
INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); priv->sclass = nvf0_disp_sclass; priv->head.nr = heads; priv->dac.nr = 3; priv->sor.nr = 4; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; priv->sor.hda_eld = nvd0_hda_eld; priv->sor.hdmi = nvd0_hdmi_ctrl; return 0; } struct nouveau_oclass * nvf0_disp_oclass = &(struct nv50_disp_impl) { .base.base.handle = NV_ENGINE(DISP, 0x92), .base.base.ofuncs = &(struct nouveau_ofuncs) { .ctor = nvf0_disp_ctor, .dtor = _nouveau_disp_dtor, .init = _nouveau_disp_init, .fini = _nouveau_disp_fini, }, .base.vblank = &nvd0_disp_vblank_func, .base.outp = nvd0_disp_outp_sclass, .mthd.core = &nve0_disp_mast_mthd_chan, .mthd.base = &nvd0_disp_sync_mthd_chan, .mthd.ovly = &nve0_disp_ovly_mthd_chan, .mthd.prev = -0x020000, .head.scanoutpos = nvd0_disp_base_scanoutpos, }.base.base;
0x1000, 0x200, gf100_pm_gpc); if (ret) return ret; /* PART */ mask = (1 << nv_rd32(priv, 0x022438)) - 1; mask &= ~nv_rd32(priv, 0x022548); mask &= ~nv_rd32(priv, 0x0225c8); ret = nvkm_perfdom_new(&priv->base, "part", mask, 0x1a0000, 0x1000, 0x200, gf100_pm_part); if (ret) return ret; nv_engine(priv)->cclass = &nvkm_pm_cclass; nv_engine(priv)->sclass = nvkm_pm_sclass; priv->base.last = 7; return 0; } struct nvkm_oclass gf100_pm_oclass = { .handle = NV_ENGINE(PM, 0xc0), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gf100_pm_ctor, .dtor = _nvkm_pm_dtor, .init = _nvkm_pm_init, .fini = gf100_pm_fini, }, };
{ 0x040, (const struct nouveau_specsig[]) { {} }, &nv40_perfctr_func }, { 0x100, (const struct nouveau_specsig[]) { { 0xc8, "gr_idle" }, {} }, &nv40_perfctr_func }, { 0x100, (const struct nouveau_specsig[]) { {} }, &nv40_perfctr_func }, { 0x020, (const struct nouveau_specsig[]) { {} }, &nv40_perfctr_func }, { 0x040, (const struct nouveau_specsig[]) { {} }, &nv40_perfctr_func }, {} }; struct nouveau_oclass * nv50_perfmon_oclass = &(struct nv40_perfmon_oclass) { .base.handle = NV_ENGINE(PERFMON, 0x50), .base.ofuncs = &(struct nouveau_ofuncs) { .ctor = nv40_perfmon_ctor, .dtor = _nouveau_perfmon_dtor, .init = _nouveau_perfmon_init, .fini = _nouveau_perfmon_fini, }, .doms = nv50_perfmon, }.base;
nvc0_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { struct nvc0_software_priv *priv; int ret; nv_warn(parent, "[%s]\n", __PRETTY_FUNCTION__); ret = nouveau_software_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_engine(priv)->cclass = &nvc0_software_cclass; nv_engine(priv)->sclass = nvc0_software_sclass; nv_subdev(priv)->intr = nv04_software_intr; return 0; } struct nouveau_oclass nvc0_software_oclass = { .handle = NV_ENGINE(SW, 0xc0), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nvc0_software_ctor, .dtor = _nouveau_software_dtor, .init = _nouveau_software_init, .fini = _nouveau_software_fini, }, };
priv->sclass = nve0_disp_sclass; priv->head.nr = nv_rd32(priv, 0x022448); priv->dac.nr = 3; priv->sor.nr = 4; priv->dac.power = nv50_dac_power; priv->dac.sense = nv50_dac_sense; priv->sor.power = nv50_sor_power; priv->sor.hda_eld = nvd0_hda_eld; priv->sor.hdmi = nvd0_hdmi_ctrl; priv->sor.dp_train = nvd0_sor_dp_train; priv->sor.dp_train_init = nv94_sor_dp_train_init; priv->sor.dp_train_fini = nv94_sor_dp_train_fini; priv->sor.dp_lnkctl = nvd0_sor_dp_lnkctl; priv->sor.dp_drvctl = nvd0_sor_dp_drvctl; INIT_LIST_HEAD(&priv->base.vblank.list); spin_lock_init(&priv->base.vblank.lock); return 0; } struct nouveau_oclass nve0_disp_oclass = { .handle = NV_ENGINE(DISP, 0x91), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nve0_disp_ctor, .dtor = _nouveau_disp_dtor, .init = _nouveau_disp_init, .fini = _nouveau_disp_fini, }, };
.code.size = sizeof(nve0_grhub_code), .data.data = nve0_grhub_data, .data.size = sizeof(nve0_grhub_data), }; #include "fuc/gpcnve0.fuc.h" static struct nvc0_graph_ucode nve4_graph_gpccs_ucode = { .code.data = nve0_grgpc_code, .code.size = sizeof(nve0_grgpc_code), .data.data = nve0_grgpc_data, .data.size = sizeof(nve0_grgpc_data), }; struct nouveau_oclass * nve4_graph_oclass = &(struct nvc0_graph_oclass) { .base.handle = NV_ENGINE(GR, 0xe4), .base.ofuncs = &(struct nouveau_ofuncs) { .ctor = nvc0_graph_ctor, .dtor = nvc0_graph_dtor, .init = nve4_graph_init, .fini = nve4_graph_fini, }, .cclass = &nve4_grctx_oclass, .sclass = nve4_graph_sclass, .mmio = nve4_graph_pack_mmio, .fecs.ucode = &nve4_graph_fecs_ucode, .gpccs.ucode = &nve4_graph_gpccs_ucode, }.base;
nv_engine(priv)->sclass = g84_cipher_sclass; return 0; } static int g84_cipher_init(struct nvkm_object *object) { struct g84_cipher_priv *priv = (void *)object; int ret; ret = nvkm_engine_init(&priv->base); if (ret) return ret; nv_wr32(priv, 0x102130, 0xffffffff); nv_wr32(priv, 0x102140, 0xffffffbf); nv_wr32(priv, 0x10200c, 0x00000010); return 0; } struct nvkm_oclass g84_cipher_oclass = { .handle = NV_ENGINE(CIPHER, 0x84), .ofuncs = &(struct nvkm_ofuncs) { .ctor = g84_cipher_ctor, .dtor = _nvkm_engine_dtor, .init = g84_cipher_init, .fini = _nvkm_engine_fini, }, };
static int nvc0_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { struct nvc0_dmaeng_priv *priv; int ret; nv_warn(parent, "[%s]\n", __PRETTY_FUNCTION__); ret = nouveau_dmaeng_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_engine(priv)->sclass = nouveau_dmaobj_sclass; priv->base.bind = nvc0_dmaobj_bind; return 0; } struct nouveau_oclass nvc0_dmaeng_oclass = { .handle = NV_ENGINE(DMAOBJ, 0xc0), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nvc0_dmaeng_ctor, .dtor = _nouveau_dmaeng_dtor, .init = _nouveau_dmaeng_init, .fini = _nouveau_dmaeng_fini, }, };
} static struct nouveau_ofuncs nv50_dmaobj_ofuncs = { .ctor = nv50_dmaobj_ctor, .dtor = _nvkm_dmaobj_dtor, .init = _nvkm_dmaobj_init, .fini = _nvkm_dmaobj_fini, }; static struct nouveau_oclass nv50_dmaeng_sclass[] = { { NV_DMA_FROM_MEMORY, &nv50_dmaobj_ofuncs }, { NV_DMA_TO_MEMORY, &nv50_dmaobj_ofuncs }, { NV_DMA_IN_MEMORY, &nv50_dmaobj_ofuncs }, {} }; struct nouveau_oclass * nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { .base.handle = NV_ENGINE(DMAOBJ, 0x50), .base.ofuncs = &(struct nouveau_ofuncs) { .ctor = _nvkm_dmaeng_ctor, .dtor = _nvkm_dmaeng_dtor, .init = _nvkm_dmaeng_init, .fini = _nvkm_dmaeng_fini, }, .sclass = nv50_dmaeng_sclass, .bind = nv50_dmaobj_bind, }.base;
{ nvc1_graph_init_pe_0 }, { nvc0_graph_init_l1c_0 }, { nvc0_graph_init_wwdx_0 }, { nvc0_graph_init_tpccs_1 }, { nvc0_graph_init_mpc_0 }, { nvc4_graph_init_sm_0 }, { nvc0_graph_init_be_0 }, { nvc0_graph_init_fe_1 }, {} }; /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ struct nouveau_oclass * nvc1_graph_oclass = &(struct nvc0_graph_oclass) { .base.handle = NV_ENGINE(GR, 0xc1), .base.ofuncs = &(struct nouveau_ofuncs) { .ctor = nvc0_graph_ctor, .dtor = nvc0_graph_dtor, .init = nvc0_graph_init, .fini = _nouveau_graph_fini, }, .cclass = &nvc1_grctx_oclass, .sclass = nvc1_graph_sclass, .mmio = nvc1_graph_pack_mmio, .fecs.ucode = &nvc0_graph_fecs_ucode, .gpccs.ucode = &nvc0_graph_gpccs_ucode, }.base;
nv_wr32(priv, 0x00b0e0, 0x0000001a); nv_wr32(priv, 0x00b220, 0x00000044); nv_wr32(priv, 0x00b300, 0x00801ec1); nv_wr32(priv, 0x00b390, 0x00000000); nv_wr32(priv, 0x00b394, 0x00000000); nv_wr32(priv, 0x00b398, 0x00000000); nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); nv_wr32(priv, 0x00b100, 0xffffffff); nv_wr32(priv, 0x00b140, 0xffffffff); if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) { nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200)); return -EBUSY; } return 0; } struct nvkm_oclass nv50_mpeg_oclass = { .handle = NV_ENGINE(MPEG, 0x50), .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_mpeg_ctor, .dtor = _nvkm_mpeg_dtor, .init = nv50_mpeg_init, .fini = _nvkm_mpeg_fini, }, };
ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); *pobject = nv_object(priv); if (ret) return ret; nouveau_ramht_ref(imem->ramht, &priv->ramht); nouveau_gpuobj_ref(imem->ramro, &priv->ramro); nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); nv_subdev(priv)->unit = 0x00000100; nv_subdev(priv)->intr = nv04_fifo_intr; nv_engine(priv)->cclass = &nv10_fifo_cclass; nv_engine(priv)->sclass = nv10_fifo_sclass; priv->base.pause = nv04_fifo_pause; priv->base.start = nv04_fifo_start; priv->ramfc_desc = nv10_ramfc; return 0; } struct nouveau_oclass * nv10_fifo_oclass = &(struct nouveau_oclass) { .handle = NV_ENGINE(FIFO, 0x10), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv10_fifo_ctor, .dtor = nv04_fifo_dtor, .init = nv04_fifo_init, .fini = _nouveau_fifo_fini, }, };
.data.data = gm107_grhub_data, .data.size = sizeof(gm107_grhub_data), }; #include "fuc/gpcgm107.fuc5.h" static struct gf100_gr_ucode gm107_gr_gpccs_ucode = { .code.data = gm107_grgpc_code, .code.size = sizeof(gm107_grgpc_code), .data.data = gm107_grgpc_data, .data.size = sizeof(gm107_grgpc_data), }; struct nvkm_oclass * gm107_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0x07), .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gf100_gr_ctor, .dtor = gf100_gr_dtor, .init = gm107_gr_init, .fini = _nvkm_gr_fini, }, .cclass = &gm107_grctx_oclass, .sclass = gm107_gr_sclass, .mmio = gm107_gr_pack_mmio, .fecs.ucode = &gm107_gr_fecs_ucode, .gpccs.ucode = &gm107_gr_gpccs_ucode, .ppc_nr = 2, }.base;
{ struct nouveau_xtensa *priv; int ret; ret = nouveau_xtensa_create(parent, engine, oclass, 0xf000, true, "PVP", "vp", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x01020000; nv_engine(priv)->cclass = &nv84_vp_cclass; nv_engine(priv)->sclass = nv84_vp_sclass; priv->fifo_val = 0x111; priv->unkd28 = 0x9c544; return 0; } struct nouveau_oclass nv84_vp_oclass = { .handle = NV_ENGINE(VP, 0x84), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nv84_vp_ctor, .dtor = _nouveau_xtensa_dtor, .init = _nouveau_xtensa_init, .fini = _nouveau_xtensa_fini, .rd32 = _nouveau_xtensa_rd32, .wr32 = _nouveau_xtensa_wr32, }, };
#include "gf100.h" static int gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { struct gf100_pm_priv *priv; int ret; ret = nvkm_pm_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; nv_engine(priv)->cclass = &nvkm_pm_cclass; nv_engine(priv)->sclass = nvkm_pm_sclass; return 0; } struct nvkm_oclass gk110_pm_oclass = { .handle = NV_ENGINE(PM, 0xf0), .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk110_pm_ctor, .dtor = _nvkm_pm_dtor, .init = _nvkm_pm_init, .fini = gf100_pm_fini, }, };
}, &nv40_perfctr_func }, { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, { 0x20, (const struct nvkm_specsig[]) { {} }, &nv40_perfctr_func }, {} }; struct nvkm_oclass * g84_pm_oclass = &(struct nv40_pm_oclass) { .base.handle = NV_ENGINE(PM, 0x84), .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_pm_ctor, .dtor = _nvkm_pm_dtor, .init = _nvkm_pm_init, .fini = _nvkm_pm_fini, }, .doms = g84_pm, }.base;
* copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "gk104.h" struct nvkm_oclass * gk20a_fifo_oclass = &(struct gk104_fifo_impl) { .base.handle = NV_ENGINE(FIFO, 0xea), .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gk104_fifo_ctor, .dtor = gk104_fifo_dtor, .init = gk104_fifo_init, .fini = gk104_fifo_fini, }, .channels = 128, }.base;