NvError NvRmPrivAp20ChipUniqueId(NvRmDeviceHandle hDevHandle,void* pId)
{
NvU64* pOut = (NvU64*)pId; // Pointer to output buffer
NvU32 OldRegData; // Old register contents
NvU32 NewRegData; // New register contents
NV_ASSERT(hDevHandle);
NV_ASSERT(pId);
#if NV_USE_FUSE_CLOCK_ENABLE
// Enable fuse clock
Ap20EnableModuleClock(hDevHandle, NvRmModuleID_Fuse, NV_TRUE);
#endif
// Access to unique id is protected, so make sure all registers visible first.
OldRegData = NV_REGR(hDevHandle, NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_MISC_CLK_ENB_0);
NewRegData = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, MISC_CLK_ENB, CFG_ALL_VISIBLE, 1, OldRegData);
NV_REGW(hDevHandle, NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_MISC_CLK_ENB_0, NewRegData);
// Read the secure id from the fuse registers and copy to the output buffer.
*pOut = ((NvU64)NV_REGR(hDevHandle, (NvRmPrivModuleID)NvRmModuleID_Fuse, 0, FUSE_JTAG_SECUREID_0_0)) |
(((NvU64)NV_REGR(hDevHandle, (NvRmPrivModuleID)NvRmModuleID_Fuse, 0, FUSE_JTAG_SECUREID_1_0)) << 32);
// Restore the protected registers enable to the way we found it.
NV_REGW(hDevHandle, NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_MISC_CLK_ENB_0, OldRegData);
#if NV_USE_FUSE_CLOCK_ENABLE
// Disable fuse clock
Ap20EnableModuleClock(hDevHandle, NvRmModuleID_Fuse, NV_FALSE);
#endif
return NvError_Success;
}
static void aos_UartClockEnableT30(NvU32 port, NvBool Enable)
{
NvU32 Reg;
switch (port)
{
case UARTA:
Reg = NV_CAR_REGR(CLK_RST_PA_BASE, CLK_OUT_ENB_L);
Reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_OUT_ENB_L,
CLK_ENB_UARTA, Enable, Reg);
NV_CAR_REGW(CLK_RST_PA_BASE, CLK_OUT_ENB_L, Reg);
break;
case UARTB:
Reg = NV_CAR_REGR(CLK_RST_PA_BASE, CLK_OUT_ENB_L);
Reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_OUT_ENB_L,
CLK_ENB_UARTB, Enable, Reg);
NV_CAR_REGW(CLK_RST_PA_BASE, CLK_OUT_ENB_L, Reg);
break;
case UARTC:
Reg = NV_CAR_REGR(CLK_RST_PA_BASE, CLK_OUT_ENB_H);
Reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_OUT_ENB_H,
CLK_ENB_UARTC, Enable, Reg);
NV_CAR_REGW(CLK_RST_PA_BASE, CLK_OUT_ENB_H, Reg);
break;
case UARTD:
Reg = NV_CAR_REGR(CLK_RST_PA_BASE, CLK_OUT_ENB_U);
Reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_OUT_ENB_U,
CLK_ENB_UARTD, Enable, Reg);
NV_CAR_REGW(CLK_RST_PA_BASE, CLK_OUT_ENB_U, Reg);
break;
case UARTE:
Reg = NV_CAR_REGR(CLK_RST_PA_BASE, CLK_OUT_ENB_U);
Reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, CLK_OUT_ENB_U,
CLK_ENB_UARTE, Enable, Reg);
NV_CAR_REGW(CLK_RST_PA_BASE, CLK_OUT_ENB_U, Reg);
break;
default:
NV_ASSERT(0);
}
}
static void aos_UartResetT30(NvU32 port, NvBool Assert)
{
NvU32 Reg;
switch (port)
{
case UARTA:
Reg = NV_CAR_REGR(CLK_RST_PA_BASE, RST_DEVICES_L);
Reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, RST_DEVICES_L,
SWR_UARTA_RST, Assert, Reg);
NV_CAR_REGW(CLK_RST_PA_BASE, RST_DEVICES_L, Reg);
break;
case UARTB:
Reg = NV_CAR_REGR(CLK_RST_PA_BASE, RST_DEVICES_L);
Reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, RST_DEVICES_L,
SWR_UARTB_RST, Assert, Reg);
NV_CAR_REGW(CLK_RST_PA_BASE, RST_DEVICES_L, Reg);
break;
case UARTC:
Reg = NV_CAR_REGR(CLK_RST_PA_BASE, RST_DEVICES_H);
Reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, RST_DEVICES_H,
SWR_UARTC_RST, Assert, Reg);
NV_CAR_REGW(CLK_RST_PA_BASE, RST_DEVICES_H, Reg);
break;
case UARTD:
Reg = NV_CAR_REGR(CLK_RST_PA_BASE, RST_DEVICES_U);
Reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, RST_DEVICES_U,
SWR_UARTD_RST, Assert, Reg);
NV_CAR_REGW(CLK_RST_PA_BASE, RST_DEVICES_U, Reg);
break;
case UARTE:
Reg = NV_CAR_REGR(CLK_RST_PA_BASE, RST_DEVICES_U);
Reg = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, RST_DEVICES_U,
SWR_UARTE_RST, Assert, Reg);
NV_CAR_REGW(CLK_RST_PA_BASE, RST_DEVICES_U, Reg);
break;
default:
NV_ASSERT(0);
}
}
static NvError
NvRmPrivTvDcControl( NvRmDeviceHandle hDevice, NvBool enable, NvU32 inst,
void *Config, NvU32 ConfigLength )
{
NvRmAnalogTvDacConfig *cfg;
NvU32 ctrl, source;
NvU32 src_id;
NvU32 src_inst;
NV_ASSERT( ConfigLength == 0 ||
ConfigLength == sizeof(NvRmAnalogTvDacConfig) );
if( enable )
{
cfg = (NvRmAnalogTvDacConfig *)Config;
NV_ASSERT( cfg );
src_id = NVRM_MODULE_ID_MODULE( cfg->Source );
src_inst = NVRM_MODULE_ID_INSTANCE( cfg->Source );
ctrl = NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_IDDQ, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_POWERDOWN, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_DETECT_EN, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPR, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPG, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPB, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPR_EN, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPG_EN, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPB_EN, ENABLE );
if( src_id == NvRmModuleID_Tvo )
{
source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
DAC_SOURCE, TVO );
}
else
{
NV_ASSERT( src_id == NvRmModuleID_Display );
if( src_inst == 0 )
{
source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
DAC_SOURCE, DISPLAY );
}
else
{
source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
DAC_SOURCE, DISPLAYB );
}
}
source = NV_FLD_SET_DRF_NUM( APB_MISC_ASYNC, TVDACDINCONFIG, DAC_AMPIN,
cfg->DacAmplitude, source );
}
else
{
ctrl = NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_IDDQ, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_POWERDOWN, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_DETECT_EN, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPR, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPG, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_SLEEPB, ENABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPR_EN, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPG_EN, DISABLE )
| NV_DRF_DEF( APB_MISC_ASYNC, TVDACCNTL, DAC_COMPB_EN, DISABLE );
source = NV_DRF_DEF( APB_MISC_ASYNC, TVDACDINCONFIG,
DAC_SOURCE, TVDAC_OFF );
}
NV_REGW( hDevice, NvRmModuleID_Misc, 0, APB_MISC_ASYNC_TVDACCNTL_0,
ctrl );
NV_REGW( hDevice, NvRmModuleID_Misc, 0,
APB_MISC_ASYNC_TVDACDINCONFIG_0, source );
return NvSuccess;
}
