void
NvRmPrivGetSku( NvRmDeviceHandle rm )
{
NvError e;
NvRmChipId *id;
NvU8 *FuseVirt;
NvU32 reg;
#if NV_USE_FUSE_CLOCK_ENABLE
NvU8 *CarVirt = 0;
#endif
NV_ASSERT( rm );
id = &rm->ChipId;
#if NV_USE_FUSE_CLOCK_ENABLE
// Enable fuse clock
e = NvRmPhysicalMemMap(0x60006000, 0x1000, NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached, (void **)&CarVirt);
if (e == NvSuccess)
{
reg = NV_READ32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
reg |= 0x80;
NV_WRITE32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, reg);
}
#endif
/* Read the fuse only on real silicon, as it was not gauranteed to be
* preset on the eluation/simulation platforms.
*/
e = NvRmPhysicalMemMap(0x7000f800, 0x400, NVOS_MEM_READ_WRITE,
NvOsMemAttribute_Uncached, (void **)&FuseVirt);
if (e == NvSuccess)
{
// Read the SKU from the fuse module.
reg = NV_READ32( FuseVirt + FUSE_SKU_INFO_0 );
id->SKU = (NvU16)reg;
NvRmPhysicalMemUnmap(FuseVirt, 0x400);
#if NV_USE_FUSE_CLOCK_ENABLE
// Disable fuse clock
if (CarVirt)
{
reg = NV_READ32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
reg &= ~0x80;
NV_WRITE32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, reg);
NvRmPhysicalMemUnmap(CarVirt, 0x1000);
}
#endif
} else
{
NV_ASSERT(!"Cannot map the FUSE aperture to get the SKU");
id->SKU = 0;
}
}
void t30_UartD_Init(void)
{
NvU32 RegData;
// Initialization is responsible for correct pin mux configuration
// It also needs to wait for the correct osc frequency to be known
// IMPORTANT, there is some unspecified logic in the UART that always
// operate off PLLP_out3, mail from Robert Quan says that correct operation
// of UART without starting PLLP requires
// - to put PLLP in bypass
// - to override the PLLP_ou3 divider to be 1 (or put in bypass)
// This is done like that here to avoid any dependence on PLLP analog circuitry
// operating correctly
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_BASE_0);
RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_BASE_0, RegData);
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_OUTB_0);
RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_OUTB,
PLLP_OUT3_OVRRIDE, ENABLE);
RegData |= NV_DRF_NUM(CLK_RST_CONTROLLER,
PLLP_OUTB, PLLP_OUT3_RATIO, 0);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_OUTB_0, RegData);
// Set up the pinmuxes to bring UARTD out on ULPI_clk and ULPI_dir
// for waluigi T30. All alternate mappings of UARTD are set to select an input other than UARTD.
//
// GMI_AD16 => Alternate 1 ( SPI4 instead of UD3_TXD)
// GMI_AD17 => Alternate 1 ( SPI4 instead of UD3_RXD)
// ULPI_CLK =>Alternate 2 (UD3_TXD)
// ULPI_DIR =>Alternate 2 UD3_RXD)
//
// Last reviewed on 08/27/2010
SET_PIN(GMI_A16,PM,SPI4) ;
SET_PIN(GMI_A17,PM,SPI4) ;
SET_PIN(ULPI_CLK,PM,UARTD) ;
SET_PIN(ULPI_DIR,PM,UARTD) ;
// Enable the pads.
SET_PIN(ULPI_CLK, TRISTATE, NORMAL);
SET_PIN(ULPI_DIR, TRISTATE, NORMAL);
// enable UART D clock, toggle reset
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0);
RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_U,
CLK_ENB_UARTD, ENABLE);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0, RegData);
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_U_0);
RegData = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_U,
SWR_UARTD_RST, ENABLE, RegData);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_U_0, RegData);
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_U_0);
RegData = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_U,
SWR_UARTD_RST, DISABLE, RegData);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_U_0, RegData);
// Then there is the specific set up for UART itself, including the clock configuration.
// configure at top for source & configure the divider, internal to uart for obscure reasons
// when UARTD_DIV_ENB is enable DLL/DLLM programming is not required
//.Refer to the CLK_SOURCE_UARTD reg description in arclk_rst
// UARTD_DIV_ENB is disabled as new divisor logic is not enabled on FPGA Bug #739606
#if 0
NV_WRITE32(NV_ADDRESS_MAP_CAR_BASE+
CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0 ,
(CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_CLK_M <<
CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT) |
(CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_DISABLE <<
CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SHIFT) |
0);
#endif
}
void t30_UartC_Init(void)
{
NvU32 RegData;
// Initialization is responsible for correct pin mux configuration
// It also needs to wait for the correct osc frequency to be known
// IMPORTANT, there is some unspecified logic in the UART that always
// operate off PLLP_out3, mail from Robert Quan says that correct operation
// of UART without starting PLLP requires
// - to put PLLP in bypass
// - to override the PLLP_ou3 divider to be 1 (or put in bypass)
// This is done like that here to avoid any dependence on PLLP analog circuitry
// operating correctly
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_BASE_0);
RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_BASE_0, RegData);
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_OUTB_0);
RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_OUTB,
PLLP_OUT3_OVRRIDE, ENABLE);
RegData |= NV_DRF_NUM(CLK_RST_CONTROLLER,
PLLP_OUTB, PLLP_OUT3_RATIO, 0);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_OUTB_0, RegData);
// Set up the pinmuxes to bring UARTC out on uart3_txd and uart_rxd
// for oregon T30.
//
// UART3_TXD =>primary 0 (UC3_TXD)
// UART3_RXD =>primary 0(UC3_RXD)
//
SET_PIN(UART3_TXD,PM,UARTC) ;
SET_PIN(UART3_RXD,PM,UARTC) ;
// SET_PIN(UART3_CTS_N,PM,UARTC) ;
// SET_PIN(UART3_RTS_N,PM,UARTC) ;
// Enable the pads.
SET_PIN(UART3_TXD, TRISTATE, NORMAL);
SET_PIN(UART3_RXD, TRISTATE, NORMAL);
// enable UART C clock, toggle reset
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_H,
CLK_ENB_UARTC, ENABLE);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, RegData);
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_H_0);
RegData = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_H,
SWR_UARTC_RST, ENABLE, RegData);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_H_0, RegData);
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_H_0);
RegData = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_H,
SWR_UARTC_RST, DISABLE, RegData);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_H_0, RegData);
// Then there is the specific set up for UART itself, including the clock configuration.
// configure at top for source & configure the divider, internal to uart for obscure reasons
// when UARTC_DIV_ENB is enable DLL/DLLM programming is not required
//.Refer to the CLK_SOURCE_UARTD reg description in arclk_rst
// UARTD_DIV_ENB is disabled as new divisor logic is not enabled on FPGA Bug #739606
#if 0
NV_WRITE32(NV_ADDRESS_MAP_CAR_BASE+
CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0 ,
(CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_CLK_M <<
CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT) |
(CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_DISABLE <<
CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_DIV_ENB_SHIFT) |
0);
#endif
}
void t30_UartA_Init(void)
{
NvU32 RegData;
// Initialization is responsible for correct pin mux configuration
// It also needs to wait for the correct osc frequency to be known
// IMPORTANT, there is some unspecified logic in the UART that always
// operate off PLLP_out3, mail from Robert Quan says that correct operation
// of UART without starting PLLP requires
// - to put PLLP in bypass
// - to override the PLLP_ou3 divider to be 1 (or put in bypass)
// This is done like that here to avoid any dependence on PLLP analog circuitry
// operating correctly
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_BASE_0);
RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_BASE, PLLP_BYPASS, ENABLE);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_BASE_0, RegData);
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_OUTB_0);
RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, PLLP_OUTB,
PLLP_OUT3_OVRRIDE, ENABLE);
RegData |= NV_DRF_NUM(CLK_RST_CONTROLLER,
PLLP_OUTB, PLLP_OUT3_RATIO, 0);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_PLLP_OUTB_0, RegData);
// Set up the pinmuxes to bring UARTA out on ULPI_DATA0 and ULPI_DATA1
// for T30. All alternate mappings of UARTA are set to select an input other than UARTA.
//
// UART2_RTS_N => Alternate 3 ( SPI4 instead of UA3_TXD)
// UART2_CTS_N => Alternate 3 ( SPI4 instead of UA3_TXD)
// ULPI_DATA0 =>Alternate 2 (UA3_TXD)
// ULPI_DATA1 =>Alternate 2 UA3_RXD)
// SDMMC1_DAT3 => Primary (SDMMC1_DAT3 instead of UA3_TXD)
// SDMMC1_DAT2 => Primary (SDMMC1_DAT2 instead of UA3_RXD)
// GPIO_PU0 => Alternate 2 (GMI_A6 instead of UA3_TXD)
// GPIO_PU1 => Alternate 2 (GMI_A7 instead of UA3_RXD)
// SDMMC3_CLK => Alternate 2 (SDMMC3_SCLK instead of UA3_TXD)
// SDMMC3_CMD => Alternate 2 (SDMMC3_CMD instead of UA3_RXD)
//
// Last reviewed on 08/27/2010
SET_PIN(UART2_RTS_N,PM,SPI4) ;
SET_PIN(UART2_CTS_N,PM,SPI4) ;
SET_PIN(ULPI_DATA0,PM,UARTA) ;
SET_PIN(ULPI_DATA1,PM,UARTA) ;
SET_PIN(SDMMC1_DAT3,PM,SDMMC1) ;
SET_PIN(SDMMC1_DAT2,PM,SDMMC1) ;
SET_PIN(GPIO_PU0,PM,GMI) ;
SET_PIN(GPIO_PU1,PM,GMI) ;
SET_PIN(SDMMC3_CLK, PM, SDMMC3);
SET_PIN(SDMMC3_CMD, PM, SDMMC3);
// Enable the pads.
SET_PIN(ULPI_DATA0, TRISTATE, NORMAL);
SET_PIN(ULPI_DATA1, TRISTATE, NORMAL);
// enable UART A clock, toggle reset
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0);
RegData |= NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_OUT_ENB_L,
CLK_ENB_UARTA, ENABLE);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0, RegData);
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_L_0);
RegData = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_L,
SWR_UARTA_RST, ENABLE, RegData);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_L_0, RegData);
RegData = NV_READ32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_L_0);
RegData = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, RST_DEVICES_L,
SWR_UARTA_RST, DISABLE, RegData);
NV_WRITE32(NV_ADDRESS_MAP_PPSB_CLK_RST_BASE +
CLK_RST_CONTROLLER_RST_DEVICES_L_0, RegData);
// Then there is the specific set up for UART itself, including the clock configuration.
// configure at top for source & configure the divider, internal to uart for obscure reasons
// when UARTA_DIV_ENB is enable DLL/DLLM programming is not required
//.Refer to the CLK_SOURCE_UARTA reg description in arclk_rst
// UARTA_DIV_ENB is disabled as new divisor logic is not enabled on FPGA Bug #739606
NV_WRITE32(NV_ADDRESS_MAP_CAR_BASE+
CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0 ,
(CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_CLK_M <<
CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT) |
(CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_DISABLE <<
CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_SHIFT) |
0);
}
