static void
unm_nic_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
{
struct unm_adapter_s *adapter = netdev_priv(netdev);
uint32_t fw_major = 0;
uint32_t fw_minor = 0;
uint32_t fw_build = 0;
strncpy(drvinfo->driver, unm_nic_driver_name, 32);
strncpy(drvinfo->version, UNM_NIC_LINUX_VERSIONID, 32);
read_lock(&adapter->adapter_lock);
fw_major = NXRD32(adapter, UNM_FW_VERSION_MAJOR);
fw_minor = NXRD32(adapter, UNM_FW_VERSION_MINOR);
fw_build = NXRD32(adapter, UNM_FW_VERSION_SUB);
read_unlock(&adapter->adapter_lock);
sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
drvinfo->n_stats = UNM_NIC_STATS_LEN;
drvinfo->testinfo_len = UNM_NIC_TEST_LEN;
if (adapter->mdump.has_valid_dump) {
drvinfo->regdump_len = adapter->mdump.md_dump_size;
} else {
drvinfo->regdump_len = UNM_NIC_REGS_LEN;
}
drvinfo->eedump_len = unm_nic_get_eeprom_len(netdev);
}
static void
netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)
{
struct netxen_adapter *adapter = netdev_priv(dev);
__u32 mode, *regs_buff = p;
int i, window;
memset(p, 0, NETXEN_NIC_REGS_LEN);
regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
(adapter->pdev)->device;
/* which mode */
regs_buff[0] = NXRD32(adapter, NETXEN_NIU_MODE);
mode = regs_buff[0];
/* Common registers to all the modes */
regs_buff[2] = NXRD32(adapter, NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER);
/* GB/XGB Mode */
mode = (mode / 2) - 1;
window = 0;
if (mode <= 1) {
for (i = 3; niu_registers[mode].reg[i - 3] != -1; i++) {
/* GB: port specific registers */
if (mode == 0 && i >= 19)
window = adapter->physical_port *
NETXEN_NIC_PORT_WINDOW;
regs_buff[i] = NXRD32(adapter,
niu_registers[mode].reg[i - 3] + window);
}
}
}
static int
netxen_nic_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct netxen_adapter *adapter = netdev_priv(dev);
u32 wol_cfg = 0;
if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
return -EOPNOTSUPP;
if (wol->wolopts & ~WAKE_MAGIC)
return -EOPNOTSUPP;
wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
if (!(wol_cfg & (1 << adapter->portnum)))
return -EOPNOTSUPP;
wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
if (wol->wolopts & WAKE_MAGIC)
wol_cfg |= 1UL << adapter->portnum;
else
wol_cfg &= ~(1UL << adapter->portnum);
NXWR32(adapter, NETXEN_WOL_CONFIG, wol_cfg);
return 0;
}
int sw_lock(struct unm_adapter_s *adapter)
{
int i;
int done = 0, timeout = 0;
while (!done) {
/* acquire semaphore3 from PCI HW block */
done = NXRD32(adapter, UNM_PCIE_REG(PCIE_SEM6_LOCK));
if (done == 1)
break;
if (timeout >= sw_lock_timeout) {
return -1;
}
timeout++;
/*
* Yield CPU
*/
if(!in_atomic())
schedule();
else {
for(i = 0; i < 20; i++)
cpu_relax(); /*This a nop instr on i386*/
}
}
return 0;
}
static int
netxen_api_unlock(struct netxen_adapter *adapter)
{
/* Release PCIE HW semaphore5 */
NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM5_UNLOCK));
return 0;
}
static int
netxen_api_lock(struct netxen_adapter *adapter)
{
u32 done = 0, timeout = 0;
for (;;) {
/* Acquire PCIE HW semaphore5 */
done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM5_LOCK));
if (done == 1)
break;
if (++timeout >= NX_OS_CRB_RETRY_COUNT) {
printk(KERN_ERR "%s: lock timeout.\n", __func__);
return -1;
}
msleep(1);
}
#if 0
NXWR32(adapter,
NETXEN_API_LOCK_ID, NX_OS_API_LOCK_DRIVER);
#endif
return 0;
}
static int netxen_nic_reg_test(struct net_device *dev)
{
struct netxen_adapter *adapter = netdev_priv(dev);
u32 data_read, data_written;
data_read = NXRD32(adapter, NETXEN_PCIX_PH_REG(0));
if ((data_read & 0xffff) != PHAN_VENDOR_ID)
return 1;
data_written = (u32)0xa5a5a5a5;
NXWR32(adapter, CRB_SCRATCHPAD_TEST, data_written);
data_read = NXRD32(adapter, CRB_SCRATCHPAD_TEST);
if (data_written != data_read)
return 1;
return 0;
}
static void
netxen_nic_get_pauseparam(struct net_device *dev,
struct ethtool_pauseparam *pause)
{
struct netxen_adapter *adapter = netdev_priv(dev);
__u32 val;
int port = adapter->physical_port;
if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
return;
/* get flow control settings */
val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port));
pause->rx_pause = netxen_gb_get_rx_flowctl(val);
val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL);
switch (port) {
case 0:
pause->tx_pause = !(netxen_gb_get_gb0_mask(val));
break;
case 1:
pause->tx_pause = !(netxen_gb_get_gb1_mask(val));
break;
case 2:
pause->tx_pause = !(netxen_gb_get_gb2_mask(val));
break;
case 3:
default:
pause->tx_pause = !(netxen_gb_get_gb3_mask(val));
break;
}
} else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
return;
pause->rx_pause = 1;
val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL);
if (port == 0)
pause->tx_pause = !(netxen_xg_get_xg0_mask(val));
else
pause->tx_pause = !(netxen_xg_get_xg1_mask(val));
} else {
printk(KERN_ERR"%s: Unknown board type: %x\n",
netxen_nic_driver_name, adapter->ahw.port_type);
}
}
static void
netxen_nic_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
struct netxen_adapter *adapter = netdev_priv(dev);
u32 wol_cfg = 0;
wol->supported = 0;
wol->wolopts = 0;
if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
return;
wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
if (wol_cfg & (1UL << adapter->portnum))
wol->supported |= WAKE_MAGIC;
wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
if (wol_cfg & (1UL << adapter->portnum))
wol->wolopts |= WAKE_MAGIC;
}
static int unm_nic_reg_test(struct net_device *netdev)
{
struct unm_adapter_s *adapter = netdev_priv(netdev);
uint32_t data_read, data_written;
// Read test
data_read = NXRD32(adapter, UNM_PCIX_PH_REG(0));
if ((data_read & 0xffff) != PHAN_VENDOR_ID) {
return 1;
}
// write test
data_written = (uint32_t) 0xa5a5a5a5;
NXWR32(adapter, CRB_SCRATCHPAD_TEST, data_written);
data_read = NXRD32(adapter, CRB_SCRATCHPAD_TEST);
if (data_written != data_read) {
return 1;
}
return 0;
}
static void
netxen_nic_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
{
struct netxen_adapter *adapter = netdev_priv(dev);
unsigned long flags;
u32 fw_major = 0;
u32 fw_minor = 0;
u32 fw_build = 0;
strncpy(drvinfo->driver, netxen_nic_driver_name, 32);
strncpy(drvinfo->version, NETXEN_NIC_LINUX_VERSIONID, 32);
write_lock_irqsave(&adapter->adapter_lock, flags);
fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
write_unlock_irqrestore(&adapter->adapter_lock, flags);
sprintf(drvinfo->fw_version, "%d.%d.%d", fw_major, fw_minor, fw_build);
strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
drvinfo->regdump_len = NETXEN_NIC_REGS_LEN;
drvinfo->eedump_len = netxen_nic_get_eeprom_len(dev);
}
static u32
netxen_poll_rsp(struct netxen_adapter *adapter)
{
u32 rsp = NX_CDRP_RSP_OK;
int timeout = 0;
do {
/* give atleast 1ms for firmware to respond */
msleep(1);
if (++timeout > NX_OS_CRB_RETRY_COUNT)
return NX_CDRP_RSP_TIMEOUT;
rsp = NXRD32(adapter, NX_CDRP_CRB_OFFSET);
} while (!NX_CDRP_IS_RSP(rsp));
return rsp;
}
int
nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val)
{
u32 rcode;
rcode = netxen_issue_cmd(adapter,
adapter->ahw.pci_func,
NXHAL_VERSION,
reg,
0,
0,
NX_CDRP_CMD_READ_PHY);
if (rcode != NX_RCODE_SUCCESS)
return -EIO;
return NXRD32(adapter, NX_ARG1_CRB_OFFSET);
}
static u32
netxen_issue_cmd(struct netxen_adapter *adapter,
u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd)
{
u32 rsp;
u32 signature = 0;
u32 rcode = NX_RCODE_SUCCESS;
signature = NX_CDRP_SIGNATURE_MAKE(pci_fn, version);
/* Acquire semaphore before accessing CRB */
if (netxen_api_lock(adapter))
return NX_RCODE_TIMEOUT;
NXWR32(adapter, NX_SIGN_CRB_OFFSET, signature);
NXWR32(adapter, NX_ARG1_CRB_OFFSET, arg1);
NXWR32(adapter, NX_ARG2_CRB_OFFSET, arg2);
NXWR32(adapter, NX_ARG3_CRB_OFFSET, arg3);
NXWR32(adapter, NX_CDRP_CRB_OFFSET, NX_CDRP_FORM_CMD(cmd));
rsp = netxen_poll_rsp(adapter);
if (rsp == NX_CDRP_RSP_TIMEOUT) {
printk(KERN_ERR "%s: card response timeout.\n",
netxen_nic_driver_name);
rcode = NX_RCODE_TIMEOUT;
} else if (rsp == NX_CDRP_RSP_FAIL) {
rcode = NXRD32(adapter, NX_ARG1_CRB_OFFSET);
printk(KERN_ERR "%s: failed card response code:0x%x\n",
netxen_nic_driver_name, rcode);
}
/* Release semaphore */
netxen_api_unlock(adapter);
return rcode;
}
static u32 netxen_nic_test_link(struct net_device *dev)
{
struct netxen_adapter *adapter = netdev_priv(dev);
__u32 status;
int val;
/* read which mode */
if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
if (adapter->phy_read
&& adapter->phy_read(adapter,
NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
&status) != 0)
return -EIO;
else {
val = netxen_get_phy_link(status);
return !val;
}
} else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
val = NXRD32(adapter, CRB_XG_STATE);
return (val == XG_LINK_UP) ? 0 : 1;
}
return -EIO;
}
static int
netxen_nic_set_pauseparam(struct net_device *dev,
struct ethtool_pauseparam *pause)
{
struct netxen_adapter *adapter = netdev_priv(dev);
__u32 val;
int port = adapter->physical_port;
/* read mode */
if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
return -EIO;
/* set flow control */
val = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port));
if (pause->rx_pause)
netxen_gb_rx_flowctl(val);
else
netxen_gb_unset_rx_flowctl(val);
NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
val);
/* set autoneg */
val = NXRD32(adapter, NETXEN_NIU_GB_PAUSE_CTL);
switch (port) {
case 0:
if (pause->tx_pause)
netxen_gb_unset_gb0_mask(val);
else
netxen_gb_set_gb0_mask(val);
break;
case 1:
if (pause->tx_pause)
netxen_gb_unset_gb1_mask(val);
else
netxen_gb_set_gb1_mask(val);
break;
case 2:
if (pause->tx_pause)
netxen_gb_unset_gb2_mask(val);
else
netxen_gb_set_gb2_mask(val);
break;
case 3:
default:
if (pause->tx_pause)
netxen_gb_unset_gb3_mask(val);
else
netxen_gb_set_gb3_mask(val);
break;
}
NXWR32(adapter, NETXEN_NIU_GB_PAUSE_CTL, val);
} else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
return -EIO;
val = NXRD32(adapter, NETXEN_NIU_XG_PAUSE_CTL);
if (port == 0) {
if (pause->tx_pause)
netxen_xg_unset_xg0_mask(val);
else
netxen_xg_set_xg0_mask(val);
} else {
if (pause->tx_pause)
netxen_xg_unset_xg1_mask(val);
else
netxen_xg_set_xg1_mask(val);
}
NXWR32(adapter, NETXEN_NIU_XG_PAUSE_CTL, val);
} else {
printk(KERN_ERR "%s: Unknown board type: %x\n",
netxen_nic_driver_name,
adapter->ahw.port_type);
}
return 0;
}
void sw_unlock(struct unm_adapter_s *adapter)
{
int val;
/* release semaphore3 */
val = NXRD32(adapter, UNM_PCIE_REG(PCIE_SEM6_UNLOCK));
}
static int
unm_nic_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
{
struct unm_adapter_s *adapter = netdev_priv(netdev);
unm_board_info_t *boardinfo;
u32 port_mode = 0;
int linkevent_cap;
boardinfo = &adapter->ahw.boardcfg;
linkevent_cap = nx_nic_get_linkevent_cap(adapter) &&
netif_running(netdev);
// read which mode
if (adapter->ahw.board_type == UNM_NIC_GBE) {
ecmd->supported = ( SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Full);
ecmd->advertising = ( ADVERTISED_100baseT_Full |
ADVERTISED_1000baseT_Full);
ecmd->speed = adapter->link_speed;
ecmd->duplex = adapter->link_duplex;
ecmd->autoneg = adapter->link_autoneg;
} else if (adapter->ahw.board_type == UNM_NIC_XGBE) {
port_mode = NXRD32(adapter, UNM_PORT_MODE_ADDR);
if (port_mode == UNM_PORT_MODE_802_3_AP) {
ecmd->supported = SUPPORTED_1000baseT_Full;
ecmd->advertising = ADVERTISED_1000baseT_Full;
ecmd->speed = SPEED_1000;
} else {
ecmd->supported = SUPPORTED_10000baseT_Full;
ecmd->advertising = ADVERTISED_10000baseT_Full;
ecmd->speed = SPEED_10000;
}
ecmd->duplex = DUPLEX_FULL;
/* if f/w can send async notification,
* link_speed is the correct speed
*/
if (linkevent_cap) {
ecmd->speed = adapter->link_speed;
} else if((adapter->ahw.revision_id >= NX_P3_B0)) {
u32 val;
/* Use the per-function link speed value */
val = NXRD32(adapter,
PF_LINK_SPEED_REG(adapter->ahw.pci_func));
/* we have per-function link speed */
ecmd->speed = PF_LINK_SPEED_VAL(adapter->ahw.pci_func, val)
* PF_LINK_SPEED_MHZ;
}
} else {
printk(KERN_ERR "%s: ERROR: Unsupported board model %d\n",
unm_nic_driver_name,
(unm_brdtype_t) boardinfo->board_type);
return -EIO;
}
ecmd->phy_address = adapter->portnum;
ecmd->transceiver = XCVR_EXTERNAL;
switch ((unm_brdtype_t) boardinfo->board_type) {
case UNM_BRDTYPE_P3_REF_QG:
case UNM_BRDTYPE_P3_4_GB:
case UNM_BRDTYPE_P3_4_GB_MM:
ecmd->supported |= SUPPORTED_Autoneg;
ecmd->advertising |= ADVERTISED_Autoneg;
case UNM_BRDTYPE_P3_10G_CX4:
case UNM_BRDTYPE_P3_10G_CX4_LP:
case UNM_BRDTYPE_P3_10000_BASE_T:
ecmd->supported |= SUPPORTED_TP;
ecmd->advertising |= ADVERTISED_TP;
ecmd->port = PORT_TP;
ecmd->autoneg = adapter->link_autoneg;
break;
case UNM_BRDTYPE_P3_XG_LOM:
case UNM_BRDTYPE_P3_HMEZ:
ecmd->supported = (SUPPORTED_1000baseT_Full |
SUPPORTED_10000baseT_Full |
SUPPORTED_Autoneg | SUPPORTED_MII);
ecmd->advertising = (ADVERTISED_1000baseT_Full |
ADVERTISED_10000baseT_Full |
ADVERTISED_Autoneg | ADVERTISED_MII);
ecmd->port = PORT_MII;
ecmd->autoneg = AUTONEG_ENABLE;
break;
case UNM_BRDTYPE_P3_IMEZ:
ecmd->supported |= SUPPORTED_MII;
ecmd->advertising |= ADVERTISED_MII;
ecmd->port = PORT_MII;
ecmd->autoneg = AUTONEG_DISABLE;
break;
case UNM_BRDTYPE_P3_10G_SFP_PLUS:
case UNM_BRDTYPE_P3_10G_XFP:
ecmd->supported |= SUPPORTED_FIBRE;
ecmd->advertising |= ADVERTISED_FIBRE;
if (linkevent_cap && adapter->link_module_type ==
LINKEVENT_MODULE_TWINAX) {
ecmd->port = PORT_TP;
} else {
ecmd->port = PORT_FIBRE;
}
ecmd->autoneg = AUTONEG_DISABLE;
break;
case UNM_BRDTYPE_P3_10G_TP:
if (adapter->ahw.board_type == UNM_NIC_XGBE) {
ecmd->autoneg = AUTONEG_DISABLE;
ecmd->supported |= SUPPORTED_FIBRE;
ecmd->advertising |= ADVERTISED_FIBRE;
ecmd->port = PORT_FIBRE;
}else {
ecmd->autoneg = AUTONEG_ENABLE;
ecmd->supported |= (SUPPORTED_TP |SUPPORTED_Autoneg);
ecmd->advertising |= (ADVERTISED_TP | ADVERTISED_Autoneg);
ecmd->port = PORT_TP;
}
break;
default:
printk(KERN_ERR "%s: ERROR: Unsupported board model %d\n",
unm_nic_driver_name,
(unm_brdtype_t) boardinfo->board_type);
return -EIO;
break;
}
return 0;
}
static int
netxen_nic_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
{
struct netxen_adapter *adapter = netdev_priv(dev);
int check_sfp_module = 0;
/* read which mode */
if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
ecmd->supported = (SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Half |
SUPPORTED_1000baseT_Full);
ecmd->advertising = (ADVERTISED_100baseT_Half |
ADVERTISED_100baseT_Full |
ADVERTISED_1000baseT_Half |
ADVERTISED_1000baseT_Full);
ecmd->port = PORT_TP;
ecmd->speed = adapter->link_speed;
ecmd->duplex = adapter->link_duplex;
ecmd->autoneg = adapter->link_autoneg;
} else if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
u32 val;
val = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
if (val == NETXEN_PORT_MODE_802_3_AP) {
ecmd->supported = SUPPORTED_1000baseT_Full;
ecmd->advertising = ADVERTISED_1000baseT_Full;
} else {
ecmd->supported = SUPPORTED_10000baseT_Full;
ecmd->advertising = ADVERTISED_10000baseT_Full;
}
if (netif_running(dev) && adapter->has_link_events) {
ecmd->speed = adapter->link_speed;
ecmd->autoneg = adapter->link_autoneg;
ecmd->duplex = adapter->link_duplex;
goto skip;
}
ecmd->port = PORT_TP;
if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
u16 pcifn = adapter->ahw.pci_func;
val = NXRD32(adapter, P3_LINK_SPEED_REG(pcifn));
ecmd->speed = P3_LINK_SPEED_MHZ *
P3_LINK_SPEED_VAL(pcifn, val);
} else
ecmd->speed = SPEED_10000;
ecmd->duplex = DUPLEX_FULL;
ecmd->autoneg = AUTONEG_DISABLE;
} else
return -EIO;
skip:
ecmd->phy_address = adapter->physical_port;
ecmd->transceiver = XCVR_EXTERNAL;
switch (adapter->ahw.board_type) {
case NETXEN_BRDTYPE_P2_SB35_4G:
case NETXEN_BRDTYPE_P2_SB31_2G:
case NETXEN_BRDTYPE_P3_REF_QG:
case NETXEN_BRDTYPE_P3_4_GB:
case NETXEN_BRDTYPE_P3_4_GB_MM:
ecmd->supported |= SUPPORTED_Autoneg;
ecmd->advertising |= ADVERTISED_Autoneg;
case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
case NETXEN_BRDTYPE_P3_10G_CX4:
case NETXEN_BRDTYPE_P3_10G_CX4_LP:
case NETXEN_BRDTYPE_P3_10000_BASE_T:
ecmd->supported |= SUPPORTED_TP;
ecmd->advertising |= ADVERTISED_TP;
ecmd->port = PORT_TP;
ecmd->autoneg = (adapter->ahw.board_type ==
NETXEN_BRDTYPE_P2_SB31_10G_CX4) ?
(AUTONEG_DISABLE) : (adapter->link_autoneg);
break;
case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
case NETXEN_BRDTYPE_P3_IMEZ:
case NETXEN_BRDTYPE_P3_XG_LOM:
case NETXEN_BRDTYPE_P3_HMEZ:
ecmd->supported |= SUPPORTED_MII;
ecmd->advertising |= ADVERTISED_MII;
ecmd->port = PORT_MII;
ecmd->autoneg = AUTONEG_DISABLE;
break;
case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
case NETXEN_BRDTYPE_P3_10G_SFP_CT:
case NETXEN_BRDTYPE_P3_10G_SFP_QT:
ecmd->advertising |= ADVERTISED_TP;
ecmd->supported |= SUPPORTED_TP;
check_sfp_module = netif_running(dev) &&
adapter->has_link_events;
case NETXEN_BRDTYPE_P2_SB31_10G:
case NETXEN_BRDTYPE_P3_10G_XFP:
ecmd->supported |= SUPPORTED_FIBRE;
ecmd->advertising |= ADVERTISED_FIBRE;
ecmd->port = PORT_FIBRE;
ecmd->autoneg = AUTONEG_DISABLE;
break;
case NETXEN_BRDTYPE_P3_10G_TP:
if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
ecmd->autoneg = AUTONEG_DISABLE;
ecmd->supported |= (SUPPORTED_FIBRE | SUPPORTED_TP);
ecmd->advertising |=
(ADVERTISED_FIBRE | ADVERTISED_TP);
ecmd->port = PORT_FIBRE;
check_sfp_module = netif_running(dev) &&
adapter->has_link_events;
} else {
ecmd->autoneg = AUTONEG_ENABLE;
ecmd->supported |= (SUPPORTED_TP |SUPPORTED_Autoneg);
ecmd->advertising |=
(ADVERTISED_TP | ADVERTISED_Autoneg);
ecmd->port = PORT_TP;
}
break;
default:
printk(KERN_ERR "netxen-nic: Unsupported board model %d\n",
adapter->ahw.board_type);
return -EIO;
}
if (check_sfp_module) {
switch (adapter->module_type) {
case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
case LINKEVENT_MODULE_OPTICAL_SRLR:
case LINKEVENT_MODULE_OPTICAL_LRM:
case LINKEVENT_MODULE_OPTICAL_SFP_1G:
ecmd->port = PORT_FIBRE;
break;
case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
case LINKEVENT_MODULE_TWINAX:
ecmd->port = PORT_TP;
break;
default:
ecmd->port = -1;
}
}
return 0;
}
static void
unm_nic_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
{
struct unm_adapter_s *adapter = netdev_priv(netdev);
if (adapter->mdump.has_valid_dump) {
u8 *capture_buff = adapter->mdump.md_capture_buff;
memset(p, 0, adapter->mdump.md_dump_size);
regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
adapter->ahw.device_id;
memcpy(p, capture_buff, adapter->mdump.md_dump_size);
} else {
unm_crbword_t mode, *regs_buff = p;
memset(p, 0, UNM_NIC_REGS_LEN);
regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |
adapter->ahw.device_id;
/* P3 */
// which mode
regs_buff[0] = NXRD32(adapter, UNM_PORT_MODE_ADDR);
mode = regs_buff[0];
// Common registers to all the modes
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_STRAP_VALUE_SAVE_HIGHER),
0, ®s_buff[2]);
switch (mode) {
case UNM_PORT_MODE_XG:
case UNM_PORT_MODE_AUTO_NEG_XG:{
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_SINGLE_TERM),
0, ®s_buff[3]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_DRIVE_HI),
0, ®s_buff[4]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_DRIVE_LO),
0, ®s_buff[5]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_DTX),
0, ®s_buff[6]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_DEQ),
0, ®s_buff[7]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_WORD_ALIGN),
0, ®s_buff[8]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_RESET),
0, ®s_buff[9]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_POWER_DOWN),
0, ®s_buff[10]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_RESET_PLL),
0, ®s_buff[11]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_SERDES_LOOPBACK),
0, ®s_buff[12]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_DO_BYTE_ALIGN),
0, ®s_buff[13]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_TX_ENABLE),
0, ®s_buff[14]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_RX_ENABLE),
0, ®s_buff[15]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_STATUS),
0, ®s_buff[16]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XG_PAUSE_THRESHOLD),
0, ®s_buff[17]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_CONFIG_0),
0, ®s_buff[18]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_CONFIG_1),
0, ®s_buff[19]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_IPG),
0, ®s_buff[20]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_STATION_ADDR_0_HI),
0, ®s_buff[21]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_STATION_ADDR_0_1),
0, ®s_buff[22]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_STATION_ADDR_1_LO),
0, ®s_buff[23]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_STATUS),
0, ®s_buff[24]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_MAX_FRAME_SIZE),
0, ®s_buff[25]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_PAUSE_FRAME_VALUE),
0, ®s_buff[26]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_TX_BYTE_CNT),
0, ®s_buff[27]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_TX_FRAME_CNT),
0, ®s_buff[28]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_RX_BYTE_CNT),
0, ®s_buff[29]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_RX_FRAME_CNT),
0, ®s_buff[30]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_AGGR_ERROR_CNT),
0, ®s_buff[31]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_MULTICAST_FRAME_CNT),
0, ®s_buff[32]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_UNICAST_FRAME_CNT),
0, ®s_buff[33]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_CRC_ERROR_CNT),
0, ®s_buff[34]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_OVERSIZE_FRAME_ERR),
0, ®s_buff[35]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_UNDERSIZE_FRAME_ERR),
0, ®s_buff[36]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_LOCAL_ERROR_CNT),
0, ®s_buff[37]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_REMOTE_ERROR_CNT),
0, ®s_buff[38]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_CONTROL_CHAR_CNT),
0, ®s_buff[39]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_XGE_PAUSE_FRAME_CNT),
0, ®s_buff[40]);
break;
}
case UNM_PORT_MODE_GB:
case UNM_PORT_MODE_AUTO_NEG_1G:{
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_SERDES_RESET),
0, ®s_buff[3]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB0_MII_MODE),
0, ®s_buff[4]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB1_MII_MODE),
0, ®s_buff[5]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB2_MII_MODE),
0, ®s_buff[6]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB3_MII_MODE),
0, ®s_buff[7]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB0_GMII_MODE),
0, ®s_buff[8]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB1_GMII_MODE),
0, ®s_buff[9]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB2_GMII_MODE),
0, ®s_buff[10]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB3_GMII_MODE),
0, ®s_buff[11]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_REMOTE_LOOPBACK),
0, ®s_buff[12]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB0_HALF_DUPLEX),
0, ®s_buff[13]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB1_HALF_DUPLEX),
0, ®s_buff[14]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_RESET_SYS_FIFOS),
0, ®s_buff[15]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_CRC_DROP),
0, ®s_buff[16]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_DROP_WRONGADDR),
0, ®s_buff[17]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_TEST_MUX_CTL),
0, ®s_buff[18]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_MAC_CONFIG_0(0)),
0x10000, ®s_buff[19]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_MAC_CONFIG_1(0)),
0x10000, ®s_buff[20]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_HALF_DUPLEX_CTRL(0)),
0x10000, ®s_buff[21]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_MAX_FRAME_SIZE(0)),
0x10000, ®s_buff[22]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_TEST_REG(0)),
0x10000, ®s_buff[23]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_MII_MGMT_CONFIG(0)),
0x10000, ®s_buff[24]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_MII_MGMT_COMMAND(0)),
0x10000, ®s_buff[25]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_MII_MGMT_ADDR(0)),
0x10000, ®s_buff[26]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_MII_MGMT_CTRL(0)),
0x10000, ®s_buff[27]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_MII_MGMT_STATUS(0)),
0x10000, ®s_buff[28]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_MII_MGMT_INDICATE(0)),
0x10000, ®s_buff[29]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_INTERFACE_CTRL(0)),
0x10000, ®s_buff[30]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_INTERFACE_STATUS(0)),
0x10000, ®s_buff[31]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_STATION_ADDR_0(0)),
0x10000, ®s_buff[32]);
nx_fw_cmd_query_hw_reg(adapter, adapter->portnum,
crb_pci_to_internal(UNM_NIU_GB_STATION_ADDR_1(0)),
0x10000, ®s_buff[33]);
break;
}
}
}
}
