/*------------------------------------------------------------------------------ * CPU initialize */ void nxp_periph_init(void) { #if (CFG_UART_DEBUG_CH == 0) int id = RESET_ID_UART0; char *dev = "nxp-uart.0"; #elif (CFG_UART_DEBUG_CH == 1) int id = RESET_ID_UART1; char *dev = "nxp-uart.1"; #elif (CFG_UART_DEBUG_CH == 2) int id = RESET_ID_UART2; char *dev = "nxp-uart.2"; #elif (CFG_UART_DEBUG_CH == 3) int id = RESET_ID_UART3; char *dev = "nxp-uart.3"; #elif (CFG_UART_DEBUG_CH == 4) int id = RESET_ID_UART4; char *dev = "nxp-uart.4"; #elif (CFG_UART_DEBUG_CH == 5) int id = RESET_ID_UART5; char *dev = "nxp-uart.5"; #endif struct clk *clk = clk_get(NULL, (const char*)dev); /* reset control: Low active ___|--- */ NX_RSTCON_SetnRST(id, RSTCON_nDISABLE); NX_RSTCON_SetnRST(id, RSTCON_nENABLE); /* set clock */ clk_disable(clk); clk_set_rate(clk, CFG_UART_CLKGEN_CLOCK_HZ); clk_enable(clk); }
static void _vip_hw_set_clock(int module, struct nxp_backward_camera_platform_data *param, bool on) { if (on) { volatile u32 *clkgen_base = (volatile u32 *)IO_ADDRESS(NX_CLKGEN_GetPhysicalAddress(NX_VIP_GetClockNumber(module))); NX_CLKGEN_SetBaseAddress(NX_VIP_GetClockNumber(module), (U32)clkgen_base); NX_CLKGEN_SetClockDivisorEnable(NX_VIP_GetClockNumber(module), CTRUE); NX_CLKGEN_SetClockBClkMode(NX_VIP_GetClockNumber(module), NX_BCLKMODE_DYNAMIC); /* printk("RSTCON Base: 0x%x\n", NX_RSTCON_GetBaseAddress()); */ /* printk("RSTCON VIP %d Reset Number %d, REG Number %d\n", module, NX_VIP_GetResetNumber(module), NX_VIP_GetResetNumber(module)>>5); */ /* printk("CLKGEN Base: 0x%x\n", clkgen_base); */ NX_RSTCON_SetnRST(NX_VIP_GetResetNumber(module), RSTCON_nDISABLE); NX_RSTCON_SetnRST(NX_VIP_GetResetNumber(module), RSTCON_nENABLE); if (param->is_mipi) { printk("%s: apply mipi csi clock!!!\n", __func__); NX_CLKGEN_SetClockSource(NX_VIP_GetClockNumber(module), 0, 2); /* external PCLK */ NX_CLKGEN_SetClockDivisor(NX_VIP_GetClockNumber(module), 0, 2); NX_CLKGEN_SetClockDivisorEnable(NX_VIP_GetClockNumber(module), CTRUE); } else { NX_CLKGEN_SetClockSource(NX_VIP_GetClockNumber(module), 0, 4 + param->port); /* external PCLK */ NX_CLKGEN_SetClockDivisor(NX_VIP_GetClockNumber(module), 0, 1); NX_CLKGEN_SetClockDivisorEnable(NX_VIP_GetClockNumber(module), CTRUE); } printk("VIP CLK GEN VAL: 0x%x\n", *clkgen_base); NX_VIP_SetBaseAddress(module, IO_ADDRESS(NX_VIP_GetPhysicalAddress(module))); } }
int bd_eth_init(void) { #if defined(CONFIG_DESIGNWARE_ETH) u32 addr; // Clock control NX_CLKGEN_Initialize(); addr = NX_CLKGEN_GetPhysicalAddress(CLOCKINDEX_OF_DWC_GMAC_MODULE); NX_CLKGEN_SetBaseAddress( CLOCKINDEX_OF_DWC_GMAC_MODULE, (u32)IO_ADDRESS(addr) ); NX_CLKGEN_SetClockSource( CLOCKINDEX_OF_DWC_GMAC_MODULE, 0, 4); // Sync mode for 100 & 10Base-T : External RX_clk NX_CLKGEN_SetClockDivisor( CLOCKINDEX_OF_DWC_GMAC_MODULE, 0, 1); // Sync mode for 100 & 10Base-T NX_CLKGEN_SetClockOutInv( CLOCKINDEX_OF_DWC_GMAC_MODULE, 0, CFALSE); // TX Clk invert off : 100 & 10Base-T // NX_CLKGEN_SetClockOutInv( CLOCKINDEX_OF_DWC_GMAC_MODULE, 0, CTRUE); // TX clk invert on : 100 & 10Base-T NX_CLKGEN_SetClockDivisorEnable( CLOCKINDEX_OF_DWC_GMAC_MODULE, CTRUE); // Reset control NX_RSTCON_Initialize(); addr = NX_RSTCON_GetPhysicalAddress(); NX_RSTCON_SetBaseAddress( (u32)IO_ADDRESS(addr) ); NX_RSTCON_SetnRST(RESETINDEX_OF_DWC_GMAC_MODULE_aresetn_i, RSTCON_ENABLE); udelay(100); NX_RSTCON_SetnRST(RESETINDEX_OF_DWC_GMAC_MODULE_aresetn_i, RSTCON_DISABLE); udelay(100); NX_RSTCON_SetnRST(RESETINDEX_OF_DWC_GMAC_MODULE_aresetn_i, RSTCON_ENABLE); udelay(100); // Set interrupt config. //nxp_gpio_set_pull_sel(CFG_ETHER_GMAC_PHY_IRQ_NUM, CTRUE); //nxp_gpio_set_pull_enb(CFG_ETHER_GMAC_PHY_IRQ_NUM, CTRUE); gpio_direction_input(CFG_ETHER_GMAC_PHY_IRQ_NUM); // Set GPIO nReset //nxp_gpio_set_pull_enb(CFG_ETHER_GMAC_PHY_RST_NUM, CFALSE); gpio_direction_output(CFG_ETHER_GMAC_PHY_RST_NUM, 1 ); udelay( 100 ); gpio_set_value(CFG_ETHER_GMAC_PHY_RST_NUM, 0 ); udelay( 100 ); gpio_set_value(CFG_ETHER_GMAC_PHY_RST_NUM, 1 ); #endif // #if defined(CONFIG_DESIGNWARE_ETH) return 0; }
void disp_syncgen_reset(void) { /* RESET: Dual Display = MLC0/DPC0 and MLC1/DPC1 = Low active ___|--- */ int rstnum = NX_DUALDISPLAY_GetResetNumber(0); DBGOUT("Reset SYNCGEN\n"); #if defined(CONFIG_MACH_S5P4418) if (NX_RSTCON_GetnRST(rstnum)) return; NX_RSTCON_SetnRST(rstnum, RSTCON_nDISABLE); NX_RSTCON_SetnRST(rstnum, RSTCON_nENABLE); #elif defined(CONFIG_MACH_S5P6818) if (NX_RSTCON_GetRST(rstnum)) return; NX_RSTCON_SetRST(rstnum, RSTCON_ASSERT); NX_RSTCON_SetRST(rstnum, RSTCON_NEGATE); #endif }
void disp_topctl_reset(void) { /* RESET: DISPLAYTOP = Low active ___|--- */ int rstnum = NX_DISPLAYTOP_GetResetNumber(); DBGOUT("Reset TOPCTRL\n"); #if defined(CONFIG_MACH_S5P4418) if (NX_RSTCON_GetnRST(rstnum)) return; NX_RSTCON_SetnRST(rstnum, RSTCON_nDISABLE); NX_RSTCON_SetnRST(rstnum, RSTCON_nENABLE); #elif defined(CONFIG_MACH_S5P6818) if (NX_RSTCON_GetRST(rstnum)) return; NX_RSTCON_SetRST(rstnum, RSTCON_ASSERT); NX_RSTCON_SetRST(rstnum, RSTCON_NEGATE); #endif }
int board_late_init(void) { #if defined(CONFIG_SYS_MMC_BOOT_DEV) char boot[16]; sprintf(boot, "mmc dev %d", CONFIG_SYS_MMC_BOOT_DEV); run_command(boot, 0); #endif #if defined CONFIG_RECOVERY_BOOT if (RECOVERY_SIGNATURE == readl(SCR_RESET_SIG_READ)) { writel((-1UL), SCR_RESET_SIG_RESET); /* clear */ printf("RECOVERY BOOT\n"); bd_display_run(CONFIG_CMD_LOGO_WALLPAPERS, CFG_LCD_PRI_PWM_DUTYCYCLE, 1); run_command(CONFIG_CMD_RECOVERY_BOOT, 0); /* recovery boot */ } writel((-1UL), SCR_RESET_SIG_RESET); #endif /* CONFIG_RECOVERY_BOOT */ #if defined(CONFIG_BAT_CHECK) { int ret =0; int bat_check_skip = 0; // psw0523 for cts // bat_check_skip = 1; #if defined(CONFIG_DISPLAY_OUT) ret = power_battery_check(bat_check_skip, bd_display_run); #else ret = power_battery_check(bat_check_skip, NULL); #endif if(ret == 1) auto_update(UPDATE_KEY, UPDATE_CHECK_TIME); } #else /* CONFIG_BAT_CHECK */ // mipi reset NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3); NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3); NX_RSTCON_SetnRST(RESET_ID_MIPI, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_MIPI_DSI, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_MIPI_CSI, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_S, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_M, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_MIPI, RSTCON_nENABLE); NX_RSTCON_SetnRST(RESET_ID_MIPI_DSI, RSTCON_nENABLE); NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_S, RSTCON_nENABLE); NX_RSTCON_SetnRST(RESET_ID_MIPI_PHY_M, RSTCON_nENABLE); // ac97 reset NX_RSTCON_SetnRST(RESET_ID_AC97, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_AC97, RSTCON_nENABLE); // scaler reset NX_RSTCON_SetnRST(RESET_ID_SCALER, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_SCALER, RSTCON_nENABLE); // pdm reset NX_CLKGEN_SetClockPClkMode(CLOCKINDEX_OF_PDM_MODULE, NX_PCLKMODE_ALWAYS); // PCLK Always NX_RSTCON_SetnRST(RESET_ID_PDM, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_PDM, RSTCON_nENABLE); // mpegtsi reset NX_RSTCON_SetnRST(RESET_ID_MPEGTSI, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_MPEGTSI, RSTCON_nENABLE); // crypto reset NX_CLKGEN_SetClockPClkMode(CLOCKINDEX_OF_CRYPTO_MODULE, NX_PCLKMODE_ALWAYS); // PCLK Always NX_RSTCON_SetnRST(RESET_ID_CRYPTO, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_CRYPTO, RSTCON_nENABLE); // spi1 reset NX_RSTCON_SetnRST(RESET_ID_SSP1_P, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_SSP1, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_SSP1_P, RSTCON_nENABLE); NX_RSTCON_SetnRST(RESET_ID_SSP1, RSTCON_nENABLE); // spi2 reset NX_RSTCON_SetnRST(RESET_ID_SSP2_P, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_SSP2, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_SSP2_P, RSTCON_nENABLE); NX_RSTCON_SetnRST(RESET_ID_SSP2, RSTCON_nENABLE); // vip 0/1 reset NX_CLKGEN_SetClockBClkMode(CLOCKINDEX_OF_VIP0_MODULE, NX_BCLKMODE_DYNAMIC); NX_CLKGEN_SetClockDivisorEnable(CLOCKINDEX_OF_VIP0_MODULE, CTRUE); NX_RSTCON_SetnRST(RESET_ID_VIP0, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_VIP0, RSTCON_nENABLE); NX_CLKGEN_SetClockBClkMode(CLOCKINDEX_OF_VIP1_MODULE, NX_BCLKMODE_DYNAMIC); NX_CLKGEN_SetClockDivisorEnable(CLOCKINDEX_OF_VIP1_MODULE, CTRUE); NX_RSTCON_SetnRST(RESET_ID_VIP1, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESET_ID_VIP1, RSTCON_nENABLE); #if defined(CONFIG_DISPLAY_OUT) bd_display_run(CONFIG_CMD_LOGO_WALLPAPERS, CFG_LCD_PRI_PWM_DUTYCYCLE, 1); #endif #ifdef CONFIG_CMD_NET bd_eth_init(); #endif /* Temp check gpio to update */ auto_update(UPDATE_KEY, UPDATE_CHECK_TIME); #endif /* CONFIG_BAT_CHECK */ return 0; }
static int _hw_set(struct nxp_resc *me) { u32 sg_vfp, sg_vs, sg_vbp, sg_hfp, sg_hbp, sg_hs; u32 src_hsize, src_vsize, dst_hsize, dst_vsize, sg_hav, sg_vav; u32 src_crop_l, src_crop_r, src_crop_t, src_crop_b; u32 sg_hdelay, sg_hoffset, sg_s2in_vs; u32 delta_x, delta_y; u32 v_diff, h_diff; src_hsize = me->format[NXP_RESC_PAD_SINK].width; src_vsize = me->format[NXP_RESC_PAD_SINK].height; dst_hsize = me->format[NXP_RESC_PAD_SOURCE].width; dst_vsize = me->format[NXP_RESC_PAD_SOURCE].height; sg_hav = dst_hsize; sg_vav = dst_vsize; v_diff = src_vsize - dst_vsize; h_diff = src_hsize - dst_hsize; sg_vfp = 4 + v_diff/2;; sg_vs = 5; sg_vbp = 36 + v_diff/2; sg_hfp = 88 + h_diff/2; sg_hs = 44; sg_hbp = 148 + h_diff/2; src_crop_l = 0; src_crop_r = 0; src_crop_t = 0; src_crop_b = 0; delta_x = (src_hsize*FIXED_POINT+dst_hsize/2)/(dst_hsize); delta_y = (src_vsize*FIXED_POINT+dst_vsize/2)/(dst_vsize); sg_hdelay = 1; sg_hoffset = 0; sg_s2in_vs = 0; NX_RSTCON_SetnRST(RESETINDEX_OF_RESCONV_MODULE, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESETINDEX_OF_RESCONV_MODULE, RSTCON_nENABLE); NX_RESCONV_Initialize(); NX_RESCONV_SetBaseAddress(me->id, (U32)IO_ADDRESS(NX_RESCONV_GetPhysicalAddress(0))); NX_RESCONV_FIFO_Init(me->id, CTRUE); NX_RESCONV_FIFO_Init(me->id, CFALSE); NX_RESCONV_SetS2IN_VS(me->id, CFALSE); NX_RESCONV_FINIT(me->id); NX_RESCONV_INIT(me->id, src_hsize, src_vsize, src_crop_l, src_crop_r, src_crop_t, src_crop_b, dst_hsize, dst_vsize, FIXED_POINT, delta_x, delta_y, SOFT_V, SOFT_H, sg_vfp, sg_vbp, sg_vs, sg_vav, sg_hfp, sg_hbp, sg_hs, sg_hav, sg_s2in_vs, sg_hoffset, sg_hdelay); return 0; }
static int _hw_set_with_preset(struct nxp_resc *me) { u32 sg_vfp, sg_vs, sg_vbp, sg_hfp, sg_hbp, sg_hs; u32 src_hsize, src_vsize, dst_hsize, dst_vsize, sg_hav, sg_vav; u32 src_crop_l, src_crop_r, src_crop_t, src_crop_b; u32 sg_hdelay, sg_hoffset, sg_s2in_vs; u32 delta_x, delta_y; struct sync_preset *preset = me->preset; pr_debug("%s: entered\n", __func__); src_hsize = preset->mlc_resol.width; src_vsize = preset->mlc_resol.height; dst_hsize = preset->resc_sync_param.hact; dst_vsize = preset->resc_sync_param.vact; sg_hav = dst_hsize; sg_vav = dst_vsize; sg_vfp = preset->resc_sync_param.vfp; sg_vs = preset->resc_sync_param.vsw; sg_vbp = preset->resc_sync_param.vbp; sg_hfp = preset->resc_sync_param.hfp; sg_hs = preset->resc_sync_param.hsw; sg_hbp = preset->resc_sync_param.hbp; src_crop_l = 0; src_crop_r = 0; src_crop_t = 0; src_crop_b = 0; if (src_hsize >= dst_hsize) { // scale down pr_debug("%s: scale down\n", __func__); delta_x = (src_hsize*FIXED_POINT+dst_hsize/2)/(dst_hsize); delta_y = (src_vsize*FIXED_POINT+dst_vsize/2)/(dst_vsize); } else { // scale up pr_debug("%s: scale up\n", __func__); delta_x = (src_hsize*FIXED_POINT+dst_hsize/2)/(dst_hsize-1); delta_y = (src_vsize*FIXED_POINT+dst_vsize/2)/(dst_vsize-1); } sg_hdelay = preset->resc_sync_param.hdelay; sg_hoffset = preset->resc_sync_param.hoffset; sg_s2in_vs = 0; pr_debug("%s: sg_vfp %d, sg_vs %d, sg_vbp %d, sg_hfp %d, sg_hbp %d, sg_hs %d\n", __func__, sg_vfp, sg_vs, sg_vbp, sg_hfp, sg_hbp, sg_hs); pr_debug("%s: src_hsize %d, src_vsize %d, st_hsize %d, dst_vsize %d, sg_hav %d, sg_vav %d\n", __func__, src_hsize, src_vsize, dst_hsize, dst_vsize, sg_hav, sg_vav); pr_debug("%s: sg_hdelay %d, sg_hoffset %d, sg_s2in_vs %d\n", __func__, sg_hdelay, sg_hoffset, sg_s2in_vs); NX_RSTCON_SetnRST(RESETINDEX_OF_RESCONV_MODULE, RSTCON_nDISABLE); NX_RSTCON_SetnRST(RESETINDEX_OF_RESCONV_MODULE, RSTCON_nENABLE); NX_RESCONV_Initialize(); NX_RESCONV_SetBaseAddress(me->id, (U32)IO_ADDRESS(NX_RESCONV_GetPhysicalAddress(0))); NX_RESCONV_FIFO_Init(me->id, CTRUE); NX_RESCONV_FIFO_Init(me->id, CFALSE); NX_RESCONV_SetS2IN_VS(me->id, CFALSE); NX_RESCONV_FINIT(me->id); NX_RESCONV_INIT(me->id, src_hsize, src_vsize, src_crop_l, src_crop_r, src_crop_t, src_crop_b, dst_hsize, dst_vsize, FIXED_POINT, delta_x, delta_y, SOFT_V, SOFT_H, sg_vfp, sg_vbp, sg_vs, sg_vav, sg_hfp, sg_hbp, sg_hs, sg_hav, sg_s2in_vs, sg_hoffset, sg_hdelay); pr_debug("%s: exit\n", __func__); return 0; }