void titan_mailbox_irq(void)
{
int cpu = smp_processor_id();
unsigned long status;
switch (cpu) {
case 0:
status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
if (status & 0x2)
smp_call_function_interrupt();
if (status & 0x4)
scheduler_ipi();
break;
case 1:
status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
if (status & 0x2)
smp_call_function_interrupt();
if (status & 0x4)
scheduler_ipi();
break;
}
}
/*
* Send inter-processor interrupt
*/
static void yos_send_ipi_single(int cpu, unsigned int action)
{
/*
* Generate an INTMSG so that it can be sent over to the
* destination CPU. The INTMSG will put the STATUS bits
* based on the action desired. An alternative strategy
* is to write to the Interrupt Set register, read the
* Interrupt Status register and clear the Interrupt
* Clear register. The latter is preffered.
*/
switch (action) {
case SMP_RESCHEDULE_YOURSELF:
if (cpu == 1)
OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
else
OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
break;
case SMP_CALL_FUNCTION:
if (cpu == 1)
OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
else
OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
break;
}
}
void __init plat_mem_setup(void)
{
late_time_init = py_late_time_init;
/* Add memory regions */
add_memory_region(0x00000000, 0x10000000, BOOT_MEM_RAM);
#if 0 /* XXX Crash ... */
OCD_WRITE(RM9000x2_OCD_HTSC,
OCD_READ(RM9000x2_OCD_HTSC) | HYPERTRANSPORT_ENABLE);
/* Set the BAR. Shifted mode */
OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
#endif
}
asmlinkage void titan_mailbox_irq(struct pt_regs *regs)
{
int cpu = smp_processor_id();
unsigned long status;
if (cpu == 0) {
status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
}
if (cpu == 1) {
status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
}
if (status & 0x2)
smp_call_function_interrupt();
}
static void __init py_map_ocd(void)
{
ocd_base = (unsigned long) ioremap(OCD_BASE, OCD_SIZE);
if (!ocd_base)
panic("Mapping OCD failed - game over. Your score is 0.");
/* Kludge for PMON bug ... */
OCD_WRITE(0x0710, 0x0ffff029);
}
void titan_mailbox_irq(void)
{
int cpu = smp_processor_id();
unsigned long status;
switch (cpu) {
case 0:
status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
if (status & 0x2)
smp_call_function_interrupt();
<<<<<<< HEAD
if (status & 0x4)
scheduler_ipi();
=======
>>>>>>> 296c66da8a02d52243f45b80521febece5ed498a
break;
/*
* Handle hypertransport & SMP interrupts. The interrupt lines are scarce.
* For interprocessor interrupts, the best thing to do is to use the INTMSG
* register. We use the same external interrupt line, i.e. INTB3 and monitor
* another status bit
*/
static void ll_ht_smp_irq_handler(int irq)
{
u32 status = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
/* Ack all the bits that correspond to the interrupt sources */
if (status != 0)
OCD_WRITE(RM9000x2_OCD_INTP0STATUS4, IRQ_ACK_BITS);
status = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
if (status != 0)
OCD_WRITE(RM9000x2_OCD_INTP1STATUS4, IRQ_ACK_BITS);
#ifdef CONFIG_HT_LEVEL_TRIGGER
/*
* Level Trigger Mode only. Send the HT EOI message back to the source.
*/
switch (status) {
case 0x1000000:
OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
break;
case 0x2000000:
OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
break;
case 0x4000000:
OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
break;
case 0x8000000:
OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
break;
case 0x0000001:
/* PLX */
OCD_WRITE(RM9000x2_OCD_HTEOI, 0x20);
OCD_WRITE(IRQ_CLEAR_REG, IRQ_ACK_BITS);
break;
case 0xf000000:
OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
break;
}
#endif /* CONFIG_HT_LEVEL_TRIGGER */
do_IRQ(irq);
}
