static int
fm801_pci_attach(device_t dev)
{
struct ac97_info *codec = 0;
struct fm801_info *fm801;
int i;
int mapped = 0;
char status[SND_STATUSLEN];
fm801 = malloc(sizeof(*fm801), M_DEVBUF, M_WAITOK | M_ZERO);
fm801->type = pci_get_devid(dev);
pci_enable_busmaster(dev);
for (i = 0; (mapped == 0) && (i < PCI_MAXMAPS_0); i++) {
fm801->regid = PCIR_BAR(i);
fm801->regtype = SYS_RES_MEMORY;
fm801->reg = bus_alloc_resource_any(dev, fm801->regtype,
&fm801->regid, RF_ACTIVE);
if(!fm801->reg)
{
fm801->regtype = SYS_RES_IOPORT;
fm801->reg = bus_alloc_resource_any(dev,
fm801->regtype,
&fm801->regid,
RF_ACTIVE);
}
if(fm801->reg) {
fm801->st = rman_get_bustag(fm801->reg);
fm801->sh = rman_get_bushandle(fm801->reg);
mapped++;
}
}
if (mapped == 0) {
device_printf(dev, "unable to map register space\n");
goto oops;
}
fm801->bufsz = pcm_getbuffersize(dev, 4096, FM801_DEFAULT_BUFSZ, 65536);
fm801_init(fm801);
codec = AC97_CREATE(dev, fm801, fm801_ac97);
if (codec == NULL) goto oops;
if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto oops;
fm801->irqid = 0;
fm801->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &fm801->irqid,
RF_ACTIVE | RF_SHAREABLE);
if (!fm801->irq || snd_setup_intr(dev, fm801->irq, 0, fm801_intr, fm801, &fm801->ih)) {
device_printf(dev, "unable to map interrupt\n");
goto oops;
}
if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
/*boundary*/0,
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL, /*filterarg*/NULL,
/*maxsize*/fm801->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
/*flags*/0, /*lockfunc*/busdma_lock_mutex,
/*lockarg*/&Giant, &fm801->parent_dmat) != 0) {
device_printf(dev, "unable to create dma tag\n");
goto oops;
}
snprintf(status, 64, "at %s 0x%lx irq %ld %s",
(fm801->regtype == SYS_RES_IOPORT)? "io" : "memory",
rman_get_start(fm801->reg), rman_get_start(fm801->irq),PCM_KLDSTRING(snd_fm801));
#define FM801_MAXPLAYCH 1
if (pcm_register(dev, fm801, FM801_MAXPLAYCH, 1)) goto oops;
pcm_addchan(dev, PCMDIR_PLAY, &fm801ch_class, fm801);
pcm_addchan(dev, PCMDIR_REC, &fm801ch_class, fm801);
pcm_setstatus(dev, status);
fm801->radio = device_add_child(dev, "radio", -1);
bus_generic_attach(dev);
return 0;
oops:
if (codec) ac97_destroy(codec);
if (fm801->reg) bus_release_resource(dev, fm801->regtype, fm801->regid, fm801->reg);
if (fm801->ih) bus_teardown_intr(dev, fm801->irq, fm801->ih);
if (fm801->irq) bus_release_resource(dev, SYS_RES_IRQ, fm801->irqid, fm801->irq);
if (fm801->parent_dmat) bus_dma_tag_destroy(fm801->parent_dmat);
free(fm801, M_DEVBUF);
return ENXIO;
}
static int
hdspe_alloc_resources(struct sc_info *sc)
{
/* Allocate resource. */
sc->csid = PCIR_BAR(0);
sc->cs = bus_alloc_resource(sc->dev, SYS_RES_MEMORY,
&sc->csid, 0, ~0, 1, RF_ACTIVE);
if (!sc->cs) {
device_printf(sc->dev, "Unable to map SYS_RES_MEMORY.\n");
return (ENXIO);
}
sc->cst = rman_get_bustag(sc->cs);
sc->csh = rman_get_bushandle(sc->cs);
/* Allocate interrupt resource. */
sc->irqid = 0;
sc->irq = bus_alloc_resource(sc->dev, SYS_RES_IRQ, &sc->irqid,
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
if (!sc->irq ||
bus_setup_intr(sc->dev, sc->irq, INTR_MPSAFE | INTR_TYPE_AV,
NULL, hdspe_intr, sc, &sc->ih)) {
device_printf(sc->dev, "Unable to alloc interrupt resource.\n");
return (ENXIO);
}
/* Allocate DMA resources. */
if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(sc->dev),
/*alignment*/4,
/*boundary*/0,
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
/*highaddr*/BUS_SPACE_MAXADDR,
/*filter*/NULL,
/*filterarg*/NULL,
/*maxsize*/2 * HDSPE_DMASEGSIZE,
/*nsegments*/2,
/*maxsegsz*/HDSPE_DMASEGSIZE,
/*flags*/0,
/*lockfunc*/busdma_lock_mutex,
/*lockarg*/&Giant,
/*dmatag*/&sc->dmat) != 0) {
device_printf(sc->dev, "Unable to create dma tag.\n");
return (ENXIO);
}
sc->bufsize = HDSPE_DMASEGSIZE;
/* pbuf (play buffer). */
if (bus_dmamem_alloc(sc->dmat, (void **)&sc->pbuf,
BUS_DMA_NOWAIT, &sc->pmap)) {
device_printf(sc->dev, "Can't alloc pbuf.\n");
return (ENXIO);
}
if (bus_dmamap_load(sc->dmat, sc->pmap, sc->pbuf, sc->bufsize,
hdspe_dmapsetmap, sc, 0)) {
device_printf(sc->dev, "Can't load pbuf.\n");
return (ENXIO);
}
/* rbuf (rec buffer). */
if (bus_dmamem_alloc(sc->dmat, (void **)&sc->rbuf,
BUS_DMA_NOWAIT, &sc->rmap)) {
device_printf(sc->dev, "Can't alloc rbuf.\n");
return (ENXIO);
}
if (bus_dmamap_load(sc->dmat, sc->rmap, sc->rbuf, sc->bufsize,
hdspe_dmapsetmap, sc, 0)) {
device_printf(sc->dev, "Can't load rbuf.\n");
return (ENXIO);
}
bzero(sc->pbuf, sc->bufsize);
bzero(sc->rbuf, sc->bufsize);
return (0);
}
static int
amr_pci_attach(device_t dev)
{
struct amr_softc *sc;
struct amr_ident *id;
int rid, rtype, error;
u_int32_t command;
debug_called(1);
/*
* Initialise softc.
*/
sc = device_get_softc(dev);
bzero(sc, sizeof(*sc));
sc->amr_dev = dev;
/* assume failure is 'not configured' */
error = ENXIO;
/*
* Determine board type.
*/
if ((id = amr_find_ident(dev)) == NULL)
return (ENXIO);
command = pci_read_config(dev, PCIR_COMMAND, 1);
if (id->flags & AMR_ID_QUARTZ) {
/*
* Make sure we are going to be able to talk to this board.
*/
if ((command & PCIM_CMD_MEMEN) == 0) {
device_printf(dev, "memory window not available\n");
return (ENXIO);
}
sc->amr_type |= AMR_TYPE_QUARTZ;
} else {
/*
* Make sure we are going to be able to talk to this board.
*/
if ((command & PCIM_CMD_PORTEN) == 0) {
device_printf(dev, "I/O window not available\n");
return (ENXIO);
}
}
if ((amr_force_sg32 == 0) && (id->flags & AMR_ID_DO_SG64) &&
(sizeof(vm_paddr_t) > 4)) {
device_printf(dev, "Using 64-bit DMA\n");
sc->amr_type |= AMR_TYPE_SG64;
}
/* force the busmaster enable bit on */
if (!(command & PCIM_CMD_BUSMASTEREN)) {
device_printf(dev, "busmaster bit not set, enabling\n");
command |= PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, command, 2);
}
/*
* Allocate the PCI register window.
*/
rid = PCIR_BAR(0);
rtype = AMR_IS_QUARTZ(sc) ? SYS_RES_MEMORY : SYS_RES_IOPORT;
sc->amr_reg = bus_alloc_resource_any(dev, rtype, &rid, RF_ACTIVE);
if (sc->amr_reg == NULL) {
device_printf(sc->amr_dev, "can't allocate register window\n");
goto out;
}
sc->amr_btag = rman_get_bustag(sc->amr_reg);
sc->amr_bhandle = rman_get_bushandle(sc->amr_reg);
/*
* Allocate and connect our interrupt.
*/
rid = 0;
sc->amr_irq = bus_alloc_resource_any(sc->amr_dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->amr_irq == NULL) {
device_printf(sc->amr_dev, "can't allocate interrupt\n");
goto out;
}
if (bus_setup_intr(sc->amr_dev, sc->amr_irq,
INTR_MPSAFE, amr_pci_intr,
sc, &sc->amr_intr, NULL)) {
device_printf(sc->amr_dev, "can't set up interrupt\n");
goto out;
}
debug(2, "interrupt attached");
/* assume failure is 'out of memory' */
error = ENOMEM;
/*
* Allocate the parent bus DMA tag appropriate for PCI.
*/
if (bus_dma_tag_create(NULL, /* parent */
1, 0, /* alignment,boundary */
AMR_IS_SG64(sc) ?
BUS_SPACE_MAXADDR :
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
MAXBSIZE, AMR_NSEG, /* maxsize, nsegments */
BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
0, /* flags */
&sc->amr_parent_dmat)) {
device_printf(dev, "can't allocate parent DMA tag\n");
goto out;
}
/*
* Create DMA tag for mapping buffers into controller-addressable space.
*/
if (bus_dma_tag_create(sc->amr_parent_dmat, /* parent */
1, 0, /* alignment,boundary */
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
MAXBSIZE, AMR_NSEG, /* maxsize, nsegments */
MAXBSIZE, /* maxsegsize */
0, /* flags */
&sc->amr_buffer_dmat)) {
device_printf(sc->amr_dev, "can't allocate buffer DMA tag\n");
goto out;
}
if (bus_dma_tag_create(sc->amr_parent_dmat, /* parent */
1, 0, /* alignment,boundary */
BUS_SPACE_MAXADDR, /* lowaddr */
BUS_SPACE_MAXADDR, /* highaddr */
NULL, NULL, /* filter, filterarg */
MAXBSIZE, AMR_NSEG, /* maxsize, nsegments */
MAXBSIZE, /* maxsegsize */
0, /* flags */
&sc->amr_buffer64_dmat)) {
device_printf(sc->amr_dev, "can't allocate buffer DMA tag\n");
goto out;
}
debug(2, "dma tag done");
/*
* Allocate and set up mailbox in a bus-visible fashion.
*/
lockinit(&sc->amr_list_lock, "AMR List Lock", 0, LK_CANRECURSE);
lockinit(&sc->amr_hw_lock, "AMR HW Lock", 0, LK_CANRECURSE);
if ((error = amr_setup_mbox(sc)) != 0)
goto out;
debug(2, "mailbox setup");
/*
* Build the scatter/gather buffers.
*/
if ((error = amr_sglist_map(sc)) != 0)
goto out;
debug(2, "s/g list mapped");
if ((error = amr_ccb_map(sc)) != 0)
goto out;
debug(2, "ccb mapped");
/*
* Do bus-independant initialisation, bring controller online.
*/
error = amr_attach(sc);
out:
if (error)
amr_pci_free(sc);
return(error);
}
int
pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, uint64_t hostbase,
enum pcibar_type type, uint64_t size)
{
int i, error;
uint64_t *baseptr, limit, addr, mask, lobits, bar;
struct inout_port iop;
assert(idx >= 0 && idx <= PCI_BARMAX);
if ((size & (size - 1)) != 0)
size = 1UL << flsl(size); /* round up to a power of 2 */
switch (type) {
case PCIBAR_NONE:
baseptr = NULL;
addr = mask = lobits = 0;
break;
case PCIBAR_IO:
if (hostbase && pci_slotinfo[pdi->pi_slot].si_legacy) {
assert(hostbase < PCI_EMUL_IOBASE);
baseptr = &hostbase;
} else {
baseptr = &pci_emul_iobase;
}
limit = PCI_EMUL_IOLIMIT;
mask = PCIM_BAR_IO_BASE;
lobits = PCIM_BAR_IO_SPACE;
break;
case PCIBAR_MEM64:
/*
* XXX
* Some drivers do not work well if the 64-bit BAR is allocated
* above 4GB. Allow for this by allocating small requests under
* 4GB unless then allocation size is larger than some arbitrary
* number (32MB currently).
*/
if (size > 32 * 1024 * 1024) {
/*
* XXX special case for device requiring peer-peer DMA
*/
if (size == 0x100000000UL)
baseptr = &hostbase;
else
baseptr = &pci_emul_membase64;
limit = PCI_EMUL_MEMLIMIT64;
mask = PCIM_BAR_MEM_BASE;
lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 |
PCIM_BAR_MEM_PREFETCH;
break;
}
/* fallthrough */
case PCIBAR_MEM32:
baseptr = &pci_emul_membase32;
limit = PCI_EMUL_MEMLIMIT32;
mask = PCIM_BAR_MEM_BASE;
lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
break;
default:
printf("pci_emul_alloc_base: invalid bar type %d\n", type);
assert(0);
}
if (baseptr != NULL) {
error = pci_emul_alloc_resource(baseptr, limit, size, &addr);
if (error != 0)
return (error);
}
pdi->pi_bar[idx].type = type;
pdi->pi_bar[idx].addr = addr;
pdi->pi_bar[idx].size = size;
/* Initialize the BAR register in config space */
bar = (addr & mask) | lobits;
pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar);
if (type == PCIBAR_MEM64) {
assert(idx + 1 <= PCI_BARMAX);
pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64;
pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32);
}
/*
* PCI attach: scan Open Firmware child nodes, and attach these as children
* of the macio bus
*/
static int
macio_attach(device_t dev)
{
struct macio_softc *sc;
struct macio_devinfo *dinfo;
phandle_t root;
phandle_t child;
phandle_t subchild;
device_t cdev;
u_int reg[3];
char compat[32];
int error, quirks;
sc = device_get_softc(dev);
root = sc->sc_node = ofw_bus_get_node(dev);
/*
* Locate the device node and it's base address
*/
if (OF_getprop(root, "assigned-addresses",
reg, sizeof(reg)) < (ssize_t)sizeof(reg)) {
return (ENXIO);
}
/* Used later to see if we have to enable the I2S part. */
OF_getprop(root, "compatible", compat, sizeof(compat));
sc->sc_base = reg[2];
sc->sc_size = MACIO_REG_SIZE;
sc->sc_memrid = PCIR_BAR(0);
sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&sc->sc_memrid, RF_ACTIVE);
sc->sc_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_mem_rman.rm_descr = "MacIO Device Memory";
error = rman_init(&sc->sc_mem_rman);
if (error) {
device_printf(dev, "rman_init() failed. error = %d\n", error);
return (error);
}
error = rman_manage_region(&sc->sc_mem_rman, 0, sc->sc_size);
if (error) {
device_printf(dev,
"rman_manage_region() failed. error = %d\n", error);
return (error);
}
/*
* Iterate through the sub-devices
*/
for (child = OF_child(root); child != 0; child = OF_peer(child)) {
dinfo = malloc(sizeof(*dinfo), M_MACIO, M_WAITOK | M_ZERO);
if (ofw_bus_gen_setup_devinfo(&dinfo->mdi_obdinfo, child) !=
0) {
free(dinfo, M_MACIO);
continue;
}
quirks = macio_get_quirks(dinfo->mdi_obdinfo.obd_name);
if ((quirks & MACIO_QUIRK_IGNORE) != 0) {
ofw_bus_gen_destroy_devinfo(&dinfo->mdi_obdinfo);
free(dinfo, M_MACIO);
continue;
}
resource_list_init(&dinfo->mdi_resources);
dinfo->mdi_ninterrupts = 0;
macio_add_intr(child, dinfo);
if ((quirks & MACIO_QUIRK_USE_CHILD_REG) != 0)
macio_add_reg(OF_child(child), dinfo);
else
macio_add_reg(child, dinfo);
if ((quirks & MACIO_QUIRK_CHILD_HAS_INTR) != 0)
for (subchild = OF_child(child); subchild != 0;
subchild = OF_peer(subchild))
macio_add_intr(subchild, dinfo);
cdev = device_add_child(dev, NULL, -1);
if (cdev == NULL) {
device_printf(dev, "<%s>: device_add_child failed\n",
dinfo->mdi_obdinfo.obd_name);
resource_list_free(&dinfo->mdi_resources);
ofw_bus_gen_destroy_devinfo(&dinfo->mdi_obdinfo);
free(dinfo, M_MACIO);
continue;
}
device_set_ivars(cdev, dinfo);
/* Set FCRs to enable some devices */
if (sc->sc_memr == NULL)
continue;
if (strcmp(ofw_bus_get_name(cdev), "bmac") == 0 ||
strcmp(ofw_bus_get_compat(cdev), "bmac+") == 0) {
uint32_t fcr;
fcr = bus_read_4(sc->sc_memr, HEATHROW_FCR);
fcr |= FCR_ENET_ENABLE & ~FCR_ENET_RESET;
bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr);
DELAY(50000);
fcr |= FCR_ENET_RESET;
bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr);
DELAY(50000);
fcr &= ~FCR_ENET_RESET;
bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr);
DELAY(50000);
bus_write_4(sc->sc_memr, HEATHROW_FCR, fcr);
}
/*
* Make sure the I2S0 and the I2S0_CLK are enabled.
* On certain G5's they are not.
*/
if ((strcmp(ofw_bus_get_name(cdev), "i2s") == 0) &&
(strcmp(compat, "K2-Keylargo") == 0)) {
uint32_t fcr1;
fcr1 = bus_read_4(sc->sc_memr, KEYLARGO_FCR1);
fcr1 |= FCR1_I2S0_CLK_ENABLE | FCR1_I2S0_ENABLE;
bus_write_4(sc->sc_memr, KEYLARGO_FCR1, fcr1);
}
}
return (bus_generic_attach(dev));
}
static int
thunder_pem_attach(device_t dev)
{
devclass_t pci_class;
device_t parent;
struct thunder_pem_softc *sc;
int error;
int rid;
int tuple;
uint64_t base, size;
struct rman *rman;
sc = device_get_softc(dev);
sc->dev = dev;
/* Allocate memory for resource */
pci_class = devclass_find("pci");
parent = device_get_parent(dev);
if (device_get_devclass(parent) == pci_class)
rid = PCIR_BAR(0);
else
rid = RID_PEM_SPACE;
sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
&rid, RF_ACTIVE);
if (sc->reg == NULL) {
device_printf(dev, "Failed to allocate resource\n");
return (ENXIO);
}
sc->reg_bst = rman_get_bustag(sc->reg);
sc->reg_bsh = rman_get_bushandle(sc->reg);
/* Map SLI, do it only once */
if (!sli0_s2m_regx_base) {
bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC,
SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base);
}
if (!sli1_s2m_regx_base) {
bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC +
SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0,
&sli1_s2m_regx_base);
}
if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) {
device_printf(dev,
"bus_space_map failed to map slix_s2m_regx_base\n");
goto fail;
}
/* Identify PEM */
if (thunder_pem_identify(dev) != 0)
goto fail;
/* Initialize rman and allocate regions */
sc->mem_rman.rm_type = RMAN_ARRAY;
sc->mem_rman.rm_descr = "PEM PCIe Memory";
error = rman_init(&sc->mem_rman);
if (error != 0) {
device_printf(dev, "memory rman_init() failed. error = %d\n",
error);
goto fail;
}
sc->io_rman.rm_type = RMAN_ARRAY;
sc->io_rman.rm_descr = "PEM PCIe IO";
error = rman_init(&sc->io_rman);
if (error != 0) {
device_printf(dev, "IO rman_init() failed. error = %d\n",
error);
goto fail_mem;
}
/*
* We ignore the values that may have been provided in FDT
* and configure ranges according to the below formula
* for all types of devices. This is because some DTBs provided
* by EFI do not have proper ranges property or don't have them
* at all.
*/
/* Fill memory window */
sc->ranges[0].pci_base = PCI_MEMORY_BASE;
sc->ranges[0].size = PCI_MEMORY_SIZE;
sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
sc->ranges[0].pci_base;
sc->ranges[0].flags = SYS_RES_MEMORY;
/* Fill IO window */
sc->ranges[1].pci_base = PCI_IO_BASE;
sc->ranges[1].size = PCI_IO_SIZE;
sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
sc->ranges[1].pci_base;
sc->ranges[1].flags = SYS_RES_IOPORT;
for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) {
base = sc->ranges[tuple].pci_base;
size = sc->ranges[tuple].size;
if (size == 0)
continue; /* empty range element */
rman = thunder_pem_rman(sc, sc->ranges[tuple].flags);
if (rman != NULL)
error = rman_manage_region(rman, base,
base + size - 1);
else
error = EINVAL;
if (error) {
device_printf(dev,
"rman_manage_region() failed. error = %d\n", error);
rman_fini(&sc->mem_rman);
return (error);
}
if (bootverbose) {
device_printf(dev,
"\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx, Flags:0x%jx\n",
sc->ranges[tuple].pci_base,
sc->ranges[tuple].phys_base,
sc->ranges[tuple].size,
sc->ranges[tuple].flags);
}
}
if (thunder_pem_init(sc)) {
device_printf(dev, "Failure during PEM init\n");
goto fail_io;
}
device_add_child(dev, "pci", -1);
return (bus_generic_attach(dev));
fail_io:
rman_fini(&sc->io_rman);
fail_mem:
rman_fini(&sc->mem_rman);
fail:
bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
return (ENXIO);
}
static int
ata_ali_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
struct ali_sata_resources *res;
int i, rid;
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
switch (ctlr->chip->cfg2) {
case ALI_SATA:
ctlr->channels = ctlr->chip->cfg1;
ctlr->ch_attach = ata_ali_sata_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
/* AHCI mode is correctly supported only on the ALi 5288. */
if ((ctlr->chip->chipid == ATA_ALI_5288) &&
(ata_ahci_chipinit(dev) != ENXIO))
return 0;
/* Allocate resources for later use by channel attach routines. */
res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);
for (i = 0; i < 4; i++) {
rid = PCIR_BAR(i);
res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
RF_ACTIVE);
if (res->bars[i] == NULL) {
device_printf(dev, "Failed to allocate BAR %d\n", i);
for (i--; i >=0; i--)
bus_release_resource(dev, SYS_RES_IOPORT,
PCIR_BAR(i), res->bars[i]);
free(res, M_ATAPCI);
return ENXIO;
}
}
ctlr->chipset_data = res;
break;
case ALI_NEW:
/* use device interrupt as byte count end */
pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
/* enable cable detection and UDMA support on revisions < 0xc7 */
if (ctlr->chip->chiprev < 0xc7)
pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) |
0x09, 1);
/* enable ATAPI UDMA mode (even if we are going to do PIO) */
pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) |
(ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1);
/* only chips with revision > 0xc4 can do 48bit DMA */
if (ctlr->chip->chiprev <= 0xc4)
device_printf(dev,
"using PIO transfers above 137GB as workaround for "
"48bit DMA access bug, expect reduced performance\n");
ctlr->ch_attach = ata_ali_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->reset = ata_ali_reset;
ctlr->setmode = ata_ali_setmode;
break;
case ALI_OLD:
/* deactivate the ATAPI FIFO and enable ATAPI UDMA */
pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
ctlr->setmode = ata_ali_setmode;
break;
}
return 0;
}
int
ata_sii_chipinit(device_t dev)
{
struct ata_pci_controller *ctlr = device_get_softc(dev);
if (ata_setup_interrupt(dev, ata_generic_intr))
return ENXIO;
switch (ctlr->chip->cfg1) {
case SII_PRBIO:
ctlr->r_type1 = SYS_RES_MEMORY;
ctlr->r_rid1 = PCIR_BAR(0);
if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
&ctlr->r_rid1, RF_ACTIVE)))
return ENXIO;
ctlr->r_rid2 = PCIR_BAR(2);
ctlr->r_type2 = SYS_RES_MEMORY;
if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
&ctlr->r_rid2, RF_ACTIVE))){
bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
return ENXIO;
}
#ifdef __sparc64__
if (!bus_space_map(rman_get_bustag(ctlr->r_res2),
rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2),
BUS_SPACE_MAP_LINEAR, NULL)) {
bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,
ctlr->r_res1);
bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,
ctlr->r_res2);
return (ENXIO);
}
#endif
ctlr->ch_attach = ata_siiprb_ch_attach;
ctlr->ch_detach = ata_siiprb_ch_detach;
ctlr->reset = ata_siiprb_reset;
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
/* reset controller */
ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
DELAY(10000);
ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
break;
case SII_MEMIO:
ctlr->r_type2 = SYS_RES_MEMORY;
ctlr->r_rid2 = PCIR_BAR(5);
if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
&ctlr->r_rid2, RF_ACTIVE))){
if (ctlr->chip->chipid != ATA_SII0680 ||
(pci_read_config(dev, 0x8a, 1) & 1))
return ENXIO;
}
if (ctlr->chip->cfg2 & SII_SETCLK) {
if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
pci_write_config(dev, 0x8a,
(pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
device_printf(dev, "%s could not set ATA133 clock\n",
ctlr->chip->text);
}
/* if we have 4 channels enable the second set */
if (ctlr->chip->cfg2 & SII_4CH) {
ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
ctlr->channels = 4;
}
/* dont block interrupts from any channel */
pci_write_config(dev, 0x48,
(pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
/* enable PCI interrupt as BIOS might not */
pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
if (ctlr->r_res2) {
ctlr->ch_attach = ata_sii_ch_attach;
ctlr->ch_detach = ata_sii_ch_detach;
}
if (ctlr->chip->max_dma >= ATA_SA150) {
ctlr->reset = ata_sii_reset;
ctlr->setmode = ata_sata_setmode;
ctlr->getrev = ata_sata_getrev;
}
else
ctlr->setmode = ata_sii_setmode;
break;
default:
if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
device_printf(dev, "HW has secondary channel disabled\n");
ctlr->channels = 1;
}
/* enable interrupt as BIOS might not */
pci_write_config(dev, 0x71, 0x01, 1);
ctlr->ch_attach = ata_cmd_ch_attach;
ctlr->ch_detach = ata_pci_ch_detach;
ctlr->setmode = ata_cmd_setmode;
break;
}
return 0;
}
{
int i;
for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) {
if (pci_get_devid(dev) == gem_pci_devlist[i].gpd_devid) {
device_set_desc(dev, gem_pci_devlist[i].gpd_desc);
return (BUS_PROBE_DEFAULT);
}
}
return (ENXIO);
}
static struct resource_spec gem_pci_res_spec[] = {
{ SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* GEM_RES_INTR */
{ SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* GEM_RES_BANK1 */
{ -1, 0 }
};
#define GEM_SHARED_PINS "shared-pins"
#define GEM_SHARED_PINS_SERDES "serdes"
static int
gem_pci_attach(device_t dev)
{
struct gem_softc *sc;
int i;
#if defined(__powerpc__) || defined(__sparc64__)
char buf[sizeof(GEM_SHARED_PINS)];
#else
int j;
static int
ral_pci_attach(device_t dev)
{
struct ral_pci_softc *psc = device_get_softc(dev);
struct rt2560_softc *sc = &psc->u.sc_rt2560;
int count, error, rid;
pci_enable_busmaster(dev);
switch (pci_get_device(dev)) {
case 0x0201:
psc->sc_opns = &ral_rt2560_opns;
break;
case 0x0301:
case 0x0302:
case 0x0401:
psc->sc_opns = &ral_rt2661_opns;
break;
default:
psc->sc_opns = &ral_rt2860_opns;
break;
}
rid = PCIR_BAR(0);
psc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (psc->mem == NULL) {
device_printf(dev, "could not allocate memory resource\n");
return ENXIO;
}
sc->sc_st = rman_get_bustag(psc->mem);
sc->sc_sh = rman_get_bushandle(psc->mem);
sc->sc_invalid = 1;
rid = 0;
if (ral_msi_disable == 0) {
count = 1;
if (pci_alloc_msi(dev, &count) == 0)
rid = 1;
}
psc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE |
(rid != 0 ? 0 : RF_SHAREABLE));
if (psc->irq == NULL) {
device_printf(dev, "could not allocate interrupt resource\n");
pci_release_msi(dev);
bus_release_resource(dev, SYS_RES_MEMORY,
rman_get_rid(psc->mem), psc->mem);
return ENXIO;
}
error = (*psc->sc_opns->attach)(dev, pci_get_device(dev));
if (error != 0) {
(void)ral_pci_detach(dev);
return error;
}
/*
* Hook our interrupt after all initialization is complete.
*/
error = bus_setup_intr(dev, psc->irq, INTR_TYPE_NET | INTR_MPSAFE,
NULL, psc->sc_opns->intr, psc, &psc->sc_ih);
if (error != 0) {
device_printf(dev, "could not set up interrupt\n");
(void)ral_pci_detach(dev);
return error;
}
sc->sc_invalid = 0;
return 0;
}