void USART0_SPI_DMA_Transfer(uint8_t* Txbuffer ,uint8_t* RxBuffer,uint32_t xFer_Size){
volatile PdcaChannel *pdca_channel ;
/* Disable IRQ from PDCA Channel 0 at core Level */
NVIC_DisableIRQ(PDCA_0_IRQn);
/*Allocate PDCA channel 0 to USART RX -> Memory transfer */
pdca_channel = &(PDCA->PDCA_CHANNEL[0]);
pdca_channel->PDCA_CR = PDCA_CR_TDIS;
pdca_channel->PDCA_PSR = 0;
pdca_channel->PDCA_MAR = RxBuffer;
pdca_channel->PDCA_TCR = xFer_Size;
pdca_channel->PDCA_MR = PDCA_MR_SIZE(0);
pdca_channel->PDCA_IER = PDCA_IER_RCZ;
pdca_channel->PDCA_CR = PDCA_CR_TEN;
/*Allocate PDCA channel 1 to Memory -> USART TX transfer */
pdca_channel = &(PDCA->PDCA_CHANNEL[1]);
pdca_channel->PDCA_CR = PDCA_CR_TDIS;
pdca_channel->PDCA_PSR = 18;
pdca_channel->PDCA_MAR = TxBuffer;
pdca_channel->PDCA_TCR = xFer_Size;
pdca_channel->PDCA_MR = PDCA_MR_SIZE(0);
pdca_channel->PDCA_CR = PDCA_CR_TEN;
// - Reset end of transfer flag
end_of_spi_transfer = 0;
/* Enable IRQ from PDCA Channel 0 at core Level */
NVIC_EnableIRQ(PDCA_0_IRQn);
/* Wait until transfer finished */
while(!end_of_spi_transfer);
}
/**
* \brief Write PDCA channel configuration to hardware
*
* \param pdca_ch_number PDCA channel
* \param cfg Pointer to a PDCA channel config
*/
void pdca_channel_set_config(pdca_channel_num_t pdca_ch_number,
const pdca_channel_config_t *cfg)
{
/* Get the correct channel pointer */
volatile PdcaChannel *pdca_channel =
pdca_channel_get_handler(pdca_ch_number);
pdca_channel->PDCA_MAR = (uint32_t) cfg->addr;
pdca_channel->PDCA_TCR = cfg->size;
pdca_channel->PDCA_PSR = cfg->pid;
pdca_channel->PDCA_MARR = (uint32_t) cfg->r_addr;
pdca_channel->PDCA_TCRR = cfg->r_size;
if (cfg->etrig == true) {
pdca_channel->PDCA_MR |= PDCA_MR_ETRIG;
} else {
pdca_channel->PDCA_MR &= ~PDCA_MR_ETRIG;
}
if (cfg->ring == true) {
pdca_channel->PDCA_MR |= PDCA_MR_RING;
} else {
pdca_channel->PDCA_MR &= ~PDCA_MR_RING;
}
pdca_channel->PDCA_MR |= PDCA_MR_SIZE(cfg->transfer_size);
pdca_channel->PDCA_CR |= PDCA_CR_ECLR;
}
