u32
ODM_GetBBReg(
PDM_ODM_T pDM_Odm,
u32 RegAddr,
u32 BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
struct rtw_adapter * Adapter = pDM_Odm->Adapter;
return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
#endif
}
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_MP))
PADAPTER Adapter = pDM_Odm->Adapter;
return PHY_QueryBBReg(Adapter, RegAddr, BitMask);
#endif
}
static void odm_RX_HWAntDivInit(struct odm_dm_struct *dm_odm)
{
struct adapter *adapter = dm_odm->Adapter;
u32 value32;
if (*(dm_odm->mp_mode) == 1) {
dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /* disable HW AntDiv */
PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* 1:CG, 0:CS */
return;
}
ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_RX_HWAntDivInit()\n"));
/* MAC Setting */
value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
/* Pin Settings */
PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1); /* Regb2c[22]=1'b0 disable CS/CG switch */
PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
/* OFDM Settings */
PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
/* CCK Settings */
PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */
PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201); /* antenna mapping table */
}
unsigned int DMDP_PHY_QueryBBReg(unsigned int phy, unsigned int RegAddr, unsigned int BitMask)
{
//printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return -1;
}
return PHY_QueryBBReg((struct rtl8192cd_priv *)if_priv[phy], RegAddr, BitMask);
}
s32 MPT_InitializeAdapter(struct adapter *pAdapter, u8 Channel)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
s32 rtStatus = _SUCCESS;
struct mpt_context *pMptCtx = &pAdapter->mppriv.MptCtx;
struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv;
/* HW Initialization for 8190 MPT. */
/* SW Initialization for 8190 MP. */
pMptCtx->bMptDrvUnload = false;
pMptCtx->bMassProdTest = false;
pMptCtx->bMptIndexEven = true; /* default gain index is -6.0db */
pMptCtx->h2cReqNum = 0x0;
/* Init mpt event. */
/* init for BT MP */
pMptCtx->bMptWorkItemInProgress = false;
pMptCtx->CurrMptAct = NULL;
/* */
/* Don't accept any packets */
rtw_write32(pAdapter, REG_RCR, 0);
PHY_IQCalibrate(pAdapter, false);
dm_CheckTXPowerTracking(&pHalData->odmpriv); /* trigger thermal meter */
PHY_LCCalibrate(pAdapter);
pMptCtx->backup0xc50 = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
pMptCtx->backup0xc58 = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
pMptCtx->backup0xc30 = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
pMptCtx->backup0x52_RF_A = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
pMptCtx->backup0x52_RF_B = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
/* set ant to wifi side in mp mode */
rtw_write16(pAdapter, 0x870, 0x300);
rtw_write16(pAdapter, 0x860, 0x110);
if (pAdapter->registrypriv.mp_mode == 1)
pmlmepriv->fw_state = WIFI_MP_STATE;
return rtStatus;
}
static bool
odm_GetATCStatus(
IN void * pDM_VOID
)
{
bool ATCStatus;
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
ATCStatus = (bool)PHY_QueryBBReg(pDM_Odm->Adapter, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm));
return ATCStatus;
}
u4Byte
PHY_QueryRFReg_8814(
IN HAL_PADAPTER Adapter,
IN u4Byte eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
{
// The phy Query function have bug in 8812 & 8881, must follow the rules as below
// 1. No matter path A or B, we have to assign the addr on 0x8b0[7:0]
// 2. Before Query RF reg, we must turn off CCA
// 3. delay 10us after set addr
// 4. If SI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB
// 5. If PI mode, read value from 0xd08[19:0] on PathA, 0xd48[19:0] on PathB
HAL_PADAPTER priv = Adapter;
unsigned long flags;
u4Byte Original_Value, Readback_Value, BitShift;
u4Byte temp_CCA;
#if CFG_HAL_DISABLE_BB_RF
return 0;
#endif //CFG_HAL_DISABLE_BB_RF
HAL_SAVE_INT_AND_CLI(flags);
u4Byte DataAndAddr = 0;
u4Byte Direct_Addr;
RegAddr &= 0xff;
switch(eRFPath){
case RF88XX_PATH_A:
Direct_Addr = 0x2800+RegAddr*4;
break;
case RF88XX_PATH_B:
Direct_Addr = 0x2c00+RegAddr*4;
break;
case RF88XX_PATH_C:
Direct_Addr = 0x3800+RegAddr*4;
break;
case RF88XX_PATH_D:
Direct_Addr = 0x3c00+RegAddr*4;
break;
}
BitMask &= bRFRegOffsetMask;
Readback_Value = PHY_QueryBBReg(Adapter, Direct_Addr, BitMask);
HAL_RESTORE_INT(flags);
return (Readback_Value);
}
void ODM_RF_Saving(void *pDM_VOID, u8 bForceInNormal)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
u8 Rssi_Up_bound = 30;
u8 Rssi_Low_bound = 25;
if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
Rssi_Up_bound = 50;
Rssi_Low_bound = 45;
}
if (pDM_PSTable->initialize == 0) {
pDM_PSTable->Reg874 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0x874, bMaskDWord)&0x1CC000)>>14;
pDM_PSTable->RegC70 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xc70, bMaskDWord)&BIT3)>>3;
pDM_PSTable->Reg85C = (PHY_QueryBBReg(pDM_Odm->Adapter, 0x85c, bMaskDWord)&0xFF000000)>>24;
pDM_PSTable->RegA74 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xa74, bMaskDWord)&0xF000)>>12;
/* Reg818 = PHY_QueryBBReg(padapter, 0x818, bMaskDWord); */
pDM_PSTable->initialize = 1;
}
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask);
#elif(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
return PHY_QueryMacReg(pDM_Odm->Adapter, RegAddr, BitMask);
#endif
}
unsigned short RTL_R16SU(struct rtl8190_priv *priv,unsigned int indx)
{
unsigned int data=0;
unsigned short data2=0;
struct usb_device *udev = priv->udev;
int status;
#ifdef DEBUG_CHIHHSING
//printk("----->(%s, %d)\n", __FUNCTION__, __LINE__);
#endif
if (IS_DRV_CLOSE(priv))
{
#ifdef CONFIG_RTK_VOIP
// rock: reduce debug message
#else
printk("device unlink - skip %s\n",__FUNCTION__);
#endif
return 0;
}
#if 1
if (indx>=0x800&&indx<=0xfff)
{ // read BB register
data2=PHY_QueryBBReg(priv, indx, bMaskLWord);
}
else
#endif
{
status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
RTL8192_REQ_GET_REGS, RTL8192_REQT_READ,
(indx&0xffff), 0, &data, 2, HZ / 2);
data = *(unsigned int *)(((unsigned int)&data) | 0xa0000000);
if (status < 0)
{
printk("read_nic_word TimeOut! status:%x addr=0x%x\n", status,indx);
}
#ifdef __LITTLE_ENDIAN
data2 = data & 0xffff; // jimmy porting DVR platform problem.
#else
data2 = data >> 16; //tysu: fixed usb can't read offset 2 , 2bytes data bug
#endif
data2=le16_to_cpu(data2);
}
#ifdef DEBUG_CHIHHSING
printk("(REG_DUMP): read_nic_word : idx=0x%x return=0x%x\n", indx, data2);
#endif
return data2;
}
unsigned int RTL_R32SU(struct rtl8190_priv *priv, unsigned int indx)
{
unsigned int data=0;
struct usb_device *udev = (struct usb_device *)priv->udev;
int status;
#ifdef DEBUG_CHIHHSING
//printk("----->(%s, %d udev=%x)\n", __FUNCTION__, __LINE__, (u32)udev);
#endif
if (IS_DRV_CLOSE(priv))
{
#ifdef CONFIG_RTK_VOIP
// rock: reduce debug message
#else
printk("device unlink - skip %s\n",__FUNCTION__);
#endif
return 0;
}
#if 1
if (indx>=0x800&&indx<=0xfff)
{ // read BB register
data=PHY_QueryBBReg(priv, indx, bMaskDWord);
}
else
#endif
{
status = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
RTL8192_REQ_GET_REGS, RTL8192_REQT_READ,
(indx&0xffff), 0, &data, 4, HZ / 2);
data = *(unsigned int *)(((unsigned int)&data) | 0xa0000000);
if (status < 0)
{
printk("read_nic_dword TimeOut! status:%d indx=0x%x\n", status,indx);
}
data=le32_to_cpu(data);
}
#ifdef DEBUG_CHIHHSING
printk("(REG_DUMP): read_nic_dword : idx=0x%x return=0x%x\n", indx, data);
#endif
return data;
}
static void odm_TRX_HWAntDivInit(struct odm_dm_struct *dm_odm)
{
struct adapter *adapter = dm_odm->Adapter;
u32 value32;
if (*(dm_odm->mp_mode) == 1) {
dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
PHY_SetBBReg(adapter, ODM_REG_IGI_A_11N, BIT7, 0); /* disable HW AntDiv */
PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, 0); /* Default RX (0/1) */
return;
}
ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_TRX_HWAntDivInit()\n"));
/* MAC Setting */
value32 = PHY_QueryBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
PHY_SetBBReg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
/* Pin Settings */
PHY_SetBBReg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
PHY_SetBBReg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
PHY_SetBBReg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
/* OFDM Settings */
PHY_SetBBReg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord, 0x000000a0);
/* CCK Settings */
PHY_SetBBReg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1); /* Fix CCK PHY status report issue */
PHY_SetBBReg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1); /* CCK complete HW AntDiv within 64 samples */
/* Tx Settings */
PHY_SetBBReg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0); /* Reg80c[21]=1'b0 from TX Reg */
ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
/* antenna mapping table */
if (!dm_odm->bIsMPChip) { /* testchip */
PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */
PHY_SetBBReg(adapter, ODM_REG_RX_DEFUALT_A_11N, BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */
} else { /* MPchip */
PHY_SetBBReg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord, 0x0201); /* Reg914=3'b010, Reg915=3'b001 */
}
}
static int
phy_RF6052_Config_ParaFile_8192E(
IN PADAPTER Adapter
)
{
u8 eRFPath;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
BB_REGISTER_DEFINITION_T *pPhyReg;
static char sz8192ERadioAFile[] = RTL8192E_PHY_RADIO_A;
static char sz8192ERadioBFile[] = RTL8192E_PHY_RADIO_B;
static char sz8192ETxPwrTrack[] = RTL8192E_TXPWR_TRACK;
char *pszRadioAFile = NULL, *pszRadioBFile = NULL, *pszTxPwrTrack = NULL;
u32 u4RegValue,MaskforPhySet = 0;;
pszRadioAFile = sz8192ERadioAFile;
pszRadioBFile = sz8192ERadioBFile;
pszTxPwrTrack = sz8192ETxPwrTrack;
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
pPhyReg = &pHalData->PHYRegDef[eRFPath];
switch(eRFPath)
{
case RF_PATH_A:
case RF_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV);
break;
case RF_PATH_B :
case RF_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV<<16);
break;
default:
u4RegValue = 0;
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe|MaskforPhySet, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo|MaskforPhySet, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2|MaskforPhySet, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2|MaskforPhySet, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF_PATH_A:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, eRFPath) == _FAIL)
#endif
{
#ifdef CONFIG_EMBEDDED_FWIMG
if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath))
rtStatus = _FAIL;
#endif
}
break;
case RF_PATH_B:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, eRFPath) == _FAIL)
#endif
{
#ifdef CONFIG_EMBEDDED_FWIMG
if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath))
rtStatus = _FAIL;
#endif
}
break;
default:
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF_PATH_A:
case RF_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV, u4RegValue);
break;
case RF_PATH_B :
case RF_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV<<16, u4RegValue);
break;
default:
break;
}
if(rtStatus != _SUCCESS){
DBG_871X("%s():Radio[%d] Fail!!", __FUNCTION__, eRFPath);
goto phy_RF6052_Config_ParaFile_Fail;
}
}
//3 -----------------------------------------------------------------
//3 Configuration of Tx Power Tracking
//3 -----------------------------------------------------------------
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrack) == _FAIL)
#endif
{
#ifdef CONFIG_EMBEDDED_FWIMG
ODM_ConfigRFWithTxPwrTrackHeaderFile(&pHalData->odmpriv);
#endif
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile_8192E()\n"));
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_IQK_8192C(
IN PADAPTER pAdapter,
IN BOOLEAN configPathB
)
{
u4Byte regEAC, regE94, regE9C, regEA4;
u1Byte result = 0x00;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n"));
//path-A IQK setting
RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
if(pAdapter->interfaceIndex == 0)
{
PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
}
else
{
PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c22);
PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c22);
}
PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102);
PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 :
IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502);
//path-B IQK setting
if(configPathB)
{
PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22);
PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22);
PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102);
if(IS_HARDWARE_TYPE_8192D(pAdapter))
PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160206);
else
PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202);
}
//LO calibration setting
RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n"));
if(IS_HARDWARE_TYPE_8192D(pAdapter))
PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
else
PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1);
//One shot, path A LOK & IQK
RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
// delay x ms
RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME));
PlatformStallExecution(IQK_DELAY_TIME*1000);
// Check failed
regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94));
regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C));
regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4));
if(!(regEAC & BIT28) &&
(((regE94 & 0x03FF0000)>>16) != 0x142) &&
(((regE9C & 0x03FF0000)>>16) != 0x42) )
result |= 0x01;
else //if Tx not OK, ignore Rx
return result;
static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
{
u32 u4RegValue = 0;
u8 eRFPath;
struct bb_register_def *pPhyReg;
int rtStatus = _SUCCESS;
struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
static char sz8723RadioAFile[] = RTL8723B_PHY_RADIO_A;
static char sz8723RadioBFile[] = RTL8723B_PHY_RADIO_B;
static s8 sz8723BTxPwrTrackFile[] = RTL8723B_TXPWR_TRACK;
char *pszRadioAFile, *pszRadioBFile, *pszTxPwrTrackFile;
pszRadioAFile = sz8723RadioAFile;
pszRadioBFile = sz8723RadioBFile;
pszTxPwrTrackFile = sz8723BTxPwrTrackFile;
/* 3----------------------------------------------------------------- */
/* 3 <2> Initialize RF */
/* 3----------------------------------------------------------------- */
/* for (eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) */
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch (eRFPath) {
case RF_PATH_A:
case RF_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF_PATH_B:
case RF_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
udelay(1);/* PlatformStallExecution(1); */
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
udelay(1);/* PlatformStallExecution(1); */
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
udelay(1);/* PlatformStallExecution(1); */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
udelay(1);/* PlatformStallExecution(1); */
/*----Initialize RF fom connfiguration file----*/
switch (eRFPath) {
case RF_PATH_A:
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile,
eRFPath) == _FAIL) {
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath))
rtStatus = _FAIL;
}
break;
case RF_PATH_B:
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile,
eRFPath) == _FAIL) {
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath))
rtStatus = _FAIL;
}
break;
case RF_PATH_C:
break;
case RF_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch (eRFPath) {
case RF_PATH_A:
case RF_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF_PATH_B:
case RF_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if (rtStatus != _SUCCESS) {
/* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */
goto phy_RF6052_Config_ParaFile_Fail;
}
}
/* 3 ----------------------------------------------------------------- */
/* 3 Configuration of Tx Power Tracking */
/* 3 ----------------------------------------------------------------- */
if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrackFile) ==
_FAIL) {
ODM_ConfigRFWithTxPwrTrackHeaderFile(&pHalData->odmpriv);
}
/* RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); */
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
static bool rtl8192_radio_on_off_checking(struct net_device *dev)
{
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
u8 u1Tmp = 0;
u8 gpio;
if (priv->pwrdown) {
u1Tmp = read_nic_byte(dev, 0x06);
gpio = u1Tmp & BIT6;
} else
#ifdef CONFIG_BT_COEXIST
if (pHalData->bt_coexist.BluetoothCoexist) {
if (pHalData->bt_coexist.BT_CoexistType == BT_2Wire) {
PlatformEFIOWrite1Byte(pAdapter, MAC_PINMUX_CFG, 0xa);
u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IO_SEL);
delay_us(100);
u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IN);
RTPRINT(FPWR, PWRHW, ("GPIO_IN=%02x\n", u1Tmp));
retval = (u1Tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? eRfOn : eRfOff;
} else if ((pHalData->bt_coexist.BT_CoexistType == BT_ISSC_3Wire) ||
(pHalData->bt_coexist.BT_CoexistType == BT_Accel) ||
(pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4)) {
u4tmp = PHY_QueryBBReg(pAdapter, 0x87c, bMaskDWord);
if ((u4tmp & BIT17) != 0) {
PHY_SetBBReg(pAdapter, 0x87c, bMaskDWord, u4tmp & ~BIT17);
delay_us(50);
RTPRINT(FBT, BT_RFPoll, ("BT write 0x87c (~BIT17) = 0x%x\n", u4tmp &~BIT17));
}
u4tmp = PHY_QueryBBReg(pAdapter, 0x8e0, bMaskDWord);
RTPRINT(FBT, BT_RFPoll, ("BT read 0x8e0 (BIT24)= 0x%x\n", u4tmp));
retval = (u4tmp & BIT24) ? eRfOn : eRfOff;
RTPRINT(FBT, BT_RFPoll, ("BT check RF state to %s\n", (retval==eRfOn)? "ON":"OFF"));
}
} else
#endif
{
write_nic_byte(dev, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
u1Tmp = read_nic_byte(dev, GPIO_IO_SEL);
u1Tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
write_nic_byte(dev, GPIO_IO_SEL, u1Tmp);
mdelay(10);
u1Tmp = read_nic_byte(dev, GPIO_IN);
gpio = u1Tmp & HAL_8192S_HW_GPIO_OFF_BIT;
}
#ifdef DEBUG_RFKILL
{
static u8 gpio_test;
printk("%s: gpio = %x\n", __FUNCTION__, gpio);
if(gpio_test % 5 == 0) {
gpio = 0;
} else {
gpio = 1;
}
printk("%s: gpio_test = %d, gpio = %x\n", __FUNCTION__, gpio_test++ % 20, gpio);
}
#endif
return gpio;
}
static int
phy_RF6052_Config_ParaFile(
IN PADAPTER Adapter
)
{
u32 u4RegValue;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
static char sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A;
static char sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B;
#ifdef CONFIG_USB_HCI
static char sz88CRadioAFile_mCard[] = RTL8188C_PHY_RADIO_A_mCard;
static char sz88CRadioBFile_mCard[] = RTL8188C_PHY_RADIO_B_mCard;
static char sz88CRadioAFile_HP[] = RTL8188C_PHY_RADIO_A_HP;
#endif
static char sz92CRadioAFile[] = RTL8192C_PHY_RADIO_A;
static char sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B;
static char sz8723RadioAFile[] = RTL8723_PHY_RADIO_A;
static char sz8723RadioBFile[] = RTL8723_PHY_RADIO_B;
char *pszRadioAFile, *pszRadioBFile;
if(IS_HARDWARE_TYPE_8192C(Adapter))
{
if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's
{
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz92CRadioAFile;
pszRadioBFile = sz92CRadioBFile;
}
else
{
rtStatus = _FAIL;
return rtStatus;
}
}
else
{
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz88CRadioAFile;
pszRadioBFile = sz88CRadioBFile;
#ifdef CONFIG_USB_HCI
if( BOARD_MINICARD == pHalData->BoardType)
{
pszRadioAFile = sz88CRadioAFile_mCard;
pszRadioBFile = sz88CRadioBFile_mCard;
}
else if( BOARD_USB_High_PA == pHalData->BoardType)
{
pszRadioAFile = sz88CRadioAFile_HP;
}
#endif
}
else
{
rtStatus = _FAIL;
return rtStatus;
}
}
}
else if(IS_HARDWARE_TYPE_8723(Adapter))
{
pszRadioAFile = sz8723RadioAFile;
pszRadioBFile = sz8723RadioBFile;
}
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF90_PATH_B :
case RF90_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF90_PATH_A:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus= rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath);
#else
rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF90_RADIO_PATH_E)eRFPath);
#endif
break;
case RF90_PATH_B:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus = rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath);
#else
rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF90_RADIO_PATH_E)eRFPath);
#endif
break;
case RF90_PATH_C:
break;
case RF90_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF90_PATH_B :
case RF90_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(rtStatus != _SUCCESS){
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
goto phy_RF6052_Config_ParaFile_Fail;
}
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
static int
phy_RF6052_Config_ParaFile(
IN PADAPTER Adapter
)
{
u32 u4RegValue=0;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
u8 *pszRadioAFile = NULL, *pszRadioBFile = NULL;
static s8 sz92DRadioAFile[] = RTL8192D_PHY_RADIO_A;
static s8 sz92DRadioBFile[] = RTL8192D_PHY_RADIO_B;
static s8 sz92DRadioAintPAFile[] = RTL8192D_PHY_RADIO_A_intPA;
static s8 sz92DRadioBintPAFile[] = RTL8192D_PHY_RADIO_B_intPA;
BOOLEAN bMac1NeedInitRadioAFirst = _FALSE,bMac0NeedInitRadioBFirst = _FALSE;
BOOLEAN bNeedPowerDownRadioA = _FALSE,bNeedPowerDownRadioB = _FALSE;
BOOLEAN bTrueBPath = _FALSE;//vivi added this for read parameter from header, 20100908
u32 MaskforPhySet = 0; //For 92d PHY cross access, 88c must set value 0.
pszRadioAFile = sz92DRadioAFile;
pszRadioBFile = sz92DRadioBFile;
if(pHalData->InternalPA5G[0])
pszRadioAFile = sz92DRadioAintPAFile;
if(pHalData->InternalPA5G[1])
pszRadioBFile = sz92DRadioBintPAFile;
//DMDP,MAC0 on G band,MAC1 on A band.
if(pHalData->MacPhyMode92D==DUALMAC_DUALPHY)
{
if(pHalData->CurrentBandType92D == BAND_ON_2_4G && pHalData->interfaceIndex == 0)
{
//MAC0 Need PHY1 load radio_b.txt . Driver use DBI to write.
if(rtl8192d_PHY_EnableAnotherPHY(Adapter, _TRUE))
{
pHalData->NumTotalRFPath = 2;
bMac0NeedInitRadioBFirst = _TRUE;
}
else
{
// We think if MAC1 is ON,then radio_a.txt and radio_b.txt has been load.
return rtStatus;
}
}
else if(pHalData->CurrentBandType92D == BAND_ON_5G && pHalData->interfaceIndex == 1)
{
//MAC1 Need PHY0 load radio_a.txt . Driver use DBI to write.
if(rtl8192d_PHY_EnableAnotherPHY(Adapter, _FALSE))
{
pHalData->NumTotalRFPath = 2;
bMac1NeedInitRadioAFirst = _TRUE;
}
else
{
// We think if MAC0 is ON,then radio_a.txt and radio_b.txt has been load.
return rtStatus;
}
}
else if(pHalData->interfaceIndex == 1)
{
// MAC0 enabled, only init radia B.
pszRadioAFile = pszRadioBFile;
bTrueBPath = _TRUE; //vivi added this for read parameter from header, 20100909
}
}
//RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_RF6052_Config_ParaFile() Radio_A:%s\n",pszRadioAFile));
//RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_RF6052_Config_ParaFile() Radio_B:%s\n",pszRadioBFile));
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
if (bMac1NeedInitRadioAFirst) //Mac1 use PHY0 write
{
if (eRFPath == RF_PATH_A)
{
bNeedPowerDownRadioA = _TRUE;
MaskforPhySet = MAC1_ACCESS_PHY0;
}
else if (eRFPath == RF_PATH_B)
{
MaskforPhySet = 0;
bMac1NeedInitRadioAFirst = _FALSE;
eRFPath = RF_PATH_A;
bTrueBPath = _TRUE;
pszRadioAFile = pszRadioBFile;
pHalData->NumTotalRFPath = 1;
}
}
else if (bMac0NeedInitRadioBFirst) //Mac0 use PHY1 write
{
if (eRFPath == RF_PATH_A)
{
MaskforPhySet = 0;
}
if (eRFPath == RF_PATH_B)
{
MaskforPhySet = MAC0_ACCESS_PHY1;
bMac0NeedInitRadioBFirst = _FALSE;
bNeedPowerDownRadioB = _TRUE;
eRFPath = RF_PATH_A;
bTrueBPath = _TRUE;
pszRadioAFile = pszRadioBFile;
pHalData->NumTotalRFPath = 1;
}
}
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF_PATH_A:
case RF_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV);
break;
case RF_PATH_B :
case RF_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe|MaskforPhySet, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo|MaskforPhySet, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2|MaskforPhySet, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2|MaskforPhySet, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF_PATH_A:
#ifdef CONFIG_EMBEDDED_FWIMG
//vivi added this for read parameter from header, 20100908
if(bTrueBPath == _TRUE)
rtStatus = rtl8192d_PHY_ConfigRFWithHeaderFile(Adapter,radiob_txt|MaskforPhySet, (RF_RADIO_PATH_E)eRFPath);
else
rtStatus = rtl8192d_PHY_ConfigRFWithHeaderFile(Adapter,radioa_txt|MaskforPhySet, (RF_RADIO_PATH_E)eRFPath);
#else
rtStatus = rtl8192d_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath);
#endif
break;
case RF_PATH_B:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus = rtl8192d_PHY_ConfigRFWithHeaderFile(Adapter,radiob_txt, (RF_RADIO_PATH_E)eRFPath);
#else
rtStatus = rtl8192d_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath);
#endif
break;
case RF_PATH_C:
break;
case RF_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF_PATH_A:
case RF_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV, u4RegValue);
break;
case RF_PATH_B :
case RF_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs|MaskforPhySet, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(rtStatus != _SUCCESS){
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
goto phy_RF6052_Config_ParaFile_Fail;
}
}
if (bNeedPowerDownRadioA)
{
// check MAC0 enable or not again now, if enabled, not power down radio A.
rtl8192d_PHY_PowerDownAnotherPHY(Adapter, _FALSE);
}
else if (bNeedPowerDownRadioB)
{
// check MAC1 enable or not again now, if enabled, not power down radio B.
rtl8192d_PHY_PowerDownAnotherPHY(Adapter, _TRUE);
}
for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
#if MP_DRIVER == 1
PHY_SetRFReg(Adapter, eRFPath, RF_RXRF_A3, bRFRegOffsetMask, 0xff456);
#endif
pdmpriv->RegRF3C[eRFPath] = PHY_QueryRFReg(Adapter, eRFPath, RF_RXRF_A3, bRFRegOffsetMask);
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
static int phy_RF6052_Config_ParaFile(struct adapter *Adapter)
{
struct bb_reg_def *pPhyReg;
struct hal_data_8188e *pHalData = GET_HAL_DATA(Adapter);
u32 u4RegValue = 0;
u8 eRFPath;
int rtStatus = _SUCCESS;
/* 3----------------------------------------------------------------- */
/* 3 <2> Initialize RF */
/* 3----------------------------------------------------------------- */
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch (eRFPath) {
case RF_PATH_A:
case RF_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF_PATH_B:
case RF_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);/* PlatformStallExecution(1); */
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
rtw_udelay_os(1);/* PlatformStallExecution(1); */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
rtw_udelay_os(1);/* PlatformStallExecution(1); */
/*----Initialize RF fom connfiguration file----*/
switch (eRFPath) {
case RF_PATH_A:
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath))
rtStatus = _FAIL;
break;
case RF_PATH_B:
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, (enum rf_radio_path)eRFPath, (enum rf_radio_path)eRFPath))
rtStatus = _FAIL;
break;
case RF_PATH_C:
break;
case RF_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch (eRFPath) {
case RF_PATH_A:
case RF_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF_PATH_B:
case RF_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if (rtStatus != _SUCCESS)
goto phy_RF6052_Config_ParaFile_Fail;
}
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
static int
phy_RF6052_Config_ParaFile(
IN PADAPTER Adapter
)
{
u32 u4RegValue = 0;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
static char sz8188RadioAFile[] = RTL8188F_PHY_RADIO_A;
static char sz8188RadioBFile[] = RTL8188F_PHY_RADIO_B;
static s1Byte sz8188FTxPwrTrackFile[] = RTL8188F_TXPWR_TRACK;
char *pszRadioAFile, *pszRadioBFile, *pszTxPwrTrackFile;
pszRadioAFile = sz8188RadioAFile;
pszRadioBFile = sz8188RadioBFile;
pszTxPwrTrackFile = sz8188FTxPwrTrackFile;
/*3//----------------------------------------------------------------- */
/*3// <2> Initialize RF */
/*3//----------------------------------------------------------------- */
/*for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) */
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch (eRFPath) {
case RF_PATH_A:
case RF_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF_PATH_B :
case RF_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1);
rtw_udelay_os(1);/*PlatformStallExecution(1); */
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);/*PlatformStallExecution(1); */
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
rtw_udelay_os(1);/*PlatformStallExecution(1); */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
rtw_udelay_os(1);/*PlatformStallExecution(1); */
/*----Initialize RF fom connfiguration file----*/
switch (eRFPath) {
case RF_PATH_A:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, eRFPath) == _FAIL)
#endif
{
#ifdef CONFIG_EMBEDDED_FWIMG
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath))
rtStatus = _FAIL;
#endif
}
break;
case RF_PATH_B:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, eRFPath) == _FAIL)
#endif
{
#ifdef CONFIG_EMBEDDED_FWIMG
if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath))
rtStatus = _FAIL;
#endif
}
break;
case RF_PATH_C:
break;
case RF_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch (eRFPath) {
case RF_PATH_A:
case RF_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF_PATH_B :
case RF_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue);
break;
}
if (rtStatus != _SUCCESS) {
/*RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */
goto phy_RF6052_Config_ParaFile_Fail;
}
}
/*3 ----------------------------------------------------------------- */
/*3 Configuration of Tx Power Tracking */
/*3 ----------------------------------------------------------------- */
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrackFile) == _FAIL)
#endif
{
#ifdef CONFIG_EMBEDDED_FWIMG
ODM_ConfigRFWithTxPwrTrackHeaderFile(&pHalData->odmpriv);
#endif
}
/*RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); */
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
static int phy_RF6052_Config_ParaFile(struct rtw_adapter *Adapter)
{
u32 u4RegValue = 0;
u8 eRFPath;
struct bb_reg_define *pPhyReg;
int rtStatus = _SUCCESS;
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
/* 3----------------------------------------------------------------- */
/* 3 <2> Initialize RF */
/* 3----------------------------------------------------------------- */
for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch (eRFPath) {
case RF_PATH_A:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF_PATH_B:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
udelay(1);/* PlatformStallExecution(1); */
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
udelay(1);/* PlatformStallExecution(1); */
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */
udelay(1);/* PlatformStallExecution(1); */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */
udelay(1);/* PlatformStallExecution(1); */
/*----Initialize RF fom connfiguration file----*/
switch (eRFPath) {
case RF_PATH_A:
ODM_ReadAndConfig_RadioA_1T_8723A(&pHalData->odmpriv);
break;
case RF_PATH_B:
break;
}
/*----Restore RFENV control type----*/;
switch (eRFPath) {
case RF_PATH_A:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF_PATH_B:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if (rtStatus != _SUCCESS) {
/* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */
goto phy_RF6052_Config_ParaFile_Fail;
}
}
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
static s16 odm_InbandNoise_Monitor_NSeries(
PDM_ODM_T pDM_Odm,
u8 bPauseDIG,
u8 IGIValue,
u32 max_time
)
{
u32 tmp4b;
u8 max_rf_path = 0, rf_path;
u8 reg_c50, reg_c58, valid_done = 0;
struct noise_level noise_data;
u32 start = 0, func_start = 0, func_end = 0;
func_start = jiffies;
pDM_Odm->noise_level.noise_all = 0;
if ((pDM_Odm->RFType == ODM_1T2R) || (pDM_Odm->RFType == ODM_2T2R))
max_rf_path = 2;
else
max_rf_path = 1;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() ==>\n"));
memset(&noise_data, 0, sizeof(struct noise_level));
/* */
/* Step 1. Disable DIG && Set initial gain. */
/* */
if (bPauseDIG)
odm_PauseDIG(pDM_Odm, ODM_PAUSE_DIG, IGIValue);
/* */
/* Step 2. Disable all power save for read registers */
/* */
/* dcmd_DebugControlPowerSave(padapter, PSDisable); */
/* */
/* Step 3. Get noise power level */
/* */
start = jiffies;
while (1) {
/* Stop updating idle time pwer report (for driver read) */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 1);
/* Read Noise Floor Report */
tmp4b = PHY_QueryBBReg(pDM_Odm->Adapter, 0x8f8, bMaskDWord);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b));
/* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XAAGCCore1, bMaskByte0, TestInitialGain); */
/* if (max_rf_path == 2) */
/* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBAGCCore1, bMaskByte0, TestInitialGain); */
/* update idle time pwer report per 5us */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_TxGainStage, BIT25, 0);
noise_data.value[ODM_RF_PATH_A] = (u8)(tmp4b&0xff);
noise_data.value[ODM_RF_PATH_B] = (u8)((tmp4b&0xff00)>>8);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B]));
for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
noise_data.sval[rf_path] = (s8)noise_data.value[rf_path];
noise_data.sval[rf_path] /= 2;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("sval_a = %d, sval_b = %d\n",
noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B]));
/* mdelay(10); */
/* msleep(10); */
for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
if ((noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min)) {
noise_data.valid_cnt[rf_path]++;
noise_data.sum[rf_path] += noise_data.sval[rf_path];
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RF_Path:%d Valid sval = %d\n", rf_path, noise_data.sval[rf_path]));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", noise_data.sum[rf_path]));
if (noise_data.valid_cnt[rf_path] == ValidCnt) {
valid_done++;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, RF_Path:%d , sum = %d\n", rf_path, noise_data.sum[rf_path]));
}
}
}
/* printk("####### valid_done:%d #############\n", valid_done); */
if ((valid_done == max_rf_path) || (jiffies_to_msecs(jiffies - start) > max_time)) {
for (rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) {
/* printk("%s PATH_%d - sum = %d, valid_cnt = %d\n", __func__, rf_path, noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); */
if (noise_data.valid_cnt[rf_path])
noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path];
else
noise_data.sum[rf_path] = 0;
}
break;
}
}
reg_c50 = (s32)PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XAAGCCore1, bMaskByte0);
reg_c50 &= ~BIT7;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", rOFDM0_XAAGCCore1, reg_c50, reg_c50));
pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = -110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A];
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A];
if (max_rf_path == 2) {
reg_c58 = (s32)PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBAGCCore1, bMaskByte0);
reg_c58 &= ~BIT7;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", rOFDM0_XBAGCCore1, reg_c58, reg_c58));
pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = -110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B];
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B];
}
pDM_Odm->noise_level.noise_all /= max_rf_path;
ODM_RT_TRACE(
pDM_Odm,
ODM_COMP_COMMON,
ODM_DBG_LOUD,
(
"noise_a = %d, noise_b = %d\n",
pDM_Odm->noise_level.noise[ODM_RF_PATH_A],
pDM_Odm->noise_level.noise[ODM_RF_PATH_B]
)
);
/* */
/* Step 4. Recover the Dig */
/* */
if (bPauseDIG)
odm_PauseDIG(pDM_Odm, ODM_RESUME_DIG, IGIValue);
func_end = jiffies_to_msecs(jiffies - func_start);
/* printk("%s noise_a = %d, noise_b = %d noise_all:%d (%d ms)\n", __func__, */
/* pDM_Odm->noise_level.noise[ODM_RF_PATH_A], */
/* pDM_Odm->noise_level.noise[ODM_RF_PATH_B], */
/* pDM_Odm->noise_level.noise_all, func_end); */
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n"));
return pDM_Odm->noise_level.noise_all;
}
RT_STATUS
phy_RF6052_Config_ParaFile(
struct net_device* dev
)
{
struct r8192_priv *priv = rtllib_priv(dev);
u32 u4RegValue = 0;
u8 eRFPath;
RT_STATUS rtStatus = RT_STATUS_SUCCESS;
BB_REGISTER_DEFINITION_T *pPhyReg;
for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
{
pPhyReg = &priv->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = PHY_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF90_PATH_B :
case RF90_PATH_D:
u4RegValue = PHY_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
udelay(1);
/*----Set RF_ENV output high----*/
PHY_SetBBReg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
udelay(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);
udelay(1);
PHY_SetBBReg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);
udelay(1);
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF90_PATH_A:
#if RTL8190_Download_Firmware_From_Header
rtStatus= (PHY_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE;
#else
rtStatus = (PHY_ConfigRFWithParaFile(dev, szRadioAFile, (RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE;
#endif
break;
case RF90_PATH_B:
#if RTL8190_Download_Firmware_From_Header
rtStatus= (PHY_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE;
#else
rtStatus = (PHY_ConfigRFWithParaFile(dev, szRadioBFile, (RF90_RADIO_PATH_E)eRFPath) == true)?RT_STATUS_SUCCESS:RT_STATUS_FAILURE;
#endif
break;
case RF90_PATH_C:
break;
case RF90_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
PHY_SetBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF90_PATH_B :
case RF90_PATH_D:
PHY_SetBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(rtStatus != RT_STATUS_SUCCESS){
RT_TRACE(COMP_INIT, "phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
goto phy_RF6052_Config_ParaFile_Fail;
}
}
RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n");
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
int
phy_RF6052_Config_ParaFile(
IN PADAPTER Adapter
)
{
u32 u4RegValue;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
static char sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A;
static char sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B;
static char sz92CRadioAFile[] = RTL8192C_PHY_RADIO_A;
static char sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B;
static char sz88CTestRadioAFile[] = RTL8188C_PHY_RADIO_A;
static char sz88CTestRadioBFile[] = RTL8188C_PHY_RADIO_B;
static char sz92CTestRadioAFile[] = RTL8192C_PHY_RADIO_A;
static char sz92CTestRadioBFile[] = RTL8192C_PHY_RADIO_B;
static char sz92DRadioAFile[] = RTL8192D_PHY_RADIO_A;
static char sz92DRadioBFile[] = RTL8192D_PHY_RADIO_B;
static char sz92DTestRadioAFile[] = RTL8192D_PHY_RADIO_A;
static char sz92DTestRadioBFile[] = RTL8192D_PHY_RADIO_B;
u8 *pszRadioAFile, *pszRadioBFile;
u8 u1bTmp;
BOOLEAN bMac1NeedInitRadioAFirst = _FALSE;
BOOLEAN bNeedPowerDownRadioA = _FALSE;
// 92D RF config zhiyuan 2010/04/07
// Single phy mode: use radio_a radio_b config path_A path_B seperately by MAC0, and MAC1 needn't configure RF;
// Dual PHY mode:MAC0 use radio_a config 1st phy path_A, MAC1 use radio_b config 2nd PHY path_A.
if(IS_HARDWARE_TYPE_8192D(pHalData)){
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz92DRadioAFile;
pszRadioBFile = sz92DRadioBFile;
if(pHalData->interfaceIndex==1)
{
if(pHalData->MacPhyMode92D==DUALMAC_DUALPHY)
pszRadioAFile = sz92DRadioBFile;
else
return rtStatus;
}
}
else
{
pszRadioAFile = sz92DTestRadioAFile;
pszRadioBFile = sz92DTestRadioBFile;
if(pHalData->interfaceIndex==1)
{
//
// when 92D test chip dual mac dual phy mode, if enable MAC1 first, before init RF radio B,
// also init RF radio A, and then let radio A go to power down mode.
// Note: normal chip need do this or not will be considerred later.
//
if(pHalData->MacPhyMode92D==DUALMAC_DUALPHY)
{
u1bTmp = read8(Adapter, REG_MAC0);
if (!(u1bTmp&MAC0_ON))
{
// MAC0 not enabled, also init radio A before init radio B.
// Enable BB and RF
#if (DEV_BUS_TYPE == PCI_INTERFACE)
//PlatformEFIOWrite1Byte(Adapter, REG_SYS_FUNC_EN, 0xE0);
#if 0
MpWritePCIDwordDBI8192C(Adapter,
(REG_SYS_FUNC_EN - 2),
MpReadPCIDwordDBI8192C(Adapter, (REG_SYS_FUNC_EN - 2), BIT3)&0xFFFCFFFF,
BIT3);
#endif
//u2bTmp = PlatformEFIORead2Byte(Adapter, REG_SYS_FUNC_EN);
//PlatformEFIOWrite2Byte(Adapter, REG_SYS_FUNC_EN, u2bTmp|BIT13|BIT0|BIT1);
MpWritePCIDwordDBI8192C(Adapter,
(REG_SYS_FUNC_EN - 2),
MpReadPCIDwordDBI8192C(Adapter, (REG_SYS_FUNC_EN - 2), BIT3)|BIT29|BIT16|BIT17,
BIT3);
#elif (DEV_BUS_TYPE == USB_INTERFACE)
pHalData->bDuringMac1InitRadioA = _TRUE;
write16(Adapter, REG_SYS_FUNC_EN, read16(Adapter, REG_SYS_FUNC_EN)&0xFFFC);
write16(Adapter, REG_SYS_FUNC_EN, read16(Adapter, REG_SYS_FUNC_EN)|BIT13|BIT0|BIT1);
pHalData->bDuringMac1InitRadioA = _FALSE;
#endif
pHalData->NumTotalRFPath = 2;
bMac1NeedInitRadioAFirst = _TRUE;
}
else
{
// MAC0 enabled, only init radia B.
pszRadioAFile = sz92DTestRadioBFile;
}
}
else
{
return rtStatus;
}
}
}
}
else{
if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's
{
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz92CRadioAFile;
pszRadioBFile = sz92CRadioBFile;
}
else
{
pszRadioAFile = sz92CTestRadioAFile;
pszRadioBFile = sz92CTestRadioBFile;
}
}
else
{
if(IS_NORMAL_CHIP(pHalData->VersionID))
{
pszRadioAFile = sz88CRadioAFile;
pszRadioBFile = sz88CRadioBFile;
}
else
{
pszRadioAFile = sz88CTestRadioAFile;
pszRadioBFile = sz88CTestRadioBFile;
}
}
}
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
if (IS_HARDWARE_TYPE_8192D(pHalData) && bMac1NeedInitRadioAFirst)
{
if (eRFPath == RF90_PATH_A)
{
pHalData->bDuringMac1InitRadioA = _TRUE;
bNeedPowerDownRadioA = _TRUE;
}
if (eRFPath == RF90_PATH_B)
{
pHalData->bDuringMac1InitRadioA = _FALSE;
bMac1NeedInitRadioAFirst = _FALSE;
eRFPath = RF90_PATH_A;
pszRadioAFile = sz92DTestRadioBFile;
pHalData->NumTotalRFPath = 1;
}
}
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF90_PATH_B :
case RF90_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
udelay_os(1);//PlatformStallExecution(1);
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
udelay_os(1);//PlatformStallExecution(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
udelay_os(1);//PlatformStallExecution(1);
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF90_PATH_A:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath);
#else
rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF90_RADIO_PATH_E)eRFPath);
#endif
break;
case RF90_PATH_B:
#ifdef CONFIG_EMBEDDED_FWIMG
rtStatus= PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath);
#else
rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF90_RADIO_PATH_E)eRFPath);
#endif
break;
case RF90_PATH_C:
break;
case RF90_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF90_PATH_A:
case RF90_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF90_PATH_B :
case RF90_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(rtStatus != _SUCCESS){
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
goto phy_RF6052_Config_ParaFile_Fail;
}
}
if (IS_HARDWARE_TYPE_8192D(pHalData) && bNeedPowerDownRadioA)
{
// check MAC0 enable or not again now, if enabled, not power down radio A.
u1bTmp = read8(Adapter, REG_MAC0);
if (!(u1bTmp&MAC0_ON))
{
// power down RF radio A according to YuNan's advice.
#if (DEV_BUS_TYPE == PCI_INTERFACE)
MpWritePCIDwordDBI8192C(Adapter,
rFPGA0_XA_LSSIParameter,
0x00000000,
BIT3);
#elif (DEV_BUS_TYPE == USB_INTERFACE)
pHalData->bDuringMac1InitRadioA = _TRUE;
write32(Adapter, rFPGA0_XA_LSSIParameter, 0x00000000);
pHalData->bDuringMac1InitRadioA = _FALSE;
#endif
}
bNeedPowerDownRadioA = _FALSE;
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
void rtl8192cd_dfs_det_chk(struct rtl8192cd_priv *priv)
{
unsigned int regf98_value;
unsigned int reg918_value;
unsigned int reg91c_value;
unsigned int reg920_value;
unsigned int reg924_value;
unsigned int FA_count_cur=0, FA_count_inc=0;
unsigned int VHT_CRC_ok_cnt_cur=0, VHT_CRC_ok_cnt_inc=0;
unsigned int HT_CRC_ok_cnt_cur=0, HT_CRC_ok_cnt_inc=0;
unsigned int LEG_CRC_ok_cnt_cur=0, LEG_CRC_ok_cnt_inc=0;
unsigned int Total_CRC_OK_cnt_inc=0, FA_CRCOK_ratio=0;
unsigned char DFS_tri_short_pulse=0, DFS_tri_long_pulse=0, fa_mask_mid_th=0, fa_mask_lower_th=0;
unsigned char radar_type = 0; /* 0 for short, 1 for long */
unsigned int short_pulse_cnt_cur=0, short_pulse_cnt_inc=0;
unsigned int long_pulse_cnt_cur=0, long_pulse_cnt_inc=0;
unsigned int total_pulse_count_inc=0, max_sht_pusle_cnt_th=0;
unsigned int sum, k, fa_flag=0;
unsigned int st_L2H_new=0, st_L2H_tmp, index=0, fault_flag_det, fault_flag_psd;
int flags=0;
unsigned long throughput = 0;
int j;
int i, PSD_report_right[20], PSD_report_left[20];
int max_right, max_left;
int max_fa_in_hist=0, total_fa_in_hist=0, pre_post_now_acc_fa_in_hist=0;
if (priv->det_asoc_clear > 0) {
priv->det_asoc_clear--;
priv->pmib->dot11DFSEntry.DFS_detected = 0;
priv->FA_count_pre = 0;
priv->VHT_CRC_ok_cnt_pre = 0;
priv->HT_CRC_ok_cnt_pre = 0;
priv->LEG_CRC_ok_cnt_pre = 0;
priv->mask_idx = 0;
priv->mask_hist_checked = 0;
memset(priv->radar_det_mask_hist, 0, sizeof(priv->radar_det_mask_hist));
memset(priv->pulse_flag_hist, 0, sizeof(priv->pulse_flag_hist));
mod_timer(&priv->dfs_det_chk_timer, jiffies + RTL_MILISECONDS_TO_JIFFIES(priv->pshare->rf_ft_var.dfs_det_period*10));
return;
}
throughput = priv->ext_stats.tx_avarage+priv->ext_stats.rx_avarage;
#ifdef MBSSID
if (priv->pmib->miscEntry.vap_enable) {
for (j=0; j<RTL8192CD_NUM_VWLAN; j++) {
if (IS_DRV_OPEN(priv->pvap_priv[j])) {
throughput += priv->pvap_priv[j]->ext_stats.tx_avarage+priv->pvap_priv[j]->ext_stats.rx_avarage;
}
}
}
#endif
// Get FA count during past 100ms
FA_count_cur = PHY_QueryBBReg(priv, 0xf48, 0x0000ffff);
if (priv->FA_count_pre == 0)
FA_count_inc = 0;
else if (FA_count_cur >= priv->FA_count_pre)
FA_count_inc = FA_count_cur - priv->FA_count_pre;
else
FA_count_inc = FA_count_cur;
priv->FA_count_pre = FA_count_cur;
priv->fa_inc_hist[priv->mask_idx] = FA_count_inc;
for (i=0; i<5; i++) {
total_fa_in_hist = total_fa_in_hist + priv->fa_inc_hist[i];
if (priv->fa_inc_hist[i] > max_fa_in_hist)
max_fa_in_hist = priv->fa_inc_hist[i];
}
if (priv->mask_idx >= priv->pshare->rf_ft_var.dfs_det_flag_offset)
index = priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset;
else
index = priv->pshare->rf_ft_var.dfs_det_hist_len + priv->mask_idx - priv->pshare->rf_ft_var.dfs_det_flag_offset;
if (index == 0)
pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[index+1] + priv->fa_inc_hist[4];
else if (index == 4)
pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[0] + priv->fa_inc_hist[index-1];
else
pre_post_now_acc_fa_in_hist = priv->fa_inc_hist[index] + priv->fa_inc_hist[index+1] + priv->fa_inc_hist[index-1];
// Get VHT CRC32 ok count during past 100ms
VHT_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf0c, 0x00003fff);
if (VHT_CRC_ok_cnt_cur >= priv->VHT_CRC_ok_cnt_pre)
VHT_CRC_ok_cnt_inc = VHT_CRC_ok_cnt_cur - priv->VHT_CRC_ok_cnt_pre;
else
VHT_CRC_ok_cnt_inc = VHT_CRC_ok_cnt_cur;
priv->VHT_CRC_ok_cnt_pre = VHT_CRC_ok_cnt_cur;
// Get HT CRC32 ok count during past 100ms
HT_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf10, 0x00003fff);
if (HT_CRC_ok_cnt_cur >= priv->HT_CRC_ok_cnt_pre)
HT_CRC_ok_cnt_inc = HT_CRC_ok_cnt_cur - priv->HT_CRC_ok_cnt_pre;
else
HT_CRC_ok_cnt_inc = HT_CRC_ok_cnt_cur;
priv->HT_CRC_ok_cnt_pre = HT_CRC_ok_cnt_cur;
// Get Legacy CRC32 ok count during past 100ms
LEG_CRC_ok_cnt_cur = PHY_QueryBBReg(priv, 0xf14, 0x00003fff);
if (LEG_CRC_ok_cnt_cur >= priv->LEG_CRC_ok_cnt_pre)
LEG_CRC_ok_cnt_inc = LEG_CRC_ok_cnt_cur - priv->LEG_CRC_ok_cnt_pre;
else
LEG_CRC_ok_cnt_inc = LEG_CRC_ok_cnt_cur;
priv->LEG_CRC_ok_cnt_pre = LEG_CRC_ok_cnt_cur;
if ((VHT_CRC_ok_cnt_cur == 0x3fff) ||
(HT_CRC_ok_cnt_cur == 0x3fff) ||
(LEG_CRC_ok_cnt_cur == 0x3fff)) {
PHY_SetBBReg(priv, 0xb58, BIT(0), 1);
PHY_SetBBReg(priv, 0xb58, BIT(0), 0);
}
Total_CRC_OK_cnt_inc = VHT_CRC_ok_cnt_inc + HT_CRC_ok_cnt_inc + LEG_CRC_ok_cnt_inc;
// check if the FA occrus frequencly during 100ms
// FA_count_inc is divided by Total_CRC_OK_cnt_inc, which helps to distinguish normal trasmission from interference
if (Total_CRC_OK_cnt_inc > 0)
FA_CRCOK_ratio = FA_count_inc / Total_CRC_OK_cnt_inc;
//=====dynamic power threshold (DPT) ========
// Get short pulse count, need carefully handle the counter overflow
regf98_value = PHY_QueryBBReg(priv, 0xf98, 0xffffffff);
short_pulse_cnt_cur = regf98_value & 0x000000ff;
if (short_pulse_cnt_cur >= priv->short_pulse_cnt_pre)
short_pulse_cnt_inc = short_pulse_cnt_cur - priv->short_pulse_cnt_pre;
else
short_pulse_cnt_inc = short_pulse_cnt_cur;
priv->short_pulse_cnt_pre = short_pulse_cnt_cur;
// Get long pulse count, need carefully handle the counter overflow
long_pulse_cnt_cur = (regf98_value & 0x0000ff00) >> 8;
if (long_pulse_cnt_cur >= priv->long_pulse_cnt_pre)
long_pulse_cnt_inc = long_pulse_cnt_cur - priv->long_pulse_cnt_pre;
else
long_pulse_cnt_inc = long_pulse_cnt_cur;
priv->long_pulse_cnt_pre = long_pulse_cnt_cur;
total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc;
if (priv->pshare->rf_ft_var.dfs_det_print) {
panic_printk("=====================================================================\n");
panic_printk("Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d] FA_CRCOK_ratio[%d]\n",
Total_CRC_OK_cnt_inc, VHT_CRC_ok_cnt_inc, HT_CRC_ok_cnt_inc, LEG_CRC_ok_cnt_inc, FA_count_inc, FA_CRCOK_ratio);
panic_printk("Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
priv->ini_gain_cur, priv->st_L2H_cur, regf98_value, short_pulse_cnt_inc, long_pulse_cnt_inc);
panic_printk("Throughput: %luMbps\n", (throughput>>17));
reg918_value = PHY_QueryBBReg(priv, 0x918, 0xffffffff);
reg91c_value = PHY_QueryBBReg(priv, 0x91c, 0xffffffff);
reg920_value = PHY_QueryBBReg(priv, 0x920, 0xffffffff);
reg924_value = PHY_QueryBBReg(priv, 0x924, 0xffffffff);
printk("0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n", reg918_value, reg91c_value, reg920_value, reg924_value);
}
static int
phy_RF6052_Config_ParaFile(
IN PADAPTER Adapter
)
{
u32 u4RegValue;
u8 eRFPath;
BB_REGISTER_DEFINITION_T *pPhyReg;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
static char sz88eRadioAFile[] = RTL8188E_PHY_RADIO_A;
static char sz88eRadioBFile[] = RTL8188E_PHY_RADIO_B;
char *pszRadioAFile, *pszRadioBFile;
pszRadioAFile = sz88eRadioAFile;
pszRadioBFile = sz88eRadioBFile;
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
pPhyReg = &pHalData->PHYRegDef[eRFPath];
/*----Store original RFENV control type----*/
switch(eRFPath)
{
case RF_PATH_A:
case RF_PATH_C:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
break;
case RF_PATH_B :
case RF_PATH_D:
u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
break;
}
/*----Set RF_ENV enable----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Set RF_ENV output high----*/
PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
rtw_udelay_os(1);//PlatformStallExecution(1);
/* Set bit number of Address and Data for RF register */
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
rtw_udelay_os(1);//PlatformStallExecution(1);
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF_PATH_A:
#ifdef CONFIG_EMBEDDED_FWIMG
#ifdef CONFIG_PHY_SETTING_WITH_ODM
if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))
rtStatus= _FAIL;
#else
rtStatus= rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
#endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM
#else
rtStatus = rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath);
#endif//#ifdef CONFIG_EMBEDDED_FWIMG
break;
case RF_PATH_B:
#ifdef CONFIG_EMBEDDED_FWIMG
#ifdef CONFIG_PHY_SETTING_WITH_ODM
if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))
rtStatus= _FAIL;
#else
rtStatus = rtl8188e_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
#endif //#ifdef CONFIG_PHY_SETTING_WITH_ODM
#else
rtStatus =rtl8188e_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath);
#endif
break;
case RF_PATH_C:
break;
case RF_PATH_D:
break;
}
/*----Restore RFENV control type----*/;
switch(eRFPath)
{
case RF_PATH_A:
case RF_PATH_C:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
break;
case RF_PATH_B :
case RF_PATH_D:
PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
break;
}
if(rtStatus != _SUCCESS){
//RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
goto phy_RF6052_Config_ParaFile_Fail;
}
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
return rtStatus;
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
static void odm_FastAntTrainingInit(struct odm_dm_struct *dm_odm)
{
struct adapter *adapter = dm_odm->Adapter;
u32 value32, i;
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
u32 AntCombination = 2;
ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_FastAntTrainingInit()\n"));
if (*(dm_odm->mp_mode) == 1) {
ODM_RT_TRACE(dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("dm_odm->AntDivType: %d\n", dm_odm->AntDivType));
return;
}
for (i = 0; i < 6; i++) {
dm_fat_tbl->Bssid[i] = 0;
dm_fat_tbl->antSumRSSI[i] = 0;
dm_fat_tbl->antRSSIcnt[i] = 0;
dm_fat_tbl->antAveRSSI[i] = 0;
}
dm_fat_tbl->TrainIdx = 0;
dm_fat_tbl->FAT_State = FAT_NORMAL_STATE;
/* MAC Setting */
value32 = PHY_QueryBBReg(adapter, 0x4c, bMaskDWord);
PHY_SetBBReg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
value32 = PHY_QueryBBReg(adapter, 0x7B4, bMaskDWord);
PHY_SetBBReg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
/* Match MAC ADDR */
PHY_SetBBReg(adapter, 0x7b4, 0xFFFF, 0);
PHY_SetBBReg(adapter, 0x7b0, bMaskDWord, 0);
PHY_SetBBReg(adapter, 0x870, BIT9|BIT8, 0);/* Reg870[8]=1'b0, Reg870[9]=1'b0 antsel antselb by HW */
PHY_SetBBReg(adapter, 0x864, BIT10, 0); /* Reg864[10]=1'b0 antsel2 by HW */
PHY_SetBBReg(adapter, 0xb2c, BIT22, 0); /* Regb2c[22]=1'b0 disable CS/CG switch */
PHY_SetBBReg(adapter, 0xb2c, BIT31, 1); /* Regb2c[31]=1'b1 output at CG only */
PHY_SetBBReg(adapter, 0xca4, bMaskDWord, 0x000000a0);
/* antenna mapping table */
if (AntCombination == 2) {
if (!dm_odm->bIsMPChip) { /* testchip */
PHY_SetBBReg(adapter, 0x858, BIT10|BIT9|BIT8, 1); /* Reg858[10:8]=3'b001 */
PHY_SetBBReg(adapter, 0x858, BIT13|BIT12|BIT11, 2); /* Reg858[13:11]=3'b010 */
} else { /* MPchip */
PHY_SetBBReg(adapter, 0x914, bMaskByte0, 1);
PHY_SetBBReg(adapter, 0x914, bMaskByte1, 2);
}
} else if (AntCombination == 7) {
if (!dm_odm->bIsMPChip) { /* testchip */
PHY_SetBBReg(adapter, 0x858, BIT10|BIT9|BIT8, 0); /* Reg858[10:8]=3'b000 */
PHY_SetBBReg(adapter, 0x858, BIT13|BIT12|BIT11, 1); /* Reg858[13:11]=3'b001 */
PHY_SetBBReg(adapter, 0x878, BIT16, 0);
PHY_SetBBReg(adapter, 0x858, BIT15|BIT14, 2); /* Reg878[0],Reg858[14:15])=3'b010 */
PHY_SetBBReg(adapter, 0x878, BIT19|BIT18|BIT17, 3);/* Reg878[3:1]=3b'011 */
PHY_SetBBReg(adapter, 0x878, BIT22|BIT21|BIT20, 4);/* Reg878[6:4]=3b'100 */
PHY_SetBBReg(adapter, 0x878, BIT25|BIT24|BIT23, 5);/* Reg878[9:7]=3b'101 */
PHY_SetBBReg(adapter, 0x878, BIT28|BIT27|BIT26, 6);/* Reg878[12:10]=3b'110 */
PHY_SetBBReg(adapter, 0x878, BIT31|BIT30|BIT29, 7);/* Reg878[15:13]=3b'111 */
} else { /* MPchip */
PHY_SetBBReg(adapter, 0x914, bMaskByte0, 0);
PHY_SetBBReg(adapter, 0x914, bMaskByte1, 1);
PHY_SetBBReg(adapter, 0x914, bMaskByte2, 2);
PHY_SetBBReg(adapter, 0x914, bMaskByte3, 3);
PHY_SetBBReg(adapter, 0x918, bMaskByte0, 4);
PHY_SetBBReg(adapter, 0x918, bMaskByte1, 5);
PHY_SetBBReg(adapter, 0x918, bMaskByte2, 6);
PHY_SetBBReg(adapter, 0x918, bMaskByte3, 7);
}
}
/* Default Ant Setting when no fast training */
PHY_SetBBReg(adapter, 0x80c, BIT21, 1); /* Reg80c[21]=1'b1 from TX Info */
PHY_SetBBReg(adapter, 0x864, BIT5|BIT4|BIT3, 0); /* Default RX */
PHY_SetBBReg(adapter, 0x864, BIT8|BIT7|BIT6, 1); /* Optional RX */
/* Enter Traing state */
PHY_SetBBReg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1)); /* Reg864[2:0]=3'd6 ant combination=reg864[2:0]+1 */
PHY_SetBBReg(adapter, 0xc50, BIT7, 1); /* RegC50[7]=1'b1 enable HW AntDiv */
}
s32
MPT_InitializeAdapter(
IN PADAPTER pAdapter,
IN u8 Channel
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
s32 rtStatus = _SUCCESS;
PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
u32 tmpRegA, tmpRegC, TempCCk,ledsetting;
//-------------------------------------------------------------------------
// HW Initialization for 8190 MPT.
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// SW Initialization for 8190 MP.
//-------------------------------------------------------------------------
pMptCtx->bMptDrvUnload = _FALSE;
pMptCtx->bMassProdTest = _FALSE;
pMptCtx->bMptIndexEven = _TRUE; //default gain index is -6.0db
/* Init mpt event. */
#if 0 // for Windows
NdisInitializeEvent( &(pMptCtx->MptWorkItemEvent) );
NdisAllocateSpinLock( &(pMptCtx->MptWorkItemSpinLock) );
PlatformInitializeWorkItem(
Adapter,
&(pMptCtx->MptWorkItem),
(RT_WORKITEM_CALL_BACK)MPT_WorkItemCallback,
(PVOID)Adapter,
"MptWorkItem");
#endif
pMptCtx->bMptWorkItemInProgress = _FALSE;
pMptCtx->CurrMptAct = NULL;
//-------------------------------------------------------------------------
#if 1
// Don't accept any packets
rtw_write32(pAdapter, REG_RCR, 0);
#else
// Accept CRC error and destination address
pHalData->ReceiveConfig |= (RCR_ACRC32|RCR_AAP);
rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
#endif
#if 0
// If EEPROM or EFUSE is empty,we assign as RF 2T2R for MP.
if (pHalData->AutoloadFailFlag == TRUE)
{
pHalData->RF_Type = RF_2T2R;
}
#endif
ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS);
#ifdef CONFIG_RTL8192C
PHY_IQCalibrate(pAdapter, _FALSE);
dm_CheckTXPowerTracking(pAdapter); //trigger thermal meter
PHY_LCCalibrate(pAdapter);
#endif
#ifdef CONFIG_RTL8192D
PHY_IQCalibrate(pAdapter);
dm_CheckTXPowerTracking(pAdapter); //trigger thermal meter
PHY_LCCalibrate(pAdapter);
#endif
#ifdef CONFIG_PCI_HCI
PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //Wifi default use Main
#else
#ifdef CONFIG_RTL8192C
#if 1
if (pHalData->BoardType == BOARD_MINICARD)
PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //default use Main
#else
if(pAdapter->HalFunc.GetInterfaceSelectionHandler(pAdapter) == INTF_SEL2_MINICARD )
PHY_SetRFPathSwitch(Adapter, pAdapter->MgntInfo.bDefaultAntenna); //default use Main
#endif
#endif
#endif
pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
return rtStatus;
}
s32
MPT_InitializeAdapter(
IN PADAPTER pAdapter,
IN u8 Channel
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
s32 rtStatus = _SUCCESS;
PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
u32 ledsetting;
struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv;
//-------------------------------------------------------------------------
// HW Initialization for 8190 MPT.
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// SW Initialization for 8190 MP.
//-------------------------------------------------------------------------
pMptCtx->bMptDrvUnload = _FALSE;
pMptCtx->bMassProdTest = _FALSE;
pMptCtx->bMptIndexEven = _TRUE; //default gain index is -6.0db
pMptCtx->h2cReqNum = 0x0;
/* Init mpt event. */
#if 0 // for Windows
NdisInitializeEvent( &(pMptCtx->MptWorkItemEvent) );
NdisAllocateSpinLock( &(pMptCtx->MptWorkItemSpinLock) );
PlatformInitializeWorkItem(
Adapter,
&(pMptCtx->MptWorkItem),
(RT_WORKITEM_CALL_BACK)MPT_WorkItemCallback,
(PVOID)Adapter,
"MptWorkItem");
#endif
//init for BT MP
#ifdef CONFIG_RTL8723A
pMptCtx->bMPh2c_timeout = _FALSE;
pMptCtx->MptH2cRspEvent = _FALSE;
pMptCtx->MptBtC2hEvent = _FALSE;
_rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
_init_timer( &pMptCtx->MPh2c_timeout_timer, pAdapter->pnetdev, MPh2c_timeout_handle, pAdapter );
//before the reset bt patch command,set the wifi page 0's IO to BT mac reboot.
#endif
pMptCtx->bMptWorkItemInProgress = _FALSE;
pMptCtx->CurrMptAct = NULL;
//-------------------------------------------------------------------------
#if 1
// Don't accept any packets
rtw_write32(pAdapter, REG_RCR, 0);
#else
// Accept CRC error and destination address
//pHalData->ReceiveConfig |= (RCR_ACRC32|RCR_AAP);
//rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
rtw_write32(pAdapter, REG_RCR, 0x70000101);
#endif
#if 0
// If EEPROM or EFUSE is empty,we assign as RF 2T2R for MP.
if (pHalData->AutoloadFailFlag == TRUE)
{
pHalData->RF_Type = RF_2T2R;
}
#endif
//ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
//rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS);
if(IS_HARDWARE_TYPE_8192DU(pAdapter))
{
rtw_write32(pAdapter, REG_LEDCFG0, 0x8888);
}
else
{
//rtw_write32(pAdapter, REG_LEDCFG0, 0x08080);
ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
#if defined (CONFIG_RTL8192C) || defined( CONFIG_RTL8192D )
rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS);
#endif
}
PHY_IQCalibrate(pAdapter, _FALSE);
dm_CheckTXPowerTracking(&pHalData->odmpriv); //trigger thermal meter
PHY_LCCalibrate(pAdapter);
#ifdef CONFIG_PCI_HCI
PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //Wifi default use Main
#else
#ifdef CONFIG_RTL8192C
if (pHalData->BoardType == BOARD_MINICARD)
PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //default use Main
#endif
#endif
pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
#ifdef CONFIG_RTL8188E
pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
#endif
//set ant to wifi side in mp mode
#ifdef CONFIG_RTL8723A
rtl8723a_InitAntenna_Selection(pAdapter);
#endif //CONFIG_RTL8723A
//set ant to wifi side in mp mode
rtw_write16(pAdapter, 0x870, 0x300);
rtw_write16(pAdapter, 0x860, 0x110);
if (pAdapter->registrypriv.mp_mode == 1)
pmlmepriv->fw_state = WIFI_MP_STATE;
return rtStatus;
}
