static void rk3036_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, int *reg, u8 *bit) { struct rockchip_pinctrl_priv *priv = bank->priv; *regmap = priv->regmap_base; *reg = RK3036_PULL_OFFSET; *reg += bank->bank_num * RK3036_PULL_BANK_STRIDE; *reg += (pin_num / RK3036_PULL_PINS_PER_REG) * 4; *bit = pin_num % RK3036_PULL_PINS_PER_REG; }; static struct rockchip_pin_bank rk3036_pin_banks[] = { PIN_BANK(0, 32, "gpio0"), PIN_BANK(1, 32, "gpio1"), PIN_BANK(2, 32, "gpio2"), }; static struct rockchip_pin_ctrl rk3036_pin_ctrl = { .pin_banks = rk3036_pin_banks, .nr_banks = ARRAY_SIZE(rk3036_pin_banks), .label = "RK3036-GPIO", .type = RK3036, .grf_mux_offset = 0xa8, .pull_calc_reg = rk3036_calc_pull_reg_and_bit, }; static const struct udevice_id rk3036_pinctrl_ids[] = { {
IOMUX_WIDTH_4BIT, 0, 0 ), PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 0, 0, IOMUX_UNROUTED ), PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 0, IOMUX_WIDTH_4BIT, IOMUX_UNROUTED ), PIN_BANK(8, 16, "gpio8"), }; #endif static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id) { switch (pwm_id) { case PERIPH_ID_PWM0: rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT, GPIO7A0_PWM_0 << GPIO7A0_SHIFT); break; case PERIPH_ID_PWM1: rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT, GPIO7A1_PWM_1 << GPIO7A1_SHIFT); break; case PERIPH_ID_PWM2:
{ \ .bank_num = id, \ .nr_pins = pins, \ .name = label, \ .iomux = { \ { .type = iom0, .offset = -1 }, \ { .type = iom1, .offset = -1 }, \ { .type = iom2, .offset = -1 }, \ { .type = iom3, .offset = -1 }, \ }, \ } #ifndef CONFIG_SPL_BUILD static struct rockchip_pin_bank rk3188_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), PIN_BANK(1, 32, "gpio1"), PIN_BANK(2, 32, "gpio2"), PIN_BANK(3, 32, "gpio3"), }; #endif static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id) { switch (pwm_id) { case PERIPH_ID_PWM0: rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT, GPIO3D3_PWM_0 << GPIO3D3_SHIFT); break; case PERIPH_ID_PWM1: rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT, GPIO3D4_PWM_1 << GPIO3D4_SHIFT);