/*!
* @cond DOXYGEN_PRIVATE
*
* @brief Atomically captures current time into HWTIMER_TIME_STRUCT structure
*
* Corrects/normalizes the values if necessary (interrupt pending, etc.)
*
* @param hwtimer[in] Pointer to hwtimer structure.
* @param time[out] Pointer to time structure. This value is filled with current value of the timer.
*
* @return kHwtimerSuccess Success.
*
* @see HWTIMER_SYS_PitInit
* @see HWTIMER_SYS_PitDeinit
* @see HWTIMER_SYS_PitSetDiv
* @see HWTIMER_SYS_PitStart
* @see HWTIMER_SYS_PitStop
* @see HWTIMER_SYS_PitIsr
* @see HWTIMER_SYS_PitIsrShared
*/
static _hwtimer_error_code_t HWTIMER_SYS_PitGetTime(hwtimer_t *hwtimer, hwtimer_time_t *time)
{
uint32_t pitChannel;
uint32_t tempCval;
uint32_t baseAddr = g_pitBaseAddr[0];
assert(NULL != hwtimer);
assert(NULL != time);
pitChannel = hwtimer->llContext[0U];
assert(pitChannel < FSL_FEATURE_PIT_TIMER_COUNT);
/* Enter critical section to avoid disabling interrupt from pit for very long time */
OSA_EnterCritical(kCriticalDisableInt);
PIT_HAL_SetIntCmd(baseAddr, pitChannel, false);
time->ticks = hwtimer->ticks;
tempCval = PIT_HAL_ReadTimerCount(baseAddr, pitChannel);
/* Check pending interrupt flag */
if (PIT_HAL_IsIntPending(baseAddr, pitChannel))
{
PIT_HAL_SetIntCmd(baseAddr, pitChannel, true);
OSA_ExitCritical(kCriticalDisableInt);
time->subTicks = hwtimer->modulo - 1U;
}
else
{
PIT_HAL_SetIntCmd(baseAddr, pitChannel, true);
OSA_ExitCritical(kCriticalDisableInt);
/* todo: following line should be updated when HAL will be updated with this functionality. */
time->subTicks = HW_PIT_LDVALn_RD(baseAddr, pitChannel) - tempCval;
}
return kHwtimerSuccess;
}
/*!
* @cond DOXYGEN_PRIVATE
*
* @brief Initialization of pit timer module
*
* Called by hwtimer_deinit. Disables the peripheral. Unregisters ISR.
*
* @param hwtimer[in] Pointer to hwtimer structure.
*
* @return kHwtimerSuccess Success.
* @return kHwtimerLockError When Locking failed.
* @return kHwtimerRegisterHandlerError When un-registration of the interrupt service routine failed.
*
* @see HWTIMER_SYS_PitInit
* @see HWTIMER_SYS_PitSetDiv
* @see HWTIMER_SYS_PitStart
* @see HWTIMER_SYS_PitStop
* @see HWTIMER_SYS_PitGetTime
* @see HWTIMER_SYS_PitIsr
* @see HWTIMER_SYS_PitIsrShared
*/
static _hwtimer_error_code_t HWTIMER_SYS_PitDeinit(hwtimer_t * hwtimer)
{
/* We belive that if isr is shared ,than is shared for every chanells */
uint32_t baseAddr = g_pitBaseAddr[0];
uint32_t pitChannel;
int i;
assert(NULL != hwtimer);
pitChannel = hwtimer->llContext[0U];
assert(pitChannel < FSL_FEATURE_PIT_TIMER_COUNT);
/* Remove Hwtimer from global array and disable interrupt on this channel */
PIT_HAL_StopTimer(baseAddr, pitChannel);
PIT_HAL_SetIntCmd(baseAddr, pitChannel, false);
PIT_HAL_ClearIntFlag(baseAddr, pitChannel);
/* Critical section. Access to global variable */
if (kStatus_OSA_Success != OSA_MutexLock(g_lock, OSA_WAIT_FOREVER))
{
return kHwtimerLockError;
}
/* Pit can have shared interrupt vectors. We need un-register interrupt only when all hwtimers are de-inited(set to NULL) */
g_hwtimersPit[pitChannel] = NULL;
if (kStatus_OSA_Success != OSA_MutexUnlock(g_lock))
{
return kHwtimerLockError;
}
/* Check if this is last hwtimer in pit_hwtimers_array */
for (i = 0U; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
{
if (NULL != g_hwtimersPit[i])
{
break;
}
}
if (i == FSL_FEATURE_PIT_TIMER_COUNT)
{
if(kStatus_OSA_Success != OSA_InstallIntHandler(kpitIrqIds[pitChannel], NULL))
{
return kHwtimerRegisterHandlerError;
}
}
/* Release lock if does not exists*/
/* Enter critical section to avoid interrupt release locking */
OSA_EnterCritical(kCriticalDisableInt);
if (kStatus_OSA_Success != OSA_MutexUnlock(g_lock))
{
return kHwtimerLockError;
}
g_lock = NULL;
OSA_ExitCritical(kCriticalDisableInt);
return kHwtimerSuccess;
}
/*FUNCTION**********************************************************************
*
* Function Name : PIT_DRV_Deinit
* Description : Disable PIT module and gate control
* This function will disable all PIT interrupts and PIT clock. Then gate the
* PIT clock control. pit_init must be called in order to use PIT again.
*
*END**************************************************************************/
pit_status_t PIT_DRV_Deinit(uint32_t instance)
{
assert(instance < PIT_INSTANCE_COUNT);
PIT_Type * base = g_pitBase[instance];
uint32_t i;
/* Exit if current instance is gated.*/
if (!CLOCK_SYS_GetPitGateCmd(instance))
{
return kStatus_PIT_Fail;
}
/* Disable all PIT interrupts. Clear the chain bit if available */
for (i=0; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
{
PIT_HAL_SetIntCmd(base, i, false);
INT_SYS_DisableIRQ(g_pitIrqId[i]);
#if FSL_FEATURE_PIT_HAS_CHAIN_MODE
PIT_HAL_SetTimerChainCmd(base, i, false);
#endif
}
/* Disable PIT module clock*/
PIT_HAL_Disable(base);
/* Gate PIT clock control*/
CLOCK_SYS_DisablePitClock(instance);
return kStatus_PIT_Success;
}
/*!
* @cond DOXYGEN_PRIVATE
*
* @brief Initialization of pit timer module
*
* Called by hwtimer_deinit. Disables the peripheral. Unregisters ISR.
*
* @param hwtimer[in] Pointer to hwtimer structure.
*
* @return kHwtimerSuccess Success.
* @return kHwtimerRegisterHandlerError When un-registration of the interrupt service routine failed.
*
* @see HWTIMER_SYS_PitInit
* @see HWTIMER_SYS_PitSetDiv
* @see HWTIMER_SYS_PitStart
* @see HWTIMER_SYS_PitStop
* @see HWTIMER_SYS_PitGetTime
* @see HWTIMER_SYS_PitIsrAction
*/
static _hwtimer_error_code_t HWTIMER_SYS_PitDeinit(hwtimer_t * hwtimer)
{
/* We believe that if isr is shared ,than is shared for every channels */
PIT_Type * base = g_pitBase[0];
uint32_t pitChannel;
int i;
assert(NULL != hwtimer);
pitChannel = hwtimer->llContext[0U];
assert(pitChannel < FSL_FEATURE_PIT_TIMER_COUNT);
/* Remove Hwtimer from global array and disable interrupt on this channel */
PIT_HAL_StopTimer(base, pitChannel);
PIT_HAL_SetIntCmd(base, pitChannel, false);
PIT_HAL_ClearIntFlag(base, pitChannel);
/* Pit can have shared interrupt vectors. We need un-register interrupt only when all hwtimers are de-inited(set to NULL) */
g_hwtimersPit[pitChannel] = NULL;
/* Check if this is last hwtimer in pit_hwtimers_array */
for (i = 0U; i < FSL_FEATURE_PIT_TIMER_COUNT; i++)
{
if (NULL != g_hwtimersPit[i])
{
break;
}
}
return kHwtimerSuccess;
}
/*!
* @cond DOXYGEN_PRIVATE
*
* @brief This function initializes caller allocated structure according to given
* numerical identifier of the timer.
*
* Called by hwtimer_init().
* Initializes the HWTIMER structure.
* Sets interrupt priority and registers ISR.
*
* @param hwtimer[in] Returns initialized hwtimer structure handle.
* @param pitId[in] Determines PIT module and pit channel.
* @param isrPrior[in] Interrupt priority for PIT
* @param data[in] Specific data. Not used in this timer.
*
* @return kHwtimerSuccess Success.
* @return kHwtimerInvalidInput When channel number does not exist in pit module.
* @return kHwtimerRegisterHandlerError When registration of the interrupt service routine failed.
*
* @see HWTIMER_SYS_PitDeinit
* @see HWTIMER_SYS_PitSetDiv
* @see HWTIMER_SYS_PitStart
* @see HWTIMER_SYS_PitStop
* @see HWTIMER_SYS_PitGetTime
* @see HWTIMER_SYS_PitIsr
* @see HWTIMER_SYS_PitIsrShared
*/
static _hwtimer_error_code_t HWTIMER_SYS_PitInit(hwtimer_t * hwtimer, uint32_t pitId, uint32_t isrPrior, void *data)
{
uint32_t pitChannel;
uint32_t baseAddr = g_pitBaseAddr[0];
if (FSL_FEATURE_PIT_TIMER_COUNT < pitId)
{
return kHwtimerInvalidInput;
}
assert(NULL != hwtimer);
/* We need to store pitId of timer in context struct */
hwtimer->llContext[0U] = pitId;
pitChannel = hwtimer->llContext[0U];
/* Un-gate pit clock */
CLOCK_SYS_EnablePitClock(0U);
/* Enable PIT module clock */
PIT_HAL_Enable(baseAddr);
/* Allows the timers to be stopped when the device enters the Debug mode. */
PIT_HAL_SetTimerRunInDebugCmd(baseAddr, false);
/* Disable timer and interrupt */
PIT_HAL_StopTimer(baseAddr, pitChannel);
PIT_HAL_SetIntCmd(baseAddr, pitChannel, false);
/* Clear any pending interrupt */
PIT_HAL_ClearIntFlag(baseAddr, pitChannel);
/* Store hwtimer in global array */
g_hwtimersPit[pitChannel] = hwtimer;
/* Enable PIT interrupt.*/
if (kStatus_OSA_Success != OSA_InstallIntHandler(g_pitIrqId[pitChannel], HWTIMER_SYS_PitIsr))
{
return kHwtimerRegisterHandlerError;
}
PIT_HAL_SetIntCmd(baseAddr, pitChannel, true);
INT_SYS_EnableIRQ(g_pitIrqId[pitChannel]);
return kHwtimerSuccess;
}
/*!
* @brief Function ltc_timer_init initialize PIT timer
* to measure time.
*/
static void ltc_timer_init(void)
{
SIM_HAL_EnableClock(SIM, kSimClockGatePit0);
PIT_HAL_Enable(pitBase[0]);
PIT_HAL_StopTimer(pitBase[0], LTC_TIMER_PIT_CHANNEL);
PIT_HAL_SetTimerPeriodByCount(pitBase[0], LTC_TIMER_PIT_CHANNEL, RELOAD);
PIT_HAL_SetIntCmd(pitBase[0], LTC_TIMER_PIT_CHANNEL, false);
PIT_HAL_SetTimerRunInDebugCmd(pitBase[0], false); /* timer stop counting in debug mode */
PIT_HAL_ClearIntFlag(pitBase[0], LTC_TIMER_PIT_CHANNEL);
}
/*!
* @cond DOXYGEN_PRIVATE
*
* @brief Stop pit timer module
*
* Disable timer and interrupt
*
* @param hwtimer[in] Pointer to hwtimer structure.
*
* @return kHwtimerSuccess Success.
*
* @see HWTIMER_SYS_PitInit
* @see HWTIMER_SYS_PitDeinit
* @see HWTIMER_SYS_PitSetDiv
* @see HWTIMER_SYS_PitStart
* @see HWTIMER_SYS_PitGetTime
* @see HWTIMER_SYS_PitIsr
* @see HWTIMER_SYS_PitIsrShared
*/
static _hwtimer_error_code_t HWTIMER_SYS_PitStop(hwtimer_t * hwtimer)
{
uint32_t pitChannel;
uint32_t baseAddr = g_pitBaseAddr[0];
assert(NULL != hwtimer);
pitChannel = hwtimer->llContext[0U];
assert(pitChannel < FSL_FEATURE_PIT_TIMER_COUNT);
/* Disable timer and interrupt */
PIT_HAL_StopTimer(baseAddr, pitChannel);
PIT_HAL_SetIntCmd(baseAddr, pitChannel, false);
PIT_HAL_ClearIntFlag(baseAddr, pitChannel);
return kHwtimerSuccess;
}
/*!
* @cond DOXYGEN_PRIVATE
*
* @brief Start pit timer module
*
* This function enables the timer and leaves it running, timer is
* periodically generating interrupts.
*
* @param hwtimer[in] Pointer to hwtimer structure.
*
* @return kHwtimerSuccess Success.
*
* @see HWTIMER_SYS_PitInit
* @see HWTIMER_SYS_PitDeinit
* @see HWTIMER_SYS_PitSetDiv
* @see HWTIMER_SYS_PitStop
* @see HWTIMER_SYS_PitGet_time
* @see HWTIMER_SYS_PitIsrAction
*/
static _hwtimer_error_code_t HWTIMER_SYS_PitStart(hwtimer_t * hwtimer)
{
uint32_t pitChannel;
PIT_Type * base = g_pitBase[0];
assert(NULL != hwtimer);
pitChannel = hwtimer->llContext[0U];
assert(pitChannel < FSL_FEATURE_PIT_TIMER_COUNT);
PIT_HAL_StopTimer(base, pitChannel);
PIT_HAL_ClearIntFlag(base, pitChannel);
PIT_HAL_SetIntCmd(base, pitChannel, true);
PIT_HAL_StartTimer(base, pitChannel);
return kHwtimerSuccess;
}
/*FUNCTION**********************************************************************
*
* Function Name : PIT_DRV_InitChannel
* Description : Initialize PIT channel.
* This function initialize PIT timers by channel. Pass in timer number and its
* config structure. Timers do not start counting by default after calling this
* function. Function PIT_DRV_StartTimer must be called to start timer counting.
* Call PIT_DRV_SetTimerPeriodByUs to re-set the period.
*
*END**************************************************************************/
void PIT_DRV_InitChannel(uint32_t instance,
uint32_t channel,
const pit_user_config_t * config)
{
assert(instance < PIT_INSTANCE_COUNT);
PIT_Type * base = g_pitBase[instance];
/* Set timer period.*/
PIT_DRV_SetTimerPeriodByUs(instance, channel, config->periodUs);
/* Enable or disable interrupt.*/
PIT_HAL_SetIntCmd(base, channel, config->isInterruptEnabled);
/* Configure NVIC*/
if (config->isInterruptEnabled)
{
/* Enable PIT interrupt.*/
INT_SYS_EnableIRQ(g_pitIrqId[channel]);
}
}
/*!
* @cond DOXYGEN_PRIVATE
*
* @brief This function initializes caller allocated structure according to given
* numerical identifier of the timer.
*
* Called by hwtimer_init().
* Initializes the HWTIMER structure.
* Sets interrupt priority and registers ISR.
*
* @param hwtimer[in] Returns initialized hwtimer structure handle.
* @param pitId[in] Determines PIT module and pit channel.
* @param isrPrior[in] Interrupt priority for PIT
* @param data[in] Specific data. Not used in this timer.
*
* @return kHwtimerSuccess Success.
* @return kHwtimerInvalidInput When channel number does not exist in pit module.
* @return kHwtimerLockError When Locking failed.
* @return kHwtimerRegisterHandlerError When registration of the interrupt service routine failed.
*
* @see HWTIMER_SYS_PitDeinit
* @see HWTIMER_SYS_PitSetDiv
* @see HWTIMER_SYS_PitStart
* @see HWTIMER_SYS_PitStop
* @see HWTIMER_SYS_PitGetTime
* @see HWTIMER_SYS_PitIsr
* @see HWTIMER_SYS_PitIsrShared
*/
static _hwtimer_error_code_t HWTIMER_SYS_PitInit(hwtimer_t * hwtimer, uint32_t pitId, uint32_t isrPrior, void *data)
{
uint32_t pitChannel;
uint32_t baseAddr = g_pitBaseAddr[0];
if (FSL_FEATURE_PIT_TIMER_COUNT < pitId)
{
return kHwtimerInvalidInput;
}
assert(NULL != hwtimer);
/* We need to store pitId of timer in context struct */
hwtimer->llContext[0U] = pitId;
pitChannel = hwtimer->llContext[0U];
/* Un-gate pit clock */
CLOCK_SYS_EnablePitClock(0U);
/* Enable PIT module clock */
PIT_HAL_Enable(baseAddr);
/* Allows the timers to be stopped when the device enters the Debug mode. */
PIT_HAL_SetTimerRunInDebugCmd(baseAddr, false);
/* Disable timer and interrupt */
PIT_HAL_StopTimer(baseAddr, pitChannel);
PIT_HAL_SetIntCmd(baseAddr, pitChannel, false);
/* Clear any pending interrupt */
PIT_HAL_ClearIntFlag(baseAddr, pitChannel);
/* Create lock if does not exists*/
/* Enter critical section to avoid interrupt create locking */
OSA_EnterCritical(kCriticalDisableInt);
if (g_lock == NULL)
{
/* Initialize synchronization object */
if (kStatus_OSA_Success != OSA_MutexCreate(&g_lock_data))
{
return kHwtimerLockError;
}
g_lock = &g_lock_data;
}
OSA_ExitCritical(kCriticalDisableInt);
assert(g_lock == &g_lock_data);
/* Critical section. Access to global variable */
if (kStatus_OSA_Success != OSA_MutexLock(g_lock, OSA_WAIT_FOREVER))
{
return kHwtimerLockError;
}
/* Store hwtimer in global array */
g_hwtimersPit[pitChannel] = hwtimer;
if (kStatus_OSA_Success != OSA_MutexUnlock(g_lock))
{
return kHwtimerLockError;
}
/* Enable PIT interrupt.*/
if (kStatus_OSA_Success != OSA_InstallIntHandler(kpitIrqIds[pitChannel], HWTIMER_SYS_PitIsr))
{
return kHwtimerRegisterHandlerError;
}
PIT_HAL_SetIntCmd(baseAddr, pitChannel, true);
INT_SYS_EnableIRQ(kpitIrqIds[pitChannel]);
return kHwtimerSuccess;
}