/* * Initialize the lane_to_slot[] array. * * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board * slots is hard-coded. On the Hydra board, however, the mapping is controlled * by board switch SW2, so the lane_to_slot[] array needs to be dynamically * initialized. */ static void initialize_lane_to_slot(void) { u8 sw2 = in_8(&PIXIS_SW(2)); /* SW11 appears in the programming model as SW9 */ u8 sw11 = in_8(&PIXIS_SW(9)); lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; lane_to_slot[3] = lane_to_slot[2]; lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; lane_to_slot[5] = lane_to_slot[4]; switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { case PIXIS_SW2_LANE_67_SEL_5: lane_to_slot[6] = 5; break; case PIXIS_SW2_LANE_67_SEL_6: lane_to_slot[6] = 6; break; case PIXIS_SW2_LANE_67_SEL_7: lane_to_slot[6] = 7; break; } lane_to_slot[7] = lane_to_slot[6]; lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; lane_to_slot[17] = lane_to_slot[16]; }
int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->arch.cpu; #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) || \ defined(CONFIG_P5040DS) unsigned int i; #endif static const char * const freq[] = {"100", "125", "156.25", "212.5" }; printf("Board: %sDS, ", cpu->name); printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; if (sw < 0x8) printf("vBank: %d\n", sw); else if (sw == 0x8) puts("Promjet\n"); else if (sw == 0x9) puts("NAND\n"); else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the * values that the SERDES expects (or vice versa). For now, however, * we just display both values and hope the user notices when they * don't match. */ puts("SERDES Reference Clocks: "); #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ || defined(CONFIG_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { unsigned int clock = (sw >> (6 - (2 * i))) & 3; printf("Bank%u=%sMhz ", i+1, freq[clock]); } #ifdef CONFIG_P5040DS /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ sw = in_8(&PIXIS_SW(9)); printf("Bank4=%sMhz ", freq[sw & 3]); #endif puts("\n"); #else sw = in_8(&PIXIS_SW(3)); /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); #endif return 0; }
int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw; #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ || defined(CONFIG_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { unsigned int clock = (sw >> (6 - (2 * i))) & 3; switch (clock) { case 0: actual[i] = SRDS_PLLCR0_RFCK_SEL_100; break; case 1: actual[i] = SRDS_PLLCR0_RFCK_SEL_125; break; case 2: actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; break; default: printf("Warning: SDREFCLK%u switch setting of '11' is " "unsupported\n", i + 1); break; } } #else /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. */ sw = in_8(&PIXIS_SW(3)); actual[0] = (sw & 0x40) ? SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; actual[1] = (sw & 0x20) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; actual[2] = (sw & 0x10) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; #endif for (i = 0; i < NUM_SRDS_BANKS; i++) { u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { printf("Warning: SERDES bank %u expects reference clock" " %sMHz, but actual is %sMHz\n", i + 1, serdes_clock_to_string(expected), serdes_clock_to_string(actual[i])); } } return 0; }
/* * Initialize the lane_to_slot[] array. * * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board * slots is hard-coded. On the Hydra board, however, the mapping is controlled * by board switch SW2, so the lane_to_slot[] array needs to be dynamically * initialized. */ static void initialize_lane_to_slot(void) { u8 sw2 = in_8(&PIXIS_SW(2)); lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; lane_to_slot[3] = lane_to_slot[2]; lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; lane_to_slot[5] = lane_to_slot[4]; switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { case PIXIS_SW2_LANE_67_SEL_5: lane_to_slot[6] = 5; break; case PIXIS_SW2_LANE_67_SEL_6: lane_to_slot[6] = 6; break; case PIXIS_SW2_LANE_67_SEL_7: lane_to_slot[6] = 7; break; } lane_to_slot[7] = lane_to_slot[6]; lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; lane_to_slot[17] = lane_to_slot[16]; }
int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3; gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_SRIO1 if (is_serdes_configured(SRIO1)) { set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_RIO_1); } else { printf (" SRIO1: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ #endif #ifdef CONFIG_SRIO2 if (is_serdes_configured(SRIO2)) { set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_RIO_2); } else { printf (" SRIO2: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ #endif /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. */ sw3 = in_8(&PIXIS_SW(3)); actual[0] = (sw3 & 0x40) ? SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; actual[1] = (sw3 & 0x20) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; actual[2] = (sw3 & 0x10) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; for (i = 0; i < NUM_SRDS_BANKS; i++) { u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { printf("Warning: SERDES bank %u expects reference clock" " %sMHz, but actual is %sMHz\n", i + 1, serdes_clock_to_string(expected), serdes_clock_to_string(actual[i])); } } return 0; }
int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->cpu; printf("Board: %sDS, ", cpu->name); printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; if (sw < 0x8) printf("vBank: %d\n", sw); else if (sw == 0x8) puts("Promjet\n"); else if (sw == 0x9) puts("NAND\n"); else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); #ifdef CONFIG_PHYS_64BIT puts("36-bit Addressing\n"); #endif /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the * values that the SERDES expects (or vice versa). For now, however, * we just display both values and hope the user notices when they * don't match. */ puts("SERDES Reference Clocks: "); sw = in_8(&PIXIS_SW(3)); printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); return 0; }
int checkboard(void) { u8 sw; printf("Board: P2020DS Sys ID: 0x%02x, " "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; if (sw < 0x8) /* The lower two bits are the actual vbank number */ printf("vBank: %d\n", sw & 3); else puts("Promjet\n"); return 0; }
int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->cpu; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; unsigned int i; printf("Board: %sDS, ", cpu->name); printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; if (sw < 0x8) printf("vBank: %d\n", sw); else if (sw == 0x8) puts("Promjet\n"); else if (sw == 0x9) puts("NAND\n"); else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); #ifdef CONFIG_PHYS_64BIT puts("36-bit Addressing\n"); #endif /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { u32 rcw = in_be32(&gur->rcwsr[i]); if ((i % 4) == 0) printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the * values that the SERDES expects (or vice versa). For now, however, * we just display both values and hope the user notices when they * don't match. */ puts("SERDES Reference Clocks: "); #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { static const char *freq[] = {"100", "125", "156.25", "212.5" }; unsigned int clock = (sw >> (6 - (2 * i))) & 3; printf("Bank%u=%sMhz ", i+1, freq[clock]); } puts("\n"); #else sw = in_8(&PIXIS_SW(3)); printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); #endif return 0; }