int zynq_pll_init(void) {
zynq_slcr_unlock();
/* ARM PLL & Clock config
* 375 cycles needed for pll
* 26 divisor on pll
* enable all ARM clocks
* 2 divisor on ARM clocks
* ARM clock source is ARM PLL
*/
SLCR_REG(ARM_PLL_CFG) = PLL_CFG_LOCK_CNT(375) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(ARM_PLL_CTRL) = PLL_FDIV(26) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_ARM_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(ARM_CLK_CTRL) = ARM_CLK_CTRL_DIVISOR(2) | ARM_CLK_CTRL_CPU_6OR4XCLKACT |
ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT |
ARM_CLK_CTRL_CPU_1XCLKACT |ARM_CLK_CTRL_PERI_CLKACT;
/* DDR PLL & Clock config
* 475 cycles needed
* 21 divisor on PLL
* enable all DDR clocks
* 2 divisor for 3XCLK, 3 divisor for 2XCLK
*/
SLCR_REG(DDR_PLL_CFG) = PLL_CFG_LOCK_CNT(475) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(DDR_PLL_CTRL) = PLL_FDIV(26) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_DDR_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(DDR_CLK_CTRL) = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT |
DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3);
/* IO PLL config
* 500 cycles needed for pll
* 20 divisor
*/
SLCR_REG(IO_PLL_CFG) = PLL_CFG_LOCK_CNT(500) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(IO_PLL_CTRL) = PLL_FDIV(20) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(IO_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_IO_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(IO_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
zynq_slcr_lock();
return 0;
}
/* For each PLL we need to configure the cp / res / lock_cnt and then place the PLL in bypass
* before doing a reset to switch to the new values. Then bypass is removed to switch back to using
* the PLL once its locked.
*/
int zynq_pll_init(void) {
const zynq_pll_cfg_tree_t *cfg = &zynq_pll_cfg;
SLCR_REG(ARM_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->arm.lock_cnt) | PLL_CFG_PLL_CP(cfg->arm.cp) |
PLL_CFG_PLL_RES(cfg->arm.res);
SLCR_REG(ARM_PLL_CTRL) = PLL_FDIV(cfg->arm.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_RESET;
if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_ARM_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(ARM_CLK_CTRL) = zynq_clk_cfg.arm_clk;
#if ZYNQ_SDRAM_INIT
SLCR_REG(DDR_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->ddr.lock_cnt) | PLL_CFG_PLL_CP(cfg->ddr.cp) |
PLL_CFG_PLL_RES(cfg->ddr.res);
SLCR_REG(DDR_PLL_CTRL) = PLL_FDIV(cfg->ddr.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_RESET;
if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_DDR_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(DDR_CLK_CTRL) = zynq_clk_cfg.ddr_clk;
#elif SDRAM_SIZE == 0
/* if we're not using sdram and haven't been told to initialize sdram, stop the DDR pll */
SLCR_REG(DDR_CLK_CTRL) = 0;
SLCR_REG(DDR_PLL_CTRL) |= PLL_PWRDOWN;
#endif
SLCR_REG(IO_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->io.lock_cnt) | PLL_CFG_PLL_CP(cfg->io.cp) |
PLL_CFG_PLL_RES(cfg->io.res);
SLCR_REG(IO_PLL_CTRL) = PLL_FDIV(cfg->io.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(IO_PLL_CTRL) &= ~PLL_RESET;
if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_IO_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(IO_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
return 0;
}
/* For each PLL we need to configure the cp / res / lock_cnt and then place the PLL in bypass
* before doing a reset to switch to the new values. Then bypass is removed to switch back to using
* the PLL once its locked.
*/
int zynq_pll_init(void) {
const zynq_pll_cfg_tree_t *cfg = &zynq_pll_cfg;
zynq_slcr_unlock();
SLCR_REG(ARM_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->arm.lock_cnt) | PLL_CFG_PLL_CP(cfg->arm.cp) |
PLL_CFG_PLL_RES(cfg->arm.res);
SLCR_REG(ARM_PLL_CTRL) = PLL_FDIV(cfg->arm.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_RESET;
if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_ARM_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(ARM_CLK_CTRL) = zynq_clk_cfg.arm_clk;
#if ZYNQ_SDRAM_INIT
SLCR_REG(DDR_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->ddr.lock_cnt) | PLL_CFG_PLL_CP(cfg->ddr.cp) |
PLL_CFG_PLL_RES(cfg->ddr.res);
SLCR_REG(DDR_PLL_CTRL) = PLL_FDIV(cfg->ddr.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_RESET;
if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_DDR_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(DDR_CLK_CTRL) = zynq_clk_cfg.ddr_clk;
#endif
SLCR_REG(IO_PLL_CFG) = PLL_CFG_LOCK_CNT(cfg->io.lock_cnt) | PLL_CFG_PLL_CP(cfg->io.cp) |
PLL_CFG_PLL_RES(cfg->io.res);
SLCR_REG(IO_PLL_CTRL) = PLL_FDIV(cfg->io.fdiv) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(IO_PLL_CTRL) &= ~PLL_RESET;
if (reg_poll((uintptr_t)&SLCR->PLL_STATUS, PLL_STATUS_IO_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(IO_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
zynq_slcr_lock();
return 0;
}