static inline void plls_resume(void)
{
mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3),
plls_con[ABPLL_ID][3] | PLL_BYPASS_W_MSK);
mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3),
plls_con[ALPLL_ID][3] | PLL_BYPASS_W_MSK);
mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3),
plls_con[GPLL_ID][3] | PLL_BYPASS_W_MSK);
mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3),
plls_con[CPLL_ID][3] | PLL_BYPASS_W_MSK);
mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3),
plls_con[NPLL_ID][3] | PLL_BYPASS_W_MSK);
}
void pm_plls_resume(void)
{
plls_resume();
mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3),
plls_con[ABPLL_ID][3] | PLLS_MODE_WMASK);
mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3),
plls_con[ALPLL_ID][3] | PLLS_MODE_WMASK);
mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3),
plls_con[GPLL_ID][3] | PLLS_MODE_WMASK);
mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3),
plls_con[CPLL_ID][3] | PLLS_MODE_WMASK);
mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3),
plls_con[NPLL_ID][3] | PLLS_MODE_WMASK);
}
/* Waiting for pll locked by pll id */
static void rkclk_pll_wait_lock(enum rk_plls_id pll_id)
{
/* delay for pll lock */
while (1) {
if (cru_readl(PLL_CONS(pll_id, 1)) & (0x01 << 31)) {
break;
}
clk_loop_delayus(1);
}
}
/* Set pll mode by id, normal mode or slow mode */
static void rkclk_pll_set_mode(enum rk_plls_id pll_id, int pll_mode)
{
uint32 con;
uint32 nr, dly;
con = cru_readl(PLL_CONS(pll_id, 0));
nr = PLL_NR(con);
dly = (nr * 500) / 24 + 1;
if (pll_mode == RKCLK_PLL_MODE_NORMAL) {
cru_writel(PLL_PWR_ON | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
clk_loop_delayus(dly);
rkclk_pll_wait_lock(pll_id);
/* PLL enter normal-mode */
cru_writel(PLL_MODE_NORM | PLL_MODE_W_MSK, PLL_CONS(pll_id, 3));
} else {
/* PLL enter slow-mode */
cru_writel(PLL_MODE_SLOW | PLL_MODE_W_MSK, PLL_CONS(pll_id, 3));
cru_writel(PLL_PWR_DN | PLL_PWR_DN_W_MSK, PLL_CONS(pll_id, 3));
}
}
/* Set pll rate by id */
static int rkclk_pll_set_rate(enum rk_plls_id pll_id, uint32 mHz, pll_callback_f cb_f)
{
const struct pll_data *pll = NULL;
struct pll_clk_set *clkset = NULL;
unsigned long rate = mHz * MHZ;
int i = 0;
/* Find pll rate set */
for (i=0; i<ARRAY_SIZE(rkpll_data); i++) {
if (rkpll_data[i].id == pll_id) {
pll = &rkpll_data[i];
break;
}
}
if ((pll == NULL) || (pll->clkset == NULL)) {
return -1;
}
/* Find clock set */
for (i=0; i<pll->size; i++) {
if (pll->clkset[i].rate <= rate) {
clkset = &(pll->clkset[i]);
break;
}
}
if (clkset == NULL) {
return -1;
}
/* PLL enter slow-mode */
cru_writel(PLL_MODE_SLOW | PLL_MODE_W_MSK, PLL_CONS(pll_id, 3));
/* enter rest */
cru_writel((PLL_RESET | PLL_RESET_W_MSK), PLL_CONS(pll_id, 3));
cru_writel(clkset->pllcon0, PLL_CONS(pll_id, 0));
cru_writel(clkset->pllcon1, PLL_CONS(pll_id, 1));
cru_writel(clkset->pllcon2, PLL_CONS(pll_id, 2));
clk_loop_delayus(5);
/* return form rest */
cru_writel(PLL_RESET_RESUME | PLL_RESET_W_MSK, PLL_CONS(pll_id, 3));
clk_loop_delayus(clkset->rst_dly);
/* waiting for pll lock */
rkclk_pll_wait_lock(pll_id);
if (cb_f != NULL) {
cb_f(clkset);
}
/* PLL enter normal-mode */
cru_writel(PLL_MODE_NORM | PLL_MODE_W_MSK, PLL_CONS(pll_id, 3));
return 0;
}
void __dead2 soc_sys_global_soft_reset(void)
{
uint32_t temp_val;
mmio_write_32(CRU_BASE + PLL_CONS((GPLL_ID), 3), PLL_SLOW_BITS);
mmio_write_32(CRU_BASE + PLL_CONS((CPLL_ID), 3), PLL_SLOW_BITS);
mmio_write_32(CRU_BASE + PLL_CONS((NPLL_ID), 3), PLL_SLOW_BITS);
mmio_write_32(CRU_BASE + PLL_CONS((ABPLL_ID), 3), PLL_SLOW_BITS);
mmio_write_32(CRU_BASE + PLL_CONS((ALPLL_ID), 3), PLL_SLOW_BITS);
temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) |
PMU_RST_BY_SECOND_SFT;
mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val);
mmio_write_32(CRU_BASE + CRU_GLB_SRST_SND, 0xeca8);
/*
* Maybe the HW needs some times to reset the system,
* so we do not hope the core to excute valid codes.
*/
while (1)
;
}
void reset_cpu(ulong ignored)
{
disable_interrupts();
FW_NandDeInit();
#ifndef CONFIG_SYS_L2CACHE_OFF
v7_outer_cache_disable();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
flush_dcache_all();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
invalidate_icache_all();
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_disable();
#endif
#ifndef CONFIG_SYS_ICACHE_OFF
icache_disable();
#endif
#if defined(CONFIG_RKCHIP_RK3368)
/* pll enter slow mode */
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(APLLB_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(APLLL_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(GPLL_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(CPLL_ID, 3));
cru_writel(((0x00 << 8) && (0x03 << 24)), PLL_CONS(NPLL_ID, 3));
/* soft reset */
writel(0xeca8, RKIO_CRU_PHYS + CRU_GLB_SRST_SND);
#else
#error "PLS config platform for reset.c!"
#endif /* CONFIG_RKPLATFORM */
}
/* Get pll rate by id */
static uint32 rkclk_pll_get_rate(enum rk_plls_id pll_id)
{
uint32 nr, no, nf;
uint32 con;
con = cru_readl(PLL_CONS(pll_id, 3));
con = (con & PLL_MODE_MSK) >> 8;
if (con == 0) {
/* slow mode */
return (24 * MHZ);
} else if (con == 1) {
/* normal mode */
con = cru_readl(PLL_CONS(pll_id, 0));
no = PLL_NO(con);
nr = PLL_NR(con);
con = cru_readl(PLL_CONS(pll_id, 1));
nf = PLL_NF(con);
return (24 * nf / (nr * no)) * MHZ;
} else {
/* deep slow mode */
return 32768;
}
}
static void plls_suspend(uint32_t pll_id)
{
plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0));
plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1));
plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2));
plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3));
mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS);
mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS);
}
void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr)
{
struct BACKUP_REG_TAG *p_ddr_reg = (struct BACKUP_REG_TAG *)base_addr;
struct PCTL_SAVE_REG_TAG *pctl_tim = &p_ddr_reg->pctl;
p_ddr_reg->tag = 0x56313031;
p_ddr_reg->pctladdr = DDR_PCTL_BASE;
p_ddr_reg->phyaddr = DDR_PHY_BASE;
p_ddr_reg->nocaddr = SERVICE_BUS_BASE;
/* PCTLR */
ddr_copy((uint32_t *)&pctl_tim->pctl_timing.TOGCNT1U,
(uint32_t *)(DDR_PCTL_BASE + DDR_PCTL_TOGCNT1U), 35);
pctl_tim->pctl_timing.TREFI |= DDR_UPD_REF_ENABLE;
pctl_tim->SCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_SCFG);
pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_CMDTSTATEN);
pctl_tim->MCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG1);
pctl_tim->MCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG);
pctl_tim->PPCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_PPCFG);
pctl_tim->pctl_timing.ddrfreq = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_TOGCNT1U * 2);
pctl_tim->DFITCTRLDELAY = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITCTRLDELAY);
pctl_tim->DFIODTCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIODTCFG);
pctl_tim->DFIODTCFG1 = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFIODTCFG1);
pctl_tim->DFIODTRANKMAP = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFIODTRANKMAP);
pctl_tim->DFITPHYWRDATA = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYWRDATA);
pctl_tim->DFITPHYWRLAT = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYWRLAT);
pctl_tim->DFITPHYWRDATALAT = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYWRDATALAT);
pctl_tim->DFITRDDATAEN = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITRDDATAEN);
pctl_tim->DFITPHYRDLAT = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYRDLAT);
pctl_tim->DFITPHYUPDTYPE0 = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYUPDTYPE0);
pctl_tim->DFITPHYUPDTYPE1 = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYUPDTYPE1);
pctl_tim->DFITPHYUPDTYPE2 = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYUPDTYPE2);
pctl_tim->DFITPHYUPDTYPE3 = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITPHYUPDTYPE3);
pctl_tim->DFITCTRLUPDMIN = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITCTRLUPDMIN);
pctl_tim->DFITCTRLUPDMAX = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITCTRLUPDMAX);
pctl_tim->DFITCTRLUPDDLY = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITCTRLUPDDLY);
pctl_tim->DFIUPDCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIUPDCFG);
pctl_tim->DFITREFMSKI = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITREFMSKI);
pctl_tim->DFITCTRLUPDI = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITCTRLUPDI);
pctl_tim->DFISTCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG0);
pctl_tim->DFISTCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG1);
pctl_tim->DFITDRAMCLKEN = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITDRAMCLKEN);
pctl_tim->DFITDRAMCLKDIS = mmio_read_32(DDR_PCTL_BASE +
DDR_PCTL_DFITDRAMCLKDIS);
pctl_tim->DFISTCFG2 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG2);
pctl_tim->DFILPCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFILPCFG0);
/* PHY */
p_ddr_reg->phy.PHY_REG0 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG0);
p_ddr_reg->phy.PHY_REG1 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG1);
p_ddr_reg->phy.PHY_REGB = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGB);
p_ddr_reg->phy.PHY_REGC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGC);
p_ddr_reg->phy.PHY_REG11 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG11);
p_ddr_reg->phy.PHY_REG13 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG13);
p_ddr_reg->phy.PHY_REG14 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG14);
p_ddr_reg->phy.PHY_REG16 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG16);
p_ddr_reg->phy.PHY_REG20 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG20);
p_ddr_reg->phy.PHY_REG21 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG21);
p_ddr_reg->phy.PHY_REG26 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG26);
p_ddr_reg->phy.PHY_REG27 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG27);
p_ddr_reg->phy.PHY_REG28 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG28);
p_ddr_reg->phy.PHY_REG30 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG30);
p_ddr_reg->phy.PHY_REG31 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG31);
p_ddr_reg->phy.PHY_REG36 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG36);
p_ddr_reg->phy.PHY_REG37 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG37);
p_ddr_reg->phy.PHY_REG38 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG38);
p_ddr_reg->phy.PHY_REG40 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG40);
p_ddr_reg->phy.PHY_REG41 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG41);
p_ddr_reg->phy.PHY_REG46 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG46);
p_ddr_reg->phy.PHY_REG47 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG47);
p_ddr_reg->phy.PHY_REG48 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG48);
p_ddr_reg->phy.PHY_REG50 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG50);
p_ddr_reg->phy.PHY_REG51 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG51);
p_ddr_reg->phy.PHY_REG56 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG56);
p_ddr_reg->phy.PHY_REG57 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG57);
p_ddr_reg->phy.PHY_REG58 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG58);
p_ddr_reg->phy.PHY_REGDLL = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REGDLL);
p_ddr_reg->phy.PHY_REGEC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC);
p_ddr_reg->phy.PHY_REGED = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED);
p_ddr_reg->phy.PHY_REGEE = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE);
p_ddr_reg->phy.PHY_REGEF = 0;
if (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG2) & 0x2) {
p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REG2C);
p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REG3C);
p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REG4C);
p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REG5C);
} else {
p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REGFB);
p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REGFC);
p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REGFD);
p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE +
DDR_PHY_REGFE);
}
/* NOC */
p_ddr_reg->noc.ddrconf = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRCONF);
p_ddr_reg->noc.ddrtiming = mmio_read_32(SERVICE_BUS_BASE +
MSCH_DDRTIMING);
p_ddr_reg->noc.ddrmode = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRMODE);
p_ddr_reg->noc.readlatency = mmio_read_32(SERVICE_BUS_BASE +
MSCH_READLATENCY);
p_ddr_reg->noc.activate = mmio_read_32(SERVICE_BUS_BASE +
MSCH_ACTIVATE);
p_ddr_reg->noc.devtodev = mmio_read_32(SERVICE_BUS_BASE +
MSCH_DEVTODEV);
p_ddr_reg->pllselect = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) * 0x1;
p_ddr_reg->phypllockaddr = GRF_BASE + GRF_SOC_STATUS0;
p_ddr_reg->phyplllockmask = GRF_DDRPHY_LOCK;
p_ddr_reg->phyplllockval = 0;
/* PLLPD */
p_ddr_reg->pllpdstat = pllpdstat;
/* DPLL */
p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3);
/* slow mode and power on */
p_ddr_reg->dpllslowmode = DPLL_WORK_SLOW_MODE | DPLL_POWER_DOWN;
p_ddr_reg->dpllnormalmode = DPLL_WORK_NORMAL_MODE;
p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3);
p_ddr_reg->dpllreset = DPLL_RESET_CONTROL_NORMAL;
p_ddr_reg->dplldereset = DPLL_RESET_CONTROL_RESET;
p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0);
if (p_ddr_reg->pllselect == 0) {
p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 0))
& 0xffff) |
(0xFFFF << 16);
p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 1))
& 0xffff);
p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 2))
& 0xffff);
p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE +
PLL_CONS(DPLL_ID, 3))
& 0xffff) |
(0xFFFF << 16);
} else {
ddr_get_dpll_cfg(&p_ddr_reg->dpllcon[0]);
}
p_ddr_reg->pllselect = 0;
p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1);
p_ddr_reg->dplllockmask = DPLL_STATUS_LOCK;
p_ddr_reg->dplllockval = DPLL_STATUS_LOCK;
/* SET_DDR_PLL_SRC */
p_ddr_reg->ddrpllsrcdivaddr = CRU_BASE + CRU_CLKSELS_CON(13);
p_ddr_reg->ddrpllsrcdiv = (mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(13))
& DDR_PLL_SRC_MASK)
| (DDR_PLL_SRC_MASK << 16);
p_ddr_reg->retendisaddr = PMU_BASE + PMU_PWRMD_COM;
p_ddr_reg->retendisval = PD_PERI_PWRDN_ENABLE;
p_ddr_reg->grfregaddr = GRF_BASE + GRF_DDRC0_CON0;
p_ddr_reg->grfddrcreg = (mmio_read_32(GRF_BASE + GRF_DDRC0_CON0) &
DDR_PLL_SRC_MASK) |
(DDR_PLL_SRC_MASK << 16);
/* pctl phy soft reset */
p_ddr_reg->crupctlphysoftrstaddr = CRU_BASE + CRU_SOFTRSTS_CON(10);
p_ddr_reg->cruresetpctlphy = DDRCTRL0_PSRSTN_REQ(1) |
DDRCTRL0_SRSTN_REQ(1) |
DDRPHY0_PSRSTN_REQ(1) |
DDRPHY0_SRSTN_REQ(1);
p_ddr_reg->cruderesetphy = DDRCTRL0_PSRSTN_REQ(1) |
DDRCTRL0_SRSTN_REQ(1) |
DDRPHY0_PSRSTN_REQ(0) |
DDRPHY0_SRSTN_REQ(0);
p_ddr_reg->cruderesetpctlphy = DDRCTRL0_PSRSTN_REQ(0) |
DDRCTRL0_SRSTN_REQ(0) |
DDRPHY0_PSRSTN_REQ(0) |
DDRPHY0_SRSTN_REQ(0);
p_ddr_reg->physoftrstaddr = DDR_PHY_BASE + DDR_PHY_REG0;
p_ddr_reg->endtag = 0xFFFFFFFF;
}