static inline void uninit_pmu(void) { PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE); PPE_TC_PMU_SETUP(IFX_PMU_DISABLE); PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE); PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE); PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE); DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE); //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE); }
static inline void init_pmu(void) { //*PMU_PWDCR &= ~((1 << 29) | (1 << 22) | (1 << 21) | (1 << 19) | (1 << 18)); //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE); PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE); PPE_TC_PMU_SETUP(IFX_PMU_ENABLE); PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE); PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE); PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE); DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE); }
static inline void init_pmu(void) { //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9)); //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE); PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE); PPE_TC_PMU_SETUP(IFX_PMU_ENABLE); PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE); //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE); PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE); DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE); }
/** Hardware initilization */ void etop_hw_init(int mode) { unsigned int reg_val; #if defined(CONFIG_AMAZON_SE) int i; /** Turnoff the PPE */ ETOP_WRITE_REG32(0, ETOP_PPE32_BASE_ADDR); /*Reset PPE modue */ reg_val = ETOP_READ_REG32(IFX_RCU_RST_REQ); reg_val |= 0x100; ETOP_WRITE_REG32(reg_val, IFX_RCU_RST_REQ); for(i=0;i<100;i++) udelay(100); #endif /*CONFIG_AMAZON_SE*/ /* Enable PPE module from PMU*/ PPE_TPE_PMU_SETUP(IFX_PMU_MODULE_PPE_TPE); /* Enable EENET0 module from PMU */ PPE_ENET0_PMU_SETUP(IFX_PMU_MODULE_PPE_ENET0); switch(mode) { case REV_MII_MAC_MODE: reg_val = ETOP_READ_REG32(ETOP_CFG_REG); /*set interface is in off mode */ reg_val |= (CFG_OFF0); ETOP_WRITE_REG32(reg_val, ETOP_CFG_REG); /*Configure rev MII mode */ reg_val |= (CFG_REMII0); /*Disable turbo mode */ reg_val &= ~(CFG_TURBO0); /*set ENET1 interface is in off mode (Danube only)*/ reg_val |= CFG_OFF1; /*set ENET0 interface is in working mode */ reg_val &= ~(CFG_OFF0); ETOP_WRITE_REG32(reg_val, ETOP_CFG_REG); reg_val = ETOP_READ_REG32(ETOP_MDIO_CFG_REG); /*Disable Auto sending mode */ reg_val &= ~(MDIO_CFG_UMM0|MDIO_CFG_UMM1); ETOP_WRITE_REG32(reg_val, ETOP_MDIO_CFG_REG); printk("Selected REV MII MAC mode \n"); break; #if defined(CONFIG_AMAZON_SE) /*Danube does not supported */ case RED_MII_MAC_MODE: reg_val = ETOP_READ_REG32(ETOP_CFG_REG); /*set interface is in off mode */ reg_val |= (CFG_OFF0); ETOP_WRITE_REG32(reg_val, ETOP_CFG_REG); setRedMiiRefClk(); amazon_se_eth_gpio_configure(1); reg_val &= ~(CFG_INT_PHY); /* enable Reduced MII mode */ reg_val |= (CFG_RMII0); /*set ENET0 interface is in working mode */ reg_val &= ~(CFG_OFF0); ETOP_WRITE_REG32(reg_val, ETOP_CFG_REG); reg_val = ETOP_READ_REG32(ETOP_MDIO_CFG_REG); /*Disable Auto sensing mode */ reg_val &= ~(MDIO_CFG_UMM0); ETOP_WRITE_REG32(reg_val, ETOP_MDIO_CFG_REG); printk("Selected RED MII MAC mode \n"); break; case MII_PHY_MODE: /* Enable EPHY module from PMU */ EPHY_PMU_SETUP(IFX_PMU_MODULE_EPHY); reg_val = ETOP_READ_REG32(ETOP_CFG_REG); /*set interface is in off mode */ reg_val |= (CFG_OFF0); ETOP_WRITE_REG32(reg_val, ETOP_CFG_REG); /*clock from CGU */ setEphyClk(); reg_val = ETOP_READ_REG32(ETOP_CFG_REG); /*set interface is in working mode */ reg_val &= ~(CFG_OFF0); reg_val |= (CFG_INT_PHY); ETOP_WRITE_REG32(reg_val, ETOP_CFG_REG); reg_val = ETOP_READ_REG32(ETOP_MDIO_CFG_REG); /*Disable Auto sensing mode */ reg_val &= ~(MDIO_CFG_UMM0); ETOP_WRITE_REG32(reg_val, ETOP_MDIO_CFG_REG); /*Due to the bug in HW, need a delay*/ udelay(100); /*0x8 PHY address, 0x12 Class A phy register address, 0cc020 is data to write in Class A phy reg */ reg_val = MDIO_ACC_PHYA_SET(0x8)| MDIO_ACC_REGA_SET(0x12) |MDIO_ACC_PHYD(0xC020) | MDIO_ACC_RA; ETOP_WRITE_REG32(reg_val, ETOP_MDIO_ACC_REG); udelay(125); do { reg_val = ETOP_READ_REG32(ETOP_MDIO_ACC_REG); }while ( reg_val & MDIO_ACC_RA ) ; /*Reenable Auto sensing mode */ reg_val = ETOP_READ_REG32(ETOP_MDIO_CFG_REG); reg_val |= (MDIO_CFG_UMM0); ETOP_WRITE_REG32(reg_val, ETOP_MDIO_CFG_REG); printk("Selected EPHY mode \n"); break; #endif /* CONFIG_AMAZON_SE*/ } reg_val = ETOP_READ_REG32(ENET0_MAC_CFG_REG); /*Enable CRC generation*/ reg_val |= MAC_CFG_CGEN_SET(1); ETOP_WRITE_REG32(reg_val, ENET0_MAC_CFG_REG); reg_val = 0; /*Set frame over/under size frame length*/ reg_val = (IG_PLEN_CTRL_OVER(IFX_MAX_MTU)|IG_PLEN_CTRL_UNDER_SET(IFX_MIN_MTU)); ETOP_WRITE_REG32(reg_val, ETOP_IG_PLEN_CTRL_REG); }