void mdfld_panel_generic_dsi_dbi_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct drm_device *dev = encoder->dev;
struct drm_psb_private *dev_priv =
(struct drm_psb_private *)dev->dev_private;
struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
struct mdfld_dsi_config *dsi_config =
mdfld_dsi_encoder_get_config(dsi_encoder);
struct mdfld_dsi_connector *dsi_connector = dsi_config->connector;
int pipe = dsi_connector->pipe;
int err = 0;
PSB_DEBUG_ENTRY("type %s\n", (pipe == 2) ? "MIPI2" : "MIPI");
PSB_DEBUG_ENTRY("h %d v %d\n", mode->hdisplay, mode->vdisplay);
/* TODO: this looks ugly, try to move it to CRTC mode setting */
if (pipe == 2)
dev_priv->pipeconf2 |= PIPEACONF_DSR;
else
dev_priv->pipeconf |= PIPEACONF_DSR;
if (err)
DRM_ERROR("mode set failed\n");
else
PSB_DEBUG_ENTRY("mode set done successfully\n");
return;
}
void mdfld_dsi_dpi_set_color_mode(struct mdfld_dsi_config *dsi_config , bool on)
{
struct mdfld_dsi_pkg_sender *sender =
mdfld_dsi_get_pkg_sender(dsi_config);
int err;
u32 spk_pkg = (on == true) ? MDFLD_DSI_DPI_SPK_COLOR_MODE_ON :
MDFLD_DSI_DPI_SPK_COLOR_MODE_OFF;
PSB_DEBUG_ENTRY("Turn color mode %s pkg value= %d...\n",
(on ? "on" : "off"), spk_pkg);
if (!sender) {
DRM_ERROR("Failed to get DSI packet sender\n");
return ;
}
/*send turn on/off color mode packet*/
err = mdfld_dsi_send_dpi_spk_pkg_hs(sender,
spk_pkg);
if (err) {
DRM_ERROR("Failed to send turn on packet\n");
return ;
}
PSB_DEBUG_ENTRY("Turn color mode %s successful.\n",
(on ? "on" : "off"));
return;
}
static int
mdfld_h8c7_get_power_state(struct mdfld_dsi_config *dsi_config,
int pipe)
{
struct mdfld_dsi_hw_registers *regs;
struct mdfld_dsi_hw_context *ctx;
struct drm_device *dev;
int powerstatus = 0;
PSB_DEBUG_ENTRY("Getting power state...");
if (!dsi_config)
return -EINVAL;
regs = &dsi_config->regs;
ctx = &dsi_config->dsi_hw_context;
dev = dsi_config->dev;
/* for get date from panel side is not easy,
so here use display side setting to judge
wheather panel have enabled or not */
if ((REG_READ(regs->dpll_reg) & BIT31) &&
(REG_READ(regs->pipeconf_reg) & BIT30) &&
(REG_READ(regs->mipi_reg) & BIT31))
powerstatus = MDFLD_DSI_PANEL_POWER_ON;
else
powerstatus = MDFLD_DSI_PANEL_POWER_OFF;
PSB_DEBUG_ENTRY("Getting power state...%s",
powerstatus ? "OFF" : "ON");
return powerstatus;
}
static
void mdfld_dsi_dpi_dpms(struct drm_encoder *encoder, int mode)
{
struct mdfld_dsi_encoder *dsi_encoder;
struct mdfld_dsi_config *dsi_config;
struct drm_device *dev;
struct drm_psb_private *dev_priv;
if (!(drm_psb_use_cases_control & PSB_DPMS_ENABLE))
return;
dsi_encoder = MDFLD_DSI_ENCODER(encoder);
dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder);
dev = dsi_config->dev;
dev_priv = dev->dev_private;
PSB_DEBUG_ENTRY(
"%s\n", (mode == DRM_MODE_DPMS_ON ? "on" : "off"));
if (!gbdispstatus) {
PSB_DEBUG_ENTRY(
"panel in suspend status, skip turn on/off from DMPS");
return ;
}
mutex_lock(&dev_priv->dpms_mutex);
dev_priv->dpms_on_off = true;
if (mode == DRM_MODE_DPMS_ON)
mdfld_dsi_dpi_set_power(encoder, true);
else
mdfld_dsi_dpi_set_power(encoder, false);
dev_priv->dpms_on_off = false;
mutex_unlock(&dev_priv->dpms_mutex);
}
int mdfld_dsi_dsr_update_panel_fb(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_dsr *dsr;
struct mdfld_dsi_pkg_sender *sender;
int err = 0;
if (!dsi_config) {
DRM_ERROR("Invalid parameter\n");
return -EINVAL;
}
dsr = dsi_config->dsr;
if (!IS_ANN(dev)) {
/*if no dsr attached, return 0*/
if (!dsr)
return 0;
}
PSB_DEBUG_ENTRY("\n");
if (dsi_config->type == MDFLD_DSI_ENCODER_DPI)
return 0;
mutex_lock(&dsi_config->context_lock);
if (!dsi_config->dsi_hw_context.panel_on) {
PSB_DEBUG_ENTRY(
"if screen off, update fb is not allowed\n");
err = -EINVAL;
goto update_fb_out;
}
/*no pending fb updates, go ahead to send out write_mem_start*/
PSB_DEBUG_ENTRY("send out write_mem_start\n");
sender = mdfld_dsi_get_pkg_sender(dsi_config);
if (!sender) {
DRM_ERROR("No sender\n");
err = -EINVAL;
goto update_fb_out;
}
err = mdfld_dsi_send_dcs(sender, write_mem_start,
NULL, 0, CMD_DATA_SRC_PIPE,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("Failed to send write_mem_start");
err = -EINVAL;
goto update_fb_out;
}
/*clear free count*/
dsr->free_count = 0;
update_fb_out:
mutex_unlock(&dsi_config->context_lock);
return err;
}
int psb_set_brightness(struct backlight_device *bd)
{
struct drm_device *dev =
(struct drm_device *)bl_get_data(psb_backlight_device);
struct drm_psb_private *dev_priv =
(struct drm_psb_private *)dev->dev_private;
int level;
if (bd != NULL)
level = bd->props.brightness;
else
level = lastFailedBrightness;
DRM_DEBUG_DRIVER("backlight level set to %d\n", level);
PSB_DEBUG_ENTRY("[DISPLAY] %s: level is %d\n", __func__, level); //DIV5-MM-DISPLAY-NC-LCM_INIT-00
/* Perform value bounds checking */
if (level < BRIGHTNESS_MIN_LEVEL)
level = BRIGHTNESS_MIN_LEVEL;
lastFailedBrightness = -1;
if (IS_FLDS(dev)) {
u32 adjusted_level = 0;
/* Adjust the backlight level with the percent in
* dev_priv->blc_adj2;
*/
adjusted_level = level * dev_priv->blc_adj2;
adjusted_level = adjusted_level / BLC_ADJUSTMENT_MAX / 100;
dev_priv->brightness_adjusted = adjusted_level;
#ifndef CONFIG_MID_DSI_DPU
if (!(dev_priv->dsr_fb_update & MDFLD_DSR_MIPI_CONTROL)
&& (dev_priv->dbi_panel_on
|| dev_priv->dbi_panel_on2)) {
mdfld_dsi_dbi_exit_dsr(dev,
MDFLD_DSR_MIPI_CONTROL,
0, 0);
PSB_DEBUG_ENTRY
("Out of DSR before set brightness to %d.\n",
adjusted_level);
}
#endif
PSB_DEBUG_BL("Adjusted Backlight value: %d\n", adjusted_level);
mdfld_dsi_brightness_control(dev, 0, adjusted_level);
mdfld_dsi_brightness_control(dev, 2, adjusted_level);
}
/* cache the brightness for later use */
psb_brightness = level;
return 0;
}
/*
* Calculate the dpi time basing on a given drm mode @mode
* return 0 on success.
* FIXME: I was using proposed mode value for calculation, may need to
* use crtc mode values later
*/
int mdfld_dsi_dpi_timing_calculation(struct drm_display_mode *mode,
struct mdfld_dsi_dpi_timing *dpi_timing,
int num_lane, int bpp)
{
int pclk_hsync, pclk_hfp, pclk_hbp, pclk_hactive;
int pclk_vsync, pclk_vfp, pclk_vbp, pclk_vactive;
if(!mode || !dpi_timing) {
DRM_ERROR("Invalid parameter\n");
return -EINVAL;
}
PSB_DEBUG_ENTRY("pclk %d, hdisplay %d, hsync_start %d, hsync_end %d, htotal %d\n",
mode->clock, mode->hdisplay, mode->hsync_start,
mode->hsync_end, mode->htotal);
PSB_DEBUG_ENTRY("vdisplay %d, vsync_start %d, vsync_end %d, vtotal %d\n",
mode->vdisplay, mode->vsync_start,
mode->vsync_end, mode->vtotal);
pclk_hactive = mode->hdisplay;
pclk_hfp = mode->hsync_start - mode->hdisplay;
pclk_hsync = mode->hsync_end - mode->hsync_start;
pclk_hbp = mode->htotal - mode->hsync_end;
pclk_vactive = mode->vdisplay;
pclk_vfp = mode->vsync_start - mode->vdisplay;
pclk_vsync = mode->vsync_end - mode->vsync_start;
pclk_vbp = mode->vtotal - mode->vsync_end;
/*
* byte clock counts were calculated by following formula
* bclock_count = pclk_count * bpp / num_lane / 8
*/
dpi_timing->hsync_count = mdfld_dsi_dpi_to_byte_clock_count(pclk_hsync, num_lane, bpp);
dpi_timing->hbp_count = mdfld_dsi_dpi_to_byte_clock_count(pclk_hbp, num_lane, bpp);
dpi_timing->hfp_count = mdfld_dsi_dpi_to_byte_clock_count(pclk_hfp, num_lane, bpp);
dpi_timing->hactive_count = mdfld_dsi_dpi_to_byte_clock_count(pclk_hactive, num_lane, bpp);
dpi_timing->vsync_count = mdfld_dsi_dpi_to_byte_clock_count(pclk_vsync, num_lane, bpp);
dpi_timing->vbp_count = mdfld_dsi_dpi_to_byte_clock_count(pclk_vbp, num_lane, bpp);
dpi_timing->vfp_count = mdfld_dsi_dpi_to_byte_clock_count(pclk_vfp, num_lane, bpp);
PSB_DEBUG_ENTRY("DPI timings: %d, %d, %d, %d, %d, %d, %d\n",
dpi_timing->hsync_count, dpi_timing->hbp_count,
dpi_timing->hfp_count, dpi_timing->hactive_count,
dpi_timing->vsync_count, dpi_timing->vbp_count,
dpi_timing->vfp_count);
return 0;
}
/**
* init dsr structure
*/
int mdfld_dsi_dsr_init(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_dsr *dsr;
PSB_DEBUG_ENTRY("\n");
if (!dsi_config) {
DRM_ERROR("Invalid parameter\n");
return -EINVAL;
}
/*check panel type*/
if (dsi_config->type == MDFLD_DSI_ENCODER_DPI) {
DRM_INFO("%s: Video mode panel, disabling DSR\n", __func__);
return 0;
}
dsr = kzalloc(sizeof(struct mdfld_dsi_dsr), GFP_KERNEL);
if (!dsr) {
DRM_ERROR("No memory\n");
return -ENOMEM;
}
/*init reference count*/
dsr->ref_count = 0;
/*init free count*/
dsr->free_count = 0;
/*init dsr enabled*/
dsr->dsr_enabled = 0;
/*set dsr state*/
dsr->dsr_state = DSR_INIT;
/*init power on/off works*/
INIT_WORK(&dsr->power_off_work, dsr_power_off_work);
INIT_WORK(&dsr->power_on_work, dsr_power_on_work);
/*init dsi config*/
dsr->dsi_config = dsi_config;
dsi_config->dsr = dsr;
PSB_DEBUG_ENTRY("successfully\n");
return 0;
}
static struct drm_display_mode *sharp5_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 1080;
mode->hsync_start = 1168;
mode->hsync_end = 1200;
mode->htotal = 1496;
mode->vdisplay = 1920;
mode->vsync_start = 1923;
mode->vsync_end = 1926;
mode->vtotal = 1987;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal * mode->htotal / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
static void sharp5_cmd_controller_init(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_hw_context *hw_ctx =
&dsi_config->dsi_hw_context;
PSB_DEBUG_ENTRY("\n");
/*reconfig lane configuration*/
dsi_config->lane_count = 4;
dsi_config->lane_config = MDFLD_DSI_DATA_LANE_4_0;
hw_ctx->cck_div = 1;
hw_ctx->pll_bypass_mode = 0;
hw_ctx->mipi_control = 0x0;
hw_ctx->intr_en = 0xFFFFFFFF;
hw_ctx->hs_tx_timeout = 0xFFFFFF;
hw_ctx->lp_rx_timeout = 0xFFFFFF;
hw_ctx->device_reset_timer = 0xffff;
hw_ctx->turn_around_timeout = 0x14;
hw_ctx->high_low_switch_count = 0x2B;
hw_ctx->clk_lane_switch_time_cnt = 0x2b0014;
hw_ctx->lp_byteclk = 0x6;
hw_ctx->dphy_param = 0x2a18681f;
hw_ctx->eot_disable = 0x0;
hw_ctx->init_count = 0xf0;
hw_ctx->dbi_bw_ctrl = 1100;
hw_ctx->hs_ls_dbi_enable = 0x0;
hw_ctx->dsi_func_prg = ((DBI_DATA_WIDTH_OPT2 << 13) |
dsi_config->lane_count);
hw_ctx->mipi = PASS_FROM_SPHY_TO_AFE |
BANDGAP_CHICKEN_BIT |
TE_TRIGGER_GPIO_PIN;
hw_ctx->video_mode_format = 0xf;
}
int mdfld_dbi_dpu_init(struct drm_device * dev)
{
struct drm_psb_private * dev_priv = dev->dev_private;
struct mdfld_dbi_dpu_info * dpu_info = dev_priv->dbi_dpu_info;
if(!dpu_info || IS_ERR(dpu_info)) {
dpu_info = kzalloc(sizeof(struct mdfld_dbi_dpu_info), GFP_KERNEL);
if(!dpu_info) {
DRM_ERROR("No memory\n");
return -ENOMEM;
}
dev_priv->dbi_dpu_info = dpu_info;
}
dpu_info->dev = dev;
dpu_info->cursors[0].size = MDFLD_CURSOR_SIZE;
dpu_info->cursors[1].size = MDFLD_CURSOR_SIZE;
/*init dpu_update_lock*/
spin_lock_init(&dpu_info->dpu_update_lock);
/*init dpu refresh timer*/
mdfld_dbi_dpu_timer_init(dev, dpu_info);
/*init pipe damage area*/
mdfld_dpu_init_damage(dpu_info, 0);
mdfld_dpu_init_damage(dpu_info, 2);
PSB_DEBUG_ENTRY("successfully\n");
return 0;
}
static
bool mdfld_generic_dsi_dbi_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
struct mdfld_dsi_dbi_output *dbi_output =
MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
struct drm_display_mode *fixed_mode = dbi_output->panel_fixed_mode;
PSB_DEBUG_ENTRY("\n");
if (fixed_mode) {
adjusted_mode->hdisplay = fixed_mode->hdisplay;
adjusted_mode->hsync_start = fixed_mode->hsync_start;
adjusted_mode->hsync_end = fixed_mode->hsync_end;
adjusted_mode->htotal = fixed_mode->htotal;
adjusted_mode->vdisplay = fixed_mode->vdisplay;
adjusted_mode->vsync_start = fixed_mode->vsync_start;
adjusted_mode->vsync_end = fixed_mode->vsync_end;
adjusted_mode->vtotal = fixed_mode->vtotal;
adjusted_mode->clock = fixed_mode->clock;
drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
}
return true;
}
static
void mdfld_generic_dsi_dbi_restore(struct drm_encoder *encoder)
{
struct mdfld_dsi_encoder *dsi_encoder;
struct mdfld_dsi_config *dsi_config;
struct drm_device *dev;
int pipe;
PSB_DEBUG_ENTRY("\n");
if (!encoder)
return;
dsi_encoder = MDFLD_DSI_ENCODER(encoder);
dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder);
dev = dsi_config->dev;
pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder);
DCLockMutex();
mdfld_generic_dsi_dbi_set_power(encoder, true);
DCAttachPipe(pipe);
DC_MRFLD_onPowerOn(pipe);
DCUnLockMutex();
}
static
void mdfld_generic_dsi_dbi_save(struct drm_encoder *encoder)
{
struct mdfld_dsi_encoder *dsi_encoder;
struct mdfld_dsi_config *dsi_config;
struct drm_device *dev;
int pipe;
PSB_DEBUG_ENTRY("\n");
if (!encoder)
return;
dsi_encoder = MDFLD_DSI_ENCODER(encoder);
dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder);
dev = dsi_config->dev;
pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder);
DCLockMutex();
mdfld_generic_dsi_dbi_set_power(encoder, false);
drm_handle_vblank(dev, pipe);
/* Turn off vsync (TE) interrupt. */
drm_vblank_off(dev, pipe);
/* Make the pending flip request as completed. */
DCUnAttachPipe(pipe);
DC_MRFLD_onPowerOff(pipe);
DCUnLockMutex();
}
static int mdfld_dsi_sharp25x16_set_brightness(struct mdfld_dsi_config *dsi_config,
int level)
{
struct mdfld_dsi_pkg_sender *sender =
mdfld_dsi_get_pkg_sender(dsi_config);
struct drm_device *dev = dsi_config->dev;
u8 duty_val = 0;
PSB_DEBUG_ENTRY("level = %d\n", level);
if (!sender) {
DRM_ERROR("Failed to get DSI packet sender\n");
return -EINVAL;
}
duty_val = (0xFF * level) / 255;
if (duty_val < 12)
duty_val = 0;
sharp_set_brightness[2] = duty_val;
mdfld_dsi_send_gen_long_hs(sender, sharp_set_brightness,
3,
MDFLD_DSI_SEND_PACKAGE);
REG_WRITE(MIPIA_HS_GEN_CTRL_REG, 5);
return 0;
}
static
int mdfld_dsi_h8c7_cmd_panel_reset(struct mdfld_dsi_config *dsi_config)
{
static int mipi_reset_gpio;
int ret = 0;
PSB_DEBUG_ENTRY("\n");
if (mipi_reset_gpio == 0) {
ret = get_gpio_by_name("mipi-reset");
if (ret < 0) {
DRM_ERROR("Faild to get panel reset gpio, " \
"use default reset pin\n");
ret = 128;
}
mipi_reset_gpio = ret;
ret = gpio_request(mipi_reset_gpio, "mipi_display");
if (ret) {
DRM_ERROR("Faild to request panel reset gpio\n");
return -EINVAL;
}
gpio_direction_output(mipi_reset_gpio, 0);
}
gpio_set_value_cansleep(mipi_reset_gpio, 0);
mdelay(11);
gpio_set_value_cansleep(mipi_reset_gpio, 1);
mdelay(5);
return 0;
}
static
struct drm_display_mode *jdi25x16_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 2560;
mode->hsync_start = mode->hdisplay + 160;
mode->hsync_end = mode->hsync_start + 24;
mode->htotal = mode->hsync_end + 56;
mode->vdisplay = 1600;
mode->vsync_start = mode->vdisplay + 12;
mode->vsync_end = mode->vsync_start + 4;
mode->vtotal = mode->vsync_end + 4;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
static
void jdi25x16_cmd_controller_init(
struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_hw_context *hw_ctx =
&dsi_config->dsi_hw_context;
PSB_DEBUG_ENTRY("\n");
/*reconfig lane configuration*/
dsi_config->lane_count = 4;
dsi_config->lane_config = MDFLD_DSI_DATA_LANE_4_0;
hw_ctx->cck_div = 1;
hw_ctx->pll_bypass_mode = 0;
hw_ctx->mipi_control = 0x0;
hw_ctx->intr_en = 0xFFFFFFFF;
hw_ctx->hs_tx_timeout = 0xFFFFFF;
hw_ctx->lp_rx_timeout = 0xFFFFFF;
hw_ctx->device_reset_timer = 0xffff;
hw_ctx->turn_around_timeout = 0x14;
hw_ctx->high_low_switch_count = 0x2b;
hw_ctx->clk_lane_switch_time_cnt = 0x2b0014;
hw_ctx->lp_byteclk = 0x6;
hw_ctx->dphy_param = 0x2a18681f;
hw_ctx->eot_disable = 0x0;
hw_ctx->init_count = 0xf0;
hw_ctx->dbi_bw_ctrl = 1024;
hw_ctx->hs_ls_dbi_enable = 0x0;
hw_ctx->dsi_func_prg = ((DBI_DATA_WIDTH_OPT2 << 13) |
dsi_config->lane_count);
hw_ctx->mipi = SEL_FLOPPED_HSTX | PASS_FROM_SPHY_TO_AFE |
DUAL_LINK_ENABLE | DUAL_LINK_CAPABLE;
hw_ctx->video_mode_format = 0xf;
}
static int __dpi_enter_ulps_locked(struct mdfld_dsi_config *dsi_config, int offset)
{
struct mdfld_dsi_hw_registers *regs = &dsi_config->regs;
struct mdfld_dsi_hw_context *ctx = &dsi_config->dsi_hw_context;
struct drm_device *dev = dsi_config->dev;
struct mdfld_dsi_pkg_sender *sender
= mdfld_dsi_get_pkg_sender(dsi_config);
if (!sender) {
DRM_ERROR("pkg sender is NULL\n");
return -EINVAL;
}
ctx->device_ready = REG_READ(regs->device_ready_reg + offset);
if (ctx->device_ready & DSI_POWER_STATE_ULPS_MASK) {
DRM_ERROR("Broken ULPS states\n");
return -EINVAL;
}
/*wait for all FIFOs empty*/
mdfld_dsi_wait_for_fifos_empty(sender);
/*inform DSI host is to be put on ULPS*/
ctx->device_ready |= DSI_POWER_STATE_ULPS_ENTER;
REG_WRITE(regs->device_ready_reg + offset, ctx->device_ready);
PSB_DEBUG_ENTRY("entered ULPS state\n");
return 0;
}
static struct drm_display_mode *smd_qhd_amoled_cmd_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 540;
mode->vdisplay = 960;
/* HFP = 90, HSYNC = 10, HBP = 20 */
mode->hsync_start = mode->hdisplay + 90;
mode->hsync_end = mode->hsync_start + 10;
mode->htotal = mode->hsync_end + 20;
/* VFP = 4, VSYNC = 2, VBP = 4 */
mode->vsync_start = mode->vdisplay + 4;
mode->vsync_end = mode->vsync_start + 2;
mode->vtotal = mode->vsync_end + 4;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * (mode->vtotal + 1) *
(mode->htotal + 1) / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
int mdfld_dsi_sharp25x16_ic_init(struct mdfld_dsi_config *dsi_config)
{
struct mdfld_dsi_pkg_sender *sender
= mdfld_dsi_get_pkg_sender(dsi_config);
struct drm_device *dev = dsi_config->dev;
int err = 0;
int i;
PSB_DEBUG_ENTRY("\n");
if (!sender) {
DRM_ERROR("Cannot get sender\n");
return -EINVAL;
}
for (i = 0; i < 7; i++) {
err = mdfld_dsi_send_gen_long_hs(sender, sharp_mode_set_data[i],
3,
MDFLD_DSI_SEND_PACKAGE);
if (err) {
DRM_ERROR("%s: %d: Set Mode data\n", __func__, __LINE__);
goto ic_init_err;
}
REG_WRITE(MIPIA_HS_GEN_CTRL_REG, 5);
}
return 0;
ic_init_err:
err = -EIO;
return err;
}
struct drm_display_mode *pr2_vid_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 800;
mode->vdisplay = 1024;
mode->hsync_start = 823;
mode->hsync_end = 831;
mode->htotal = 847;
mode->vsync_start = 1031;
mode->vsync_end = 1033;
mode->vtotal = 1035;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
mode->type |= DRM_MODE_TYPE_PREFERRED;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
return mode;
}
static
bool mdfld_dsi_dpi_mode_fixup(struct drm_encoder *encoder,
const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
struct mdfld_dsi_config *dsi_config =
mdfld_dsi_encoder_get_config(dsi_encoder);
struct drm_display_mode *fixed_mode;
if (!dsi_config) {
DRM_ERROR("dsi_config is NULL\n");
return;
}
fixed_mode = dsi_config->fixed_mode;
PSB_DEBUG_ENTRY("\n");
if (fixed_mode) {
adjusted_mode->hdisplay = fixed_mode->hdisplay;
adjusted_mode->hsync_start = fixed_mode->hsync_start;
adjusted_mode->hsync_end = fixed_mode->hsync_end;
adjusted_mode->htotal = fixed_mode->htotal;
adjusted_mode->vdisplay = fixed_mode->vdisplay;
adjusted_mode->vsync_start = fixed_mode->vsync_start;
adjusted_mode->vsync_end = fixed_mode->vsync_end;
adjusted_mode->vtotal = fixed_mode->vtotal;
adjusted_mode->clock = fixed_mode->clock;
drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
}
return true;
}
static int mdfld_dsi_sharp25x16_panel_reset(struct mdfld_dsi_config *dsi_config)
{
int ret = 0;
PSB_DEBUG_ENTRY("\n");
msleep(10);
if (mipi_reset_gpio == 0) {
ret = get_gpio_by_name("disp0_rst");
if (ret < 0) {
DRM_ERROR("Faild to get panel reset gpio, " \
"use default reset pin\n");
return 0;
}
mipi_reset_gpio = ret;
ret = gpio_request(mipi_reset_gpio, "mipi_display");
if (ret) {
DRM_ERROR("Faild to request panel reset gpio\n");
return 0;
}
}
gpio_direction_output(mipi_reset_gpio, 0);
usleep_range(1000, 1500);
gpio_set_value_cansleep(mipi_reset_gpio, 1);
return 0;
}
static
int jdi25x16_cmd_set_brightness(
struct mdfld_dsi_config *dsi_config,
int level)
{
struct mdfld_dsi_pkg_sender *sender =
mdfld_dsi_get_pkg_sender(dsi_config);
u8 duty_val = 0;
int i;
PSB_DEBUG_ENTRY("level = %d\n", level);
if (!sender) {
DRM_ERROR("Failed to get DSI packet sender\n");
return -EINVAL;
}
duty_val = (0xFF * level) / 255;
for (i = 0; i < 2; i++) {
if (i == 0)
sender->work_for_slave_panel = false;
else
sender->work_for_slave_panel = true;
/*
* Set maximum brightness here. AOB needs to be modified
* to get real brightness setting
*/
mdfld_dsi_send_mcs_short_hs(sender,
write_display_brightness, 0x90, 1,
MDFLD_DSI_SEND_PACKAGE);
}
sender->work_for_slave_panel = false;
return 0;
}
static
void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
struct mdfld_dsi_config *dsi_config =
mdfld_dsi_encoder_get_config(dsi_encoder);
int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder);
PSB_DEBUG_ENTRY("set mode %dx%d on pipe %d",
mode->hdisplay, mode->vdisplay, pipe);
/**
* if TMD panel call new power on/off sequences instead.
* NOTE: refine TOSHIBA panel code later
*/
if (!dsi_config) {
DRM_ERROR("Invalid dsi config\n");
return NULL;
}
__mdfld_dsi_dpi_set_timing(dsi_config, mode, adjusted_mode);
}
void jdi25x16_cmd_init(struct drm_device *dev,
struct panel_funcs *p_funcs)
{
if (!dev || !p_funcs) {
DRM_ERROR("Invalid parameters\n");
return;
}
PSB_DEBUG_ENTRY("\n");
p_funcs->reset = jdi25x16_cmd_panel_reset;
p_funcs->power_on = jdi25x16_cmd_power_on;
p_funcs->power_off = jdi25x16_cmd_power_off;
p_funcs->drv_ic_init = jdi25x16_cmd_drv_ic_init;
p_funcs->get_config_mode = jdi25x16_cmd_get_config_mode;
p_funcs->get_panel_info = jdi25x16_cmd_get_panel_info;
p_funcs->dsi_controller_init =
jdi25x16_cmd_controller_init;
p_funcs->detect =
jdi25x16_cmd_panel_connection_detect;
p_funcs->set_brightness =
jdi25x16_cmd_set_brightness;
p_funcs->exit_deep_standby =
jdi25x16_cmd_exit_deep_standby;
p_funcs->drv_set_panel_mode = jdi25x16_cmd_set_mode;
}
static struct drm_display_mode *jdi_vid_get_config_mode(void)
{
struct drm_display_mode *mode;
PSB_DEBUG_ENTRY("\n");
mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
return NULL;
mode->hdisplay = 720;
mode->hsync_start = 816;
mode->hsync_end = 818;
mode->htotal = 920;
mode->vdisplay = 1280;
mode->vsync_start = 1288;
mode->vsync_end = 1296;
mode->vtotal = 1304;
mode->vrefresh = 60;
mode->clock = mode->vrefresh * mode->vtotal *
mode->htotal / 1000;
drm_mode_set_name(mode);
drm_mode_set_crtcinfo(mode, 0);
mode->type |= DRM_MODE_TYPE_PREFERRED;
return mode;
}
/**
* mid_hdmi_audio_get_caps:
* used to return the HDMI audio capabilities.
* e.g. resolution, frame rate.
*/
static int mid_hdmi_audio_get_caps(
enum had_caps_list get_element,
void *capabilities)
{
struct drm_device *dev = hdmi_priv->dev;
int ret = 0;
PSB_DEBUG_ENTRY("\n");
switch (get_element) {
case HAD_GET_ELD:
ret = android_hdmi_get_eld(dev, capabilities);
break;
case HAD_GET_SAMPLING_FREQ:
{
uint32_t val;
val = android_hdmi_get_dpll_clock(dev);
memcpy(capabilities, &val, sizeof(uint32_t));
break;
}
default:
break;
}
return ret;
}
static bool pyr_dsi_dbi_mode_fixup(struct drm_encoder * encoder,
struct drm_display_mode * mode,
struct drm_display_mode * adjusted_mode)
{
struct drm_device* dev = encoder->dev;
struct drm_display_mode * fixed_mode = pyr_cmd_get_config_mode(dev);
PSB_DEBUG_ENTRY("\n");
if(fixed_mode) {
adjusted_mode->hdisplay = fixed_mode->hdisplay;
adjusted_mode->hsync_start = fixed_mode->hsync_start;
adjusted_mode->hsync_end = fixed_mode->hsync_end;
adjusted_mode->htotal = fixed_mode->htotal;
adjusted_mode->vdisplay = fixed_mode->vdisplay;
adjusted_mode->vsync_start = fixed_mode->vsync_start;
adjusted_mode->vsync_end = fixed_mode->vsync_end;
adjusted_mode->vtotal = fixed_mode->vtotal;
adjusted_mode->clock = fixed_mode->clock;
drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
kfree(fixed_mode);
}
return true;
}