/** * Initialize a BAM pipe */ int bam_pipe_init(void *base, u32 pipe, struct bam_pipe_parameters *param, u32 ee) { /* Reset the BAM pipe */ bam_write_reg(base, P_RST(pipe), 1); /* No delay needed */ bam_write_reg(base, P_RST(pipe), 0); /* Enable the Pipe Interrupt at the BAM level */ bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 1); bam_write_reg(base, P_IRQ_EN(pipe), param->pipe_irq_mask); bam_write_reg_field(base, P_CTRL(pipe), P_DIRECTION, param->dir); bam_write_reg_field(base, P_CTRL(pipe), P_SYS_MODE, param->mode); bam_write_reg(base, P_EVNT_GEN_TRSHLD(pipe), param->event_threshold); bam_write_reg(base, P_DESC_FIFO_ADDR(pipe), param->desc_base); bam_write_reg_field(base, P_FIFO_SIZES(pipe), P_DESC_FIFO_SIZE, param->desc_size); bam_write_reg_field(base, P_CTRL(pipe), P_SYS_STRM, param->stream_mode); if (param->mode == BAM_PIPE_MODE_BAM2BAM) { u32 peer_dest_addr = param->peer_phys_addr + P_EVNT_REG(param->peer_pipe); bam_write_reg(base, P_DATA_FIFO_ADDR(pipe), param->data_base); bam_write_reg_field(base, P_FIFO_SIZES(pipe), P_DATA_FIFO_SIZE, param->data_size); bam_write_reg(base, P_EVNT_DEST_ADDR(pipe), peer_dest_addr); SPS_DBG2("sps:bam=0x%x(va).pipe=%d.peer_bam=0x%x." "peer_pipe=%d.\n", (u32) base, pipe, (u32) param->peer_phys_addr, param->peer_pipe); } /* Pipe Enable - at last */ bam_write_reg_field(base, P_CTRL(pipe), P_EN, 1); return 0; }
/** * Initialize a BAM pipe */ int bam_pipe_init(void *base, u32 pipe, struct bam_pipe_parameters *param, u32 ee) { SPS_DBG2("sps:%s:bam=0x%x(va).pipe=%d.", __func__, (u32) base, pipe); /* Reset the BAM pipe */ bam_write_reg(base, P_RST(pipe), 1); /* No delay needed */ bam_write_reg(base, P_RST(pipe), 0); /* Enable the Pipe Interrupt at the BAM level */ bam_write_reg_field(base, IRQ_SRCS_MSK_EE(ee), (1 << pipe), 1); bam_write_reg(base, P_IRQ_EN(pipe), param->pipe_irq_mask); bam_write_reg_field(base, P_CTRL(pipe), P_DIRECTION, param->dir); bam_write_reg_field(base, P_CTRL(pipe), P_SYS_MODE, param->mode); bam_write_reg(base, P_EVNT_GEN_TRSHLD(pipe), param->event_threshold); bam_write_reg(base, P_DESC_FIFO_ADDR(pipe), param->desc_base); bam_write_reg_field(base, P_FIFO_SIZES(pipe), P_DESC_FIFO_SIZE, param->desc_size); bam_write_reg_field(base, P_CTRL(pipe), P_SYS_STRM, param->stream_mode); #ifdef CONFIG_SPS_SUPPORT_NDP_BAM bam_write_reg_field(base, P_CTRL(pipe), P_LOCK_GROUP, param->lock_group); SPS_DBG("sps:bam=0x%x(va).pipe=%d.lock_group=%d.\n", (u32) base, pipe, param->lock_group); #endif if (param->mode == BAM_PIPE_MODE_BAM2BAM) { u32 peer_dest_addr = param->peer_phys_addr + P_EVNT_REG(param->peer_pipe); bam_write_reg(base, P_DATA_FIFO_ADDR(pipe), param->data_base); bam_write_reg_field(base, P_FIFO_SIZES(pipe), P_DATA_FIFO_SIZE, param->data_size); bam_write_reg(base, P_EVNT_DEST_ADDR(pipe), peer_dest_addr); SPS_DBG2("sps:bam=0x%x(va).pipe=%d.peer_bam=0x%x." "peer_pipe=%d.\n", (u32) base, pipe, (u32) param->peer_phys_addr, param->peer_pipe); #ifdef CONFIG_SPS_SUPPORT_NDP_BAM bam_write_reg_field(base, P_CTRL(pipe), P_WRITE_NWD, param->write_nwd); SPS_DBG("sps:%s WRITE_NWD bit for this bam2bam pipe.", param->write_nwd ? "Set" : "Do not set"); #endif } /* Pipe Enable - at last */ bam_write_reg_field(base, P_CTRL(pipe), P_EN, 1); return 0; }