/**
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
bitwise inclusive OR, and writes the result back to the bit field in the
16-bit port.
Reads the 16-bit PCI configuration register specified by Address, performs a
bitwise AND followed by a bitwise inclusive OR between the read result and
the value specified by AndData, and writes the result to the 16-bit PCI
configuration register specified by Address. The value written to the PCI
configuration register is returned. This function must guarantee that all PCI
read and write operations are serialized. Extra left bits in both AndData and
OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
PciBitFieldAndThenOr16 (
IN UINTN Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 AndData,
IN UINT16 OrData
)
{
return PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);
}
/**
Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
bitwise OR, and writes the result back to the bit field in the
16-bit port.
Reads the 16-bit PCI configuration register specified by Address, performs a
bitwise AND followed by a bitwise OR between the read result and
the value specified by AndData, and writes the result to the 16-bit PCI
configuration register specified by Address. The value written to the PCI
configuration register is returned. This function must guarantee that all PCI
read and write operations are serialized. Extra left bits in both AndData and
OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
@param Address The PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
PciBitFieldAndThenOr16 (
IN UINTN Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 AndData,
IN UINT16 OrData
)
{
return mRunningOnQ35 ?
PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData) :
PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);
}