AGESA_STATUS
STATIC
PcieMapPortsPciAddresses (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
PCIe_WRAPPER_CONFIG *WrapperList;
PCIe_ENGINE_CONFIG *EngineList;
AgesaStatus = AGESA_SUCCESS;
WrapperList = PcieConfigGetChildWrapper (Silicon);
while (WrapperList != NULL) {
EngineList = PcieConfigGetChildEngine (WrapperList);
while (EngineList != NULL) {
if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
Status = PcieFmMapPortPciAddress (EngineList);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO (
0,
Silicon->Address.Address.Bus,
EngineList->Type.Port.PortData.DeviceNumber,
EngineList->Type.Port.PortData.FunctionNumber,
0
);
} else {
EngineList->Type.Port.PortData.PortPresent = OFF;
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to allocate PCI address for PCIe port\n"
);
//Report error
PutEventLog (
AGESA_ERROR,
GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION,
EngineList->Type.Port.PortData.DeviceNumber,
0,
0,
0,
GnbLibGetHeader (Pcie)
);
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
return AgesaStatus;
}
VOID
PcieSiliconHidePorts (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0x64_x0C_STRUCT D0F0x64_x0C;
PCIe_WRAPPER_CONFIG *WrapperList;
D0F0x64_x0C.Value = 0;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Enter\n");
D0F0x64_x0C.Value = BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7;
WrapperList = PcieConfigGetChildWrapper (Silicon);
while (WrapperList != NULL) {
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieConfigGetChildEngine (WrapperList);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
if (PcieConfigIsActivePcieEngine (EngineList) && !PcieConfigIsSbPcieEngine (EngineList)) {
D0F0x64_x0C.Value &= ~(1 << EngineList->Type.Port.Address.Address.Device);
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
(UINT32)~(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
D0F0x64_x0C.Value,
GnbLibGetHeader (Pcie)
);
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
(UINT32)~BIT6,
0x0,
GnbLibGetHeader (Pcie)
);
IDS_HDT_CONSOLE (GNB_TRACE, "Write D0F0x64_x0C.Value = %x\n", D0F0x64_x0C.Value);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieSiliconHidePorts Exit\n");
}
VOID
STATIC
GnbIommuMidInitCheckGfxPciePorts (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_WRAPPER_CONFIG *WrapperList;
BOOLEAN GfxPciePortUsed;
D0F2xF4_x57_STRUCT D0F2xF4_x57;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Enter\n");
GfxPciePortUsed = FALSE;
WrapperList = PcieConfigGetChildWrapper (Pcie);
ASSERT (WrapperList != NULL);
if (WrapperList->WrapId == GFX_WRAP_ID) {
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieConfigGetChildEngine (WrapperList);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
IDS_HDT_CONSOLE (GNB_TRACE, "Checking Gfx ports device number %x\n", EngineList->Type.Port.NativeDevNumber);
if (PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard))) {
// GFX PCIe ports beeing used
GfxPciePortUsed = TRUE;
IDS_HDT_CONSOLE (GNB_TRACE, "GFX PCIe ports beeing used\n");
break;
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
}
if (!GfxPciePortUsed) {
//D0F2xF4_x57.Field.L1ImuPcieGfxDis needs to be set
GnbRegisterReadTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, 0, GnbLibGetHeader (Pcie));
D0F2xF4_x57.Field.L1ImuPcieGfxDis = 1;
GnbRegisterWriteTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Exit\n");
}
AGESA_STATUS
PcieMapTopologyOnComplex (
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
IN PCIe_COMPLEX_CONFIG *Complex,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *Silicon;
PCIe_WRAPPER_CONFIG *Wrapper;
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n");
Silicon = PcieConfigGetChildSilicon (Complex);
while (Silicon != NULL) {
Wrapper = PcieConfigGetChildWrapper (Silicon);
while (Wrapper != NULL) {
Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_ERROR) {
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n",
PcieFmDebugGetWrapperNameString (Wrapper)
);
ASSERT (FALSE);
}
Wrapper = PcieLibGetNextDescriptor (Wrapper);
}
Status = PcieMapPortsPciAddresses (Silicon, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Silicon = PcieLibGetNextDescriptor (Silicon);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* Helper function to dump configuration to debug out
*
*
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieConfigDebugDump (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *SiliconList;
PCIe_WRAPPER_CONFIG *WrapperList;
PCIe_COMPLEX_CONFIG *ComplexList;
ComplexList = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header);
IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start------------>\n");
IDS_HDT_CONSOLE (PCIE_MISC, " PSPP Policy - %s\n",
(Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" :
(Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : (
(Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : (
(Pcie->PsppPolicy == PsppPerformance) ? "Performance" : (
(Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown")))
);
IDS_HDT_CONSOLE (PCIE_MISC, " GFX Workaround - %s\n",
(Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled"
);
IDS_HDT_CONSOLE (PCIE_MISC, " LinkL0Pooling - %dus\n",
Pcie->LinkL0Pooling
);
IDS_HDT_CONSOLE (PCIE_MISC, " LinkGpioResetAssertionTime - %dus\n",
Pcie->LinkGpioResetAssertionTime
);
IDS_HDT_CONSOLE (PCIE_MISC, " LinkReceiverDetectionPooling - %dus\n",
Pcie->LinkReceiverDetectionPooling
);
IDS_HDT_CONSOLE (PCIE_MISC, " Training Algorythm - %s\n",
(Pcie->TrainingAlgorithm == PcieTrainingStandard) ? "PcieTrainingStandard" : (
(Pcie->TrainingAlgorithm == PcieTrainingDistributed) ? "PcieTrainingDistributed" : "Unknown")
);
while (ComplexList != NULL) {
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config Start ---------->\n");
IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", ComplexList->Header.DescriptorFlags);
IDS_HDT_CONSOLE (PCIE_MISC, " Socket ID - %d\n", ComplexList->SocketId);
SiliconList = PcieConfigGetChildSilicon (ComplexList);
while (SiliconList != NULL) {
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config Start -------->\n");
IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", SiliconList->Header.DescriptorFlags);
IDS_HDT_CONSOLE (PCIE_MISC, " Silicon ID - %d\n", SiliconList->SiliconId);
IDS_HDT_CONSOLE (PCIE_MISC, " Node ID - %d\n", SiliconList->NodeId);
IDS_HDT_CONSOLE (PCIE_MISC, " Host PCI Address - %d:%d:%d\n",
SiliconList->Address.Address.Bus,
SiliconList->Address.Address.Device,
SiliconList->Address.Address.Function
);
WrapperList = PcieConfigGetChildWrapper (SiliconList);
while (WrapperList != NULL) {
PcieConfigWrapperDebugDump (WrapperList);
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config End ---------->\n");
SiliconList = PcieLibGetNextDescriptor (SiliconList);
}
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config End ------------>\n");
ComplexList = PcieLibGetNextDescriptor (ComplexList);
}
IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End-------------->\n");
}
