AGESA_STATUS
PcieConfigRunProcForAllWrappers (
IN UINT32 DescriptorFlags,
IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_WRAPPER_CONFIG *Wrapper;
AgesaStatus = AGESA_SUCCESS;
Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header);
while (Wrapper != NULL) {
if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) {
Status = Callback (Wrapper, Buffer, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
}
Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY);
}
return AgesaStatus;
}
AGESA_STATUS
PcieConfigRunProcForAllDescriptors (
IN UINT32 InDescriptorFlags,
IN UINT32 OutDescriptorFlags,
IN UINT32 TerminationFlags,
IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_DESCRIPTOR_HEADER *Descriptor;
AgesaStatus = AGESA_SUCCESS;
Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header);
while (Descriptor != NULL) {
if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) {
Status = Callback (Descriptor, Buffer, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags);
}
return AgesaStatus;
}
VOID
STATIC
PcieSiliconEnablePortsV5 (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieConfigGetChildEngine (Silicon);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
if (!PcieConfigIsSbPcieEngine (EngineList) &&
(PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) &&
(EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard)))) {
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.PortData.DeviceNumber << 3 | EngineList->Type.Port.PortData.FunctionNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
AccessS3SaveWidth32,
(UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK),
((1 << D0F0xCC_x01_CsrEnable_OFFSET) | (1 << D0F0xCC_x01_SetPowEn_OFFSET)),
GnbLibGetHeader (Pcie)
);
}
}
EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
}
}
VOID
STATIC
PcieSiliconControlPortsV5 (
IN PCIE_PORT_VISIBILITY Control,
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT32 Value;
Value = (Control == HidePorts) ? ((1 << D0F0xCC_x01_BridgeDis_OFFSET) | (1 << D0F0xCC_x01_CfgDis_OFFSET)) : 0;
Value |= (1 << D0F0xCC_x01_CsrEnable_OFFSET) | (1 << D0F0xCC_x01_SetPowEn_OFFSET);
EngineList = PcieConfigGetChildEngine (Silicon);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.NativeDevNumber << 3 | EngineList->Type.Port.NativeFunNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
AccessS3SaveWidth32,
(UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK),
Value,
GnbLibGetHeader (Pcie)
);
}
EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
}
}
VOID
PcieConfigRunProcForAllEngines (
IN UINT32 DescriptorFlags,
IN PCIe_RUN_ON_ENGINE_CALLBACK Callback,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *Engine;
Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_ENGINES, &Pcie->Header);
while (Engine != NULL) {
if (!(PcieLibIsVirtualDesciptor (Engine) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
if (!((DescriptorFlags & DESCRIPTOR_ALLOCATED) != 0 && !PcieLibIsEngineAllocated (Engine))) {
if ((Engine->Header.DescriptorFlags & DESCRIPTOR_ALL_ENGINES & DescriptorFlags) != 0) {
Callback (Engine, Buffer, Pcie);
}
}
}
Engine = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (Engine, DESCRIPTOR_TERMINATE_TOPOLOGY);
}
}
/**
* Control port visibility in PCI config space
*
*
* @param[in] Control Control Hide/Unhide ports
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PciePortsVisibilityControlV5 (
IN PCIE_PORT_VISIBILITY Control,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *SiliconList;
SiliconList = (PCIe_SILICON_CONFIG *) PcieConfigGetChild (DESCRIPTOR_SILICON, &Pcie->Header);
while (SiliconList != NULL) {
switch (Control) {
case UnhidePorts:
PcieSiliconControlPortsV5 (UnhidePorts, SiliconList, Pcie);
break;
case HidePorts:
PcieSiliconControlPortsV5 (HidePorts, SiliconList, Pcie);
PcieSiliconEnablePortsV5 (SiliconList, Pcie);
break;
default:
ASSERT (FALSE);
}
SiliconList = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (SiliconList, DESCRIPTOR_TERMINATE_TOPOLOGY);
}
}
AGESA_STATUS
PcieConfigurationInit (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
PCIe_SILICON_CONFIG *Silicon;
UINT8 SocketId;
UINTN CurrentComplexesDataLength;
UINTN ComplexesDataLength;
UINT8 ComplexIndex;
VOID *Buffer;
ComplexesDataLength = 0;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n");
for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) {
if (IsProcessorPresent (SocketId, StdHeader)) {
Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader);
ASSERT (Status == AGESA_SUCCESS);
ComplexesDataLength += CurrentComplexesDataLength;
}
}
ComplexIndex = 0;
Pcie = GnbAllocateHeapBufferAndClear (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader);
ASSERT (Pcie != NULL);
if (Pcie != NULL) {
PcieConfigAttachChild (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header);
PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY);
Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG);
for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) {
if (IsProcessorPresent (SocketId, StdHeader)) {
Pcie->ComplexList[ComplexIndex].SocketId = SocketId;
//Attache Comples to Silicon which will be created by PcieFmBuildComplexConfiguration
PcieConfigAttachChild (&Pcie->ComplexList[ComplexIndex].Header, &((PCIe_SILICON_CONFIG *) Buffer)->Header);
//Attach Comples to Pcie
PcieConfigAttachParent (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header);
PcieConfigSetDescriptorFlags (&Pcie->ComplexList[ComplexIndex], DESCRIPTOR_COMPLEX | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY);
PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader);
Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[ComplexIndex]);
while (Silicon != NULL) {
PcieConfigAttachParent (&Pcie->ComplexList[ComplexIndex].Header, &Silicon->Header);
GetNodeId (SocketId, Silicon->SiliconId, &Silicon->NodeId, StdHeader);
GnbFmGetLinkId ((GNB_HANDLE*) Silicon, &Silicon->LinkId, StdHeader);
Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY);
}
if (ComplexIndex > 0) {
PcieConfigAttachComplexes (&Pcie->ComplexList[ComplexIndex - 1], &Pcie->ComplexList[ComplexIndex]);
}
PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader);
Buffer = (VOID *) ((UINT8 *) Buffer + CurrentComplexesDataLength);
ComplexIndex++;
}
}
} else {
Status = AGESA_FATAL;
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", Status);
return Status;
}
