AGESA_STATUS STATIC PcieEarlyInitTN ( IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Enter\n"); AgesaStatus = AGESA_SUCCESS; Status = PcieFP2CriteriaTN (Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallbackTN, NULL, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); PcieEarlyStaticInitTN (Pcie); Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLetPllPersonalityInitCallbackTN, NULL, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); PcieOscInitTN (Pcie); Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLaneInitInitCallbackTN, NULL, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackTN, NULL, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); PcieSetVoltageTN (PcieGen1, Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Exit [%x]\n", AgesaStatus); return AgesaStatus; }
/** * Various initialization needed prior topology and configuration initialization * * * * @param[in] Pcie Pointer to global PCIe configuration * */ VOID PcieFmPreInit ( IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT32 Index; PCIe_SILICON_CONFIG *Silicon; Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[0]); PcieConfigRunProcForAllWrappers ( DESCRIPTOR_ALL_WRAPPERS, PcieFmPhyLetPllPersonalityInitCallback, NULL, Pcie ); PcieFmOscInitPhyForGen2 (Pcie); PcieConfigRunProcForAllWrappers ( DESCRIPTOR_PCIE_WRAPPER, PcieFmPhyLaneInitInitCallback, NULL, Pcie ); for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) { PcieSiliconRegisterRMW ( Silicon, PcieInitTable[Index].Reg, PcieInitTable[Index].Mask, PcieInitTable[Index].Data, FALSE, Pcie ); } // Set PCIe SSID. PcieSiliconRegisterRMW ( Silicon, WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS), D0F0xE4_WRAP_8002_PcieWrapScratch_MASK, UserOptions.CfgGnbPcieSSID << D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET, FALSE, Pcie ); PcieSiliconRegisterRMW ( Silicon, WRAP_SPACE (1, D0F0xE4_WRAP_8002_ADDRESS), D0F0xE4_WRAP_8002_PcieWrapScratch_MASK, UserOptions.CfgGnbPcieSSID << D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET, FALSE, Pcie ); }
AGESA_STATUS PcieFP2CriteriaTN ( IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS Status; D18F3x1FC_STRUCT D18F3x1FC; IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Enter\n"); // PACKAGE_TYPE_FP2 1 // PACKAGE_TYPE_FS1r2 2 // PACKAGE_TYPE_FM2 4 if (LibAmdGetPackageType (GnbLibGetHeader (Pcie)) != PACKAGE_TYPE_FP2) { return AGESA_SUCCESS; } GnbRegisterReadTN (D18F3x1FC_TYPE, D18F3x1FC_ADDRESS, &D18F3x1FC.Value, 0, GnbLibGetHeader (Pcie)); // FP2 processor link supports Gen2 mode if (D18F3x1FC.Field.Fp2PcieGen2Sup == 1) { return AGESA_SUCCESS; } // FP2 force gen1 Pcie->PsppPolicy = PsppPowerSaving; // FP2 only use x8 on the same PHY Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieFP2x8CheckCallbackTN, NULL, Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "PcieFP2CriteriaTN Exit\n"); return Status; }
AGESA_STATUS PcieInit ( IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Enter\n"); AgesaStatus = AGESA_SUCCESS; Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallback, NULL, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); PcieFmPreInit (Pcie); Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitCallback, NULL, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Exit [%x]\n", AgesaStatus); return AgesaStatus; }
AGESA_STATUS STATIC PcieEarlyInitCZ ( IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCZ Enter\n"); AgesaStatus = AGESA_SUCCESS; Status = PcieConfigRunProcForAllDescriptors (DESCRIPTOR_SILICON, 0, DESCRIPTOR_TERMINATE_TOPOLOGY, PciePortMapInitCallbackCZ, NULL, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLaneInitInitCallbackCZ, NULL, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackCZ, NULL, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCZ Exit [%x]\n", AgesaStatus); return AgesaStatus; }
AGESA_STATUS PciePostInit ( IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Enter\n"); AgesaStatus = AGESA_SUCCESS; Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_PCIE_WRAPPER, PciePostInitCallback, NULL, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); PcieFmSetBootUpVoltage ( PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie), Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus); return AgesaStatus; }
AGESA_STATUS STATIC PcieMidCharacterizationKV ( IN OUT PCIe_INFO_BUFFER *PcieInfoBuffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS AgesaStatus; AGESA_STATUS Status; UINT8 Index; IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidCharacterizationKV Enter\n"); AgesaStatus = AGESA_SUCCESS; // Set initial stats for all PcieInfoBuffer fields for (Index = 0; Index < NUMBER_OF_SUBLINKS; Index++) { ((PCIe_INFO_BUFFER *) PcieInfoBuffer)->SublinkInfo[Index].GppPortCount = 0; ((PCIe_INFO_BUFFER *) PcieInfoBuffer)->SublinkInfo[Index].MaxGenCapability = Gen1; } for (Index = 0; Index < NUMBER_OF_WRAPPERS; Index++) { ((PCIe_INFO_BUFFER *) PcieInfoBuffer)->WrapperInfo[Index].MinAspmL1ExitLatency = 255; ((PCIe_INFO_BUFFER *) PcieInfoBuffer)->WrapperInfo[Index].AnyDevFailPllpdnb = FALSE; ((PCIe_INFO_BUFFER *) PcieInfoBuffer)->WrapperInfo[Index].DisableL1OnWrapper = FALSE; } PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, PcieMidPortCharacterizationCallbackKV, (VOID *) PcieInfoBuffer, Pcie ); Status = PcieConfigRunProcForAllWrappers ( DESCRIPTOR_ALL_WRAPPERS, PcieMidWrapperCharacterizationCallbackKV, (VOID *) PcieInfoBuffer, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidCharacterizationKV Exit [0x%x]\n", AgesaStatus); return AgesaStatus; }
AGESA_STATUS STATIC PcieMidInitKV ( IN OUT PCIe_INFO_BUFFER *PcieInfoBuffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS AgesaStatus; AGESA_STATUS Status; IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitKV Enter\n"); AgesaStatus = AGESA_SUCCESS; Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackKV, (VOID *) PcieInfoBuffer, Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); Status = PciePowerGateKV (Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitKV Exit [0x%x]\n", AgesaStatus); return AgesaStatus; }