VOID
STATIC
PciePortInitCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
PciePortProgramRegisterTable (PortInitTable, (sizeof (PortInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, FALSE, Pcie);
PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie);
PcieSetLinkWidthCap (Engine, Pcie);
PcieCompletionTimeout (Engine, Pcie);
PcieLinkSetSlotCap (Engine, Pcie);
PcieLinkInitHotplug (Engine, Pcie);
PcieFmPhyChannelCharacteristic (Engine, Pcie);
if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
PcieLinkSafeMode (Engine, Pcie);
}
if (Engine->Type.Port.PortData.PortPresent == PortDisabled) {
ASSERT (Engine->Type.Port.IsSB == FALSE);
PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
// Train port that forced to compliance in last stage of training
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
}
}
VOID
STATIC
PcieEarlyPortInitCallbackTN (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Enter\n");
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
PciePortProgramRegisterTable (PortInitEarlyTableTN.Table, PortInitEarlyTableTN.Length, Engine, FALSE, Pcie);
PcieSetLinkSpeedCapV4 (PcieGen1, Engine, Pcie);
PcieSetLinkWidthCap (Engine, Pcie);
PcieCompletionTimeout (Engine, Pcie);
PcieLinkSetSlotCap (Engine, Pcie);
PcieLinkInitHotplug (Engine, Pcie);
if (Engine->Type.Port.PortData.PortPresent == PortDisabled ||
(Engine->Type.Port.PortData.EndpointStatus == EndpointNotPresent &&
Engine->Type.Port.PortData.LinkHotplug != HotplugEnhanced &&
Engine->Type.Port.PortData.LinkHotplug != HotplugServer)) {
ASSERT (!PcieConfigIsSbPcieEngine (Engine));
//
// Pass endpoint status in scratch
//
PciePortRegisterRMW (
Engine,
DxF0xE4_x01_ADDRESS,
0x1,
0x1,
FALSE,
Pcie
);
PcieTrainingSetPortStateV1 (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieTrainingSetPortStateV1 (Engine, LinkStateTrainingCompleted, FALSE, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyPortInitCallbackTN Exit\n");
}
VOID
PcieLinkInitHotplugV5 (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 Value;
PcieLinkInitHotplug (Engine, Pcie);
if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) {
Value = 1;
} else {
Value = 0;
}
PciePortRegisterWriteField (
Engine,
DxF0xE4_x10_ADDRESS,
DxF0xE4_x10_NativePmeEn_OFFSET,
DxF0xE4_x10_NativePmeEn_WIDTH,
Value,
TRUE,
Pcie
);
}
