static int
ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
int length, struct devrequest *req)
{
ALLOC_ALIGN_BUFFER(struct QH, qh, 1, USB_DMA_MINALIGN);
struct qTD *qtd;
int qtd_count = 0;
int qtd_counter = 0;
volatile struct qTD *vtd;
unsigned long ts;
uint32_t *tdp;
uint32_t endpt, maxpacket, token, usbsts;
uint32_t c, toggle;
uint32_t cmd;
int timeout;
int ret = 0;
struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
buffer, length, req);
if (req != NULL)
debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
req->request, req->request,
req->requesttype, req->requesttype,
le16_to_cpu(req->value), le16_to_cpu(req->value),
le16_to_cpu(req->index));
#define PKT_ALIGN 512
/*
* The USB transfer is split into qTD transfers. Eeach qTD transfer is
* described by a transfer descriptor (the qTD). The qTDs form a linked
* list with a queue head (QH).
*
* Each qTD transfer starts with a new USB packet, i.e. a packet cannot
* have its beginning in a qTD transfer and its end in the following
* one, so the qTD transfer lengths have to be chosen accordingly.
*
* Each qTD transfer uses up to QT_BUFFER_CNT data buffers, mapped to
* single pages. The first data buffer can start at any offset within a
* page (not considering the cache-line alignment issues), while the
* following buffers must be page-aligned. There is no alignment
* constraint on the size of a qTD transfer.
*/
if (req != NULL)
/* 1 qTD will be needed for SETUP, and 1 for ACK. */
qtd_count += 1 + 1;
if (length > 0 || req == NULL) {
/*
* Determine the qTD transfer size that will be used for the
* data payload (not considering the first qTD transfer, which
* may be longer or shorter, and the final one, which may be
* shorter).
*
* In order to keep each packet within a qTD transfer, the qTD
* transfer size is aligned to PKT_ALIGN, which is a multiple of
* wMaxPacketSize (except in some cases for interrupt transfers,
* see comment in submit_int_msg()).
*
* By default, i.e. if the input buffer is aligned to PKT_ALIGN,
* QT_BUFFER_CNT full pages will be used.
*/
int xfr_sz = QT_BUFFER_CNT;
/*
* However, if the input buffer is not aligned to PKT_ALIGN, the
* qTD transfer size will be one page shorter, and the first qTD
* data buffer of each transfer will be page-unaligned.
*/
if ((unsigned long)buffer & (PKT_ALIGN - 1))
xfr_sz--;
/* Convert the qTD transfer size to bytes. */
xfr_sz *= EHCI_PAGE_SIZE;
/*
* Approximate by excess the number of qTDs that will be
* required for the data payload. The exact formula is way more
* complicated and saves at most 2 qTDs, i.e. a total of 128
* bytes.
*/
qtd_count += 2 + length / xfr_sz;
}
/*
* Threshold value based on the worst-case total size of the allocated qTDs for
* a mass-storage transfer of 65535 blocks of 512 bytes.
*/
#if CONFIG_SYS_MALLOC_LEN <= 64 + 128 * 1024
#warning CONFIG_SYS_MALLOC_LEN may be too small for EHCI
#endif
qtd = memalign(USB_DMA_MINALIGN, qtd_count * sizeof(struct qTD));
if (qtd == NULL) {
printf("unable to allocate TDs\n");
return -1;
}
memset(qh, 0, sizeof(struct QH));
memset(qtd, 0, qtd_count * sizeof(*qtd));
toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
/*
* Setup QH (3.6 in ehci-r10.pdf)
*
* qh_link ................. 03-00 H
* qh_endpt1 ............... 07-04 H
* qh_endpt2 ............... 0B-08 H
* - qh_curtd
* qh_overlay.qt_next ...... 13-10 H
* - qh_overlay.qt_altnext
*/
qh->qh_link = cpu_to_hc32((unsigned long)&ctrl->qh_list | QH_LINK_TYPE_QH);
c = (dev->speed != USB_SPEED_HIGH) && !usb_pipeendpoint(pipe);
maxpacket = usb_maxpacket(dev, pipe);
endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
QH_ENDPT1_MAXPKTLEN(maxpacket) | QH_ENDPT1_H(0) |
QH_ENDPT1_DTC(QH_ENDPT1_DTC_DT_FROM_QTD) |
QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
QH_ENDPT1_ENDPT(usb_pipeendpoint(pipe)) | QH_ENDPT1_I(0) |
QH_ENDPT1_DEVADDR(usb_pipedevice(pipe));
qh->qh_endpt1 = cpu_to_hc32(endpt);
endpt = QH_ENDPT2_MULT(1) | QH_ENDPT2_UFCMASK(0) | QH_ENDPT2_UFSMASK(0);
qh->qh_endpt2 = cpu_to_hc32(endpt);
ehci_update_endpt2_dev_n_port(dev, qh);
qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
tdp = &qh->qh_overlay.qt_next;
if (req != NULL) {
/*
* Setup request qTD (3.5 in ehci-r10.pdf)
*
* qt_next ................ 03-00 H
* qt_altnext ............. 07-04 H
* qt_token ............... 0B-08 H
*
* [ buffer, buffer_hi ] loaded with "req".
*/
qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
token = QT_TOKEN_DT(0) | QT_TOKEN_TOTALBYTES(sizeof(*req)) |
QT_TOKEN_IOC(0) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
QT_TOKEN_PID(QT_TOKEN_PID_SETUP) |
QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
qtd[qtd_counter].qt_token = cpu_to_hc32(token);
if (ehci_td_buffer(&qtd[qtd_counter], req, sizeof(*req))) {
printf("unable to construct SETUP TD\n");
goto fail;
}
/* Update previous qTD! */
*tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
tdp = &qtd[qtd_counter++].qt_next;
toggle = 1;
}
if (length > 0 || req == NULL) {
uint8_t *buf_ptr = buffer;
int left_length = length;
do {
/*
* Determine the size of this qTD transfer. By default,
* QT_BUFFER_CNT full pages can be used.
*/
int xfr_bytes = QT_BUFFER_CNT * EHCI_PAGE_SIZE;
/*
* However, if the input buffer is not page-aligned, the
* portion of the first page before the buffer start
* offset within that page is unusable.
*/
xfr_bytes -= (unsigned long)buf_ptr & (EHCI_PAGE_SIZE - 1);
/*
* In order to keep each packet within a qTD transfer,
* align the qTD transfer size to PKT_ALIGN.
*/
xfr_bytes &= ~(PKT_ALIGN - 1);
/*
* This transfer may be shorter than the available qTD
* transfer size that has just been computed.
*/
xfr_bytes = min(xfr_bytes, left_length);
/*
* Setup request qTD (3.5 in ehci-r10.pdf)
*
* qt_next ................ 03-00 H
* qt_altnext ............. 07-04 H
* qt_token ............... 0B-08 H
*
* [ buffer, buffer_hi ] loaded with "buffer".
*/
qtd[qtd_counter].qt_next =
cpu_to_hc32(QT_NEXT_TERMINATE);
qtd[qtd_counter].qt_altnext =
cpu_to_hc32(QT_NEXT_TERMINATE);
token = QT_TOKEN_DT(toggle) |
QT_TOKEN_TOTALBYTES(xfr_bytes) |
QT_TOKEN_IOC(req == NULL) | QT_TOKEN_CPAGE(0) |
QT_TOKEN_CERR(3) |
QT_TOKEN_PID(usb_pipein(pipe) ?
QT_TOKEN_PID_IN : QT_TOKEN_PID_OUT) |
QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
qtd[qtd_counter].qt_token = cpu_to_hc32(token);
if (ehci_td_buffer(&qtd[qtd_counter], buf_ptr,
xfr_bytes)) {
printf("unable to construct DATA TD\n");
goto fail;
}
/* Update previous qTD! */
*tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
tdp = &qtd[qtd_counter++].qt_next;
/*
* Data toggle has to be adjusted since the qTD transfer
* size is not always an even multiple of
* wMaxPacketSize.
*/
if ((xfr_bytes / maxpacket) & 1)
toggle ^= 1;
buf_ptr += xfr_bytes;
left_length -= xfr_bytes;
} while (left_length > 0);
}
if (req != NULL) {
/*
* Setup request qTD (3.5 in ehci-r10.pdf)
*
* qt_next ................ 03-00 H
* qt_altnext ............. 07-04 H
* qt_token ............... 0B-08 H
*/
qtd[qtd_counter].qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
qtd[qtd_counter].qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
token = QT_TOKEN_DT(1) | QT_TOKEN_TOTALBYTES(0) |
QT_TOKEN_IOC(1) | QT_TOKEN_CPAGE(0) | QT_TOKEN_CERR(3) |
QT_TOKEN_PID(usb_pipein(pipe) ?
QT_TOKEN_PID_OUT : QT_TOKEN_PID_IN) |
QT_TOKEN_STATUS(QT_TOKEN_STATUS_ACTIVE);
qtd[qtd_counter].qt_token = cpu_to_hc32(token);
/* Update previous qTD! */
*tdp = cpu_to_hc32((unsigned long)&qtd[qtd_counter]);
tdp = &qtd[qtd_counter++].qt_next;
}
ctrl->qh_list.qh_link = cpu_to_hc32((unsigned long)qh | QH_LINK_TYPE_QH);
/* Flush dcache */
flush_dcache_range((unsigned long)&ctrl->qh_list,
ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
flush_dcache_range((unsigned long)qh, ALIGN_END_ADDR(struct QH, qh, 1));
flush_dcache_range((unsigned long)qtd,
ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
/* Set async. queue head pointer. */
ehci_writel(&ctrl->hcor->or_asynclistaddr, (unsigned long)&ctrl->qh_list);
usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
/* Enable async. schedule. */
cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
cmd |= CMD_ASE;
ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
100 * 1000);
if (ret < 0) {
printf("EHCI fail timeout STS_ASS set\n");
goto fail;
}
/* Wait for TDs to be processed. */
ts = get_timer(0);
vtd = &qtd[qtd_counter - 1];
timeout = USB_TIMEOUT_MS(pipe);
do {
/* Invalidate dcache */
invalidate_dcache_range((unsigned long)&ctrl->qh_list,
ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
invalidate_dcache_range((unsigned long)qh,
ALIGN_END_ADDR(struct QH, qh, 1));
invalidate_dcache_range((unsigned long)qtd,
ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
token = hc32_to_cpu(vtd->qt_token);
if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
break;
WATCHDOG_RESET();
} while (get_timer(ts) < timeout);
/*
* Invalidate the memory area occupied by buffer
* Don't try to fix the buffer alignment, if it isn't properly
* aligned it's upper layer's fault so let invalidate_dcache_range()
* vow about it. But we have to fix the length as it's actual
* transfer length and can be unaligned. This is potentially
* dangerous operation, it's responsibility of the calling
* code to make sure enough space is reserved.
*/
invalidate_dcache_range((unsigned long)buffer,
ALIGN((unsigned long)buffer + length, ARCH_DMA_MINALIGN));
/* Check that the TD processing happened */
if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)
printf("EHCI timed out on TD - token=%#x\n", token);
/* Disable async schedule. */
cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
cmd &= ~CMD_ASE;
ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
100 * 1000);
if (ret < 0) {
printf("EHCI fail timeout STS_ASS reset\n");
goto fail;
}
token = hc32_to_cpu(qh->qh_overlay.qt_token);
if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE)) {
debug("TOKEN=%#x\n", token);
switch (QT_TOKEN_GET_STATUS(token) &
~(QT_TOKEN_STATUS_SPLITXSTATE | QT_TOKEN_STATUS_PERR)) {
case 0:
toggle = QT_TOKEN_GET_DT(token);
usb_settoggle(dev, usb_pipeendpoint(pipe),
usb_pipeout(pipe), toggle);
dev->status = 0;
break;
case QT_TOKEN_STATUS_HALTED:
dev->status = USB_ST_STALLED;
break;
case QT_TOKEN_STATUS_ACTIVE | QT_TOKEN_STATUS_DATBUFERR:
case QT_TOKEN_STATUS_DATBUFERR:
dev->status = USB_ST_BUF_ERR;
break;
case QT_TOKEN_STATUS_HALTED | QT_TOKEN_STATUS_BABBLEDET:
case QT_TOKEN_STATUS_BABBLEDET:
dev->status = USB_ST_BABBLE_DET;
break;
default:
dev->status = USB_ST_CRC_ERR;
if (QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_HALTED)
dev->status |= USB_ST_STALLED;
break;
}
dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(token);
} else {
dev->act_len = 0;
#ifndef CONFIG_USB_EHCI_FARADAY
debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
ehci_readl(&ctrl->hcor->or_portsc[0]),
ehci_readl(&ctrl->hcor->or_portsc[1]));
#endif
}
free(qtd);
return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
fail:
free(qtd);
return -1;
}
//Create and return an interrupt queue object.
struct int_queue* EHCICreateIntQueue(struct usb_device *dev,
unsigned long pipe, int queuesize, int elementsize,
void *buffer, int interval)
{
struct ehci_ctrl *ctrl = ehci_get_ctrl(dev);
struct int_queue *result = NULL;
uint32_t i, toggle;
struct QH *list = NULL;
int cmd = 0;
DWORD dwFlags;
/*
* Interrupt transfers requiring several transactions are not supported
* because bInterval is ignored.
*
* Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
* <= PKT_ALIGN if several qTDs are required, while the USB
* specification does not constrain this for interrupt transfers. That
* means that ehci_submit_async() would support interrupt transfers
* requiring several transactions only as long as the transfer size does
* not require more than a single qTD.
*/
if (elementsize > usb_maxpacket(dev, pipe)) {
printf("%s: xfers requiring several transactions are not supported.\r\n",
"_ehci_create_int_queue");
return NULL;
}
if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
return NULL;
}
/* limit to 4 full pages worth of data -
* we can safely fit them in a single TD,
* no matter the alignment
*/
if (elementsize >= 16384) {
debug("too large elements for interrupt transfers\r\n");
return NULL;
}
result = malloc(sizeof(*result));
if (!result) {
debug("ehci intr queue: out of memory\r\n");
goto fail1;
}
//Create EVENT object to synchronizing the access.
result->hEvent = CreateEvent(FALSE);
if (NULL == result->hEvent)
{
goto fail1;
}
result->dwTimeOut = 0;
result->pNext = NULL;
result->pOwnerThread = KernelThreadManager.lpCurrentKernelThread;
result->QueueIntHandler = _ehciQueueIntHandler;
result->pUsbDev = dev;
result->dwStatus = INT_QUEUE_STATUS_INITIALIZED;
result->elementsize = elementsize;
result->pipe = pipe;
result->first = memalign(USB_DMA_MINALIGN,
sizeof(struct QH) * queuesize);
if (!result->first) {
debug("ehci intr queue: out of memory\r\n");
goto fail2;
}
debug("%s: Allocate %d QH(s) at %X.\r\n", __func__,queuesize,result->first);
result->current = result->first;
result->last = result->first + queuesize - 1;
result->tds = memalign(USB_DMA_MINALIGN,
sizeof(struct qTD) * queuesize);
if (!result->tds) {
debug("ehci intr queue: out of memory\r\n");
goto fail3;
}
debug("%s: Allocate %d qTD(s) at %X.\r\n", __func__,queuesize, result->tds);
memset(result->first, 0, sizeof(struct QH) * queuesize);
memset(result->tds, 0, sizeof(struct qTD) * queuesize);
toggle = usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
for (i = 0; i < (uint32_t)queuesize; i++) {
struct QH *qh = result->first + i;
struct qTD *td = result->tds + i;
void **buf = &qh->buffer;
qh->qh_link = cpu_to_hc32((unsigned long)(qh + 1) | QH_LINK_TYPE_QH);
if (i == queuesize - 1)
qh->qh_link = cpu_to_hc32(QH_LINK_TERMINATE);
qh->qh_overlay.qt_next = cpu_to_hc32((unsigned long)td);
qh->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
qh->qh_endpt1 =
cpu_to_hc32((0 << 28) | /* No NAK reload (ehci 4.9) */
(usb_maxpacket(dev, pipe) << 16) | /* MPS */
(1 << 14) |
QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) |
(usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */
(usb_pipedevice(pipe) << 0));
qh->qh_endpt2 = cpu_to_hc32((1 << 30) | /* 1 Tx per mframe */
(1 << 0)); /* S-mask: microframe 0 */
if (dev->speed == USB_SPEED_LOW ||
dev->speed == USB_SPEED_FULL) {
/* C-mask: microframes 2-4 */
qh->qh_endpt2 |= cpu_to_hc32((0x1c << 8));
}
ehci_update_endpt2_dev_n_port(dev, qh);
td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
debug("%s: communication direction is '%s'\r\n",
__func__,
usb_pipein(pipe) ? "in" : "out");
if (i == queuesize - 1) //Last one,set IoC bit.
{
td->qt_token = cpu_to_hc32(
QT_TOKEN_DT(toggle) |
(elementsize << 16) |
(1 << 15) | //Interrupt On Completion.
(3 << 10) | //CERR bits.
((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
0x80); /* active */
}
else
{
td->qt_token = cpu_to_hc32(
QT_TOKEN_DT(toggle) |
(elementsize << 16) |
(3 << 10) | //CERR bits.
((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */
0x80); /* active */
}
debug("%s: construct TD token = %X.\r\n", __func__, td->qt_token);
td->qt_buffer[0] =
cpu_to_hc32((unsigned long)buffer + i * elementsize);
td->qt_buffer[1] =
cpu_to_hc32((td->qt_buffer[0] + 0x1000) & ~0xfff);
td->qt_buffer[2] =
cpu_to_hc32((td->qt_buffer[0] + 0x2000) & ~0xfff);
td->qt_buffer[3] =
cpu_to_hc32((td->qt_buffer[0] + 0x3000) & ~0xfff);
td->qt_buffer[4] =
cpu_to_hc32((td->qt_buffer[0] + 0x4000) & ~0xfff);
#ifdef __MS_VC__
//MS VC can not support sizeof(void) operation,we should
//convert the buffer type to char*.
*buf = (void*)((char*)buffer + i * elementsize);
#else
//sizeof(void) is 1 under GCC or other environment,so the
//following sentence is same as above one.
*buf = buffer + i * elementsize;
#endif
toggle ^= 1;
}
flush_dcache_range((unsigned long)buffer,
ALIGN_END_ADDR(char, buffer,
queuesize * elementsize));
flush_dcache_range((unsigned long)result->first,
ALIGN_END_ADDR(struct QH, result->first,
queuesize));
flush_dcache_range((unsigned long)result->tds,
ALIGN_END_ADDR(struct qTD, result->tds,
queuesize));
//Acquire exclusively accessing of the controller.
WaitForThisObject(ctrl->hMutex);
if (ctrl->periodic_schedules > 0) {
if (ehci_disable_periodic(ctrl) < 0) {
ReleaseMutex(ctrl->hMutex);
_hx_printf("FATAL %s: periodic should never fail, but did.\r\n",__func__);
goto fail3;
}
}
__ENTER_CRITICAL_SECTION(NULL, dwFlags);
/* hook up to periodic list */
list = &ctrl->periodic_queue;
result->last->qh_link = list->qh_link;
list->qh_link = cpu_to_hc32((unsigned long)result->first | QH_LINK_TYPE_QH);
//Link interrupt queue to Controller's pending queue.
if (NULL == ctrl->pIntQueueFirst)
{
ctrl->pIntQueueFirst = result;
ctrl->pIntQueueLast = result;
}
else
{
result->pNext = ctrl->pIntQueueFirst;
ctrl->pIntQueueFirst = result;
}
__LEAVE_CRITICAL_SECTION(NULL, dwFlags);
flush_dcache_range((unsigned long)result->last,
ALIGN_END_ADDR(struct QH, result->last, 1));
flush_dcache_range((unsigned long)list,
ALIGN_END_ADDR(struct QH, list, 1));
if (ehci_enable_periodic(ctrl) < 0) {
ReleaseMutex(ctrl->hMutex);
_hx_printf("FATAL %s: periodic should never fail, but did.\r\n", __func__);;
goto fail3;
}
ctrl->periodic_schedules++;
ReleaseMutex(ctrl->hMutex);
debug("Exit create_int_queue\r\n");
return result;
fail3:
if (result->tds)
free(result->tds);
fail2:
if (result->first)
free(result->first);
//if (result)
// free(result);
fail1:
if (result)
{
if (NULL != result->hEvent)
{
DestroyEvent(result->hEvent);
}
free(result);
}
return NULL;
}
