int hdmi_dst_display_path_config(bool enable)
{
HDMI_FUNC();
if (enable)
{
//FIXME: now nothing can be seen on TV if output UYVY from WDMA0
unsigned int hdmiSourceAddr = hdmi_mva_r;// + p->hdmi_width * p->hdmi_height * hdmi_bpp * hdmi_buffer_read_id;
struct disp_path_config_struct config = {0};
// Config RDMA->DPI1
config.srcWidth = 1280;
config.srcHeight = 720;
config.srcModule = DISP_MODULE_RDMA1;
config.inFormat = RDMA_INPUT_FORMAT_ARGB;
config.outFormat = RDMA_OUTPUT_FORMAT_ARGB;
config.addr = hdmiSourceAddr;
config.pitch = config.srcWidth * 4;
config.dstModule = DISP_MODULE_DPI0;
//if(-1 == dp_mutex_dst)
// dp_mutex_dst = disp_lock_mutex();
dp_mutex_dst = 2;
disp_dump_reg(DISP_MODULE_RDMA0);
disp_dump_reg(DISP_MODULE_RDMA1);
disp_dump_reg(DISP_MODULE_CONFIG);
HDMI_LOG("Get mutex ID %d for RDMA1>DPI1\n", dp_mutex_dst);
disp_path_get_mutex_(dp_mutex_dst);
disp_path_config_(&config, dp_mutex_dst);
disp_path_release_mutex_(dp_mutex_dst);
disp_dump_reg(DISP_MODULE_CONFIG);
disp_dump_reg(DISP_MODULE_RDMA0);
disp_dump_reg(DISP_MODULE_RDMA1);
}
else
{
if (-1 != dp_mutex_dst)
{
//FIXME: release mutex timeout
HDMI_LOG("Stop RDMA1>DPI1\n");
disp_path_get_mutex_(dp_mutex_dst);
DISP_REG_SET_FIELD(1 << dp_mutex_src , DISP_REG_CONFIG_MUTEX_INTEN, 1);
RDMAStop(1);
RDMAReset(1);
disp_path_release_mutex_(dp_mutex_dst);
//disp_unlock_mutex(dp_mutex_dst);
dp_mutex_dst = -1;
}
}
return 0;
}
int disp_path_config(struct disp_path_config_struct* pConfig)
{
///> get mutex and set mout/sel
// unsigned int gMutexID = 0;
unsigned int mutex_mode;
printf("[DDP]disp_path_config(), srcModule=%d, addr=0x%x, inFormat=%d, \n\
pitch=%d, bgROI(%d,%d,%d,%d), bgColor=%d, outFormat=%d, dstModule=%d, dstAddr=0x%x, \n",
pConfig->srcModule,
pConfig->addr,
pConfig->inFormat,
pConfig->pitch,
pConfig->bgROI.x,
pConfig->bgROI.y,
pConfig->bgROI.width,
pConfig->bgROI.height,
pConfig->bgColor,
pConfig->outFormat,
pConfig->dstModule,
pConfig->dstAddr);
if(pConfig->srcModule==DISP_MODULE_RDMA0 && pConfig->dstModule==DISP_MODULE_WDMA1)
{
printf("[DDP] error! rdma0 wdma1 can not enable together! \n");
return -1;
}
switch(pConfig->dstModule)
{
case DISP_MODULE_DSI_VDO:
mutex_mode = 1;
break;
case DISP_MODULE_DPI0:
mutex_mode = 2;
break;
case DISP_MODULE_DBI:
case DISP_MODULE_DSI_CMD:
case DISP_MODULE_WDMA1:
mutex_mode = 0;
break;
default:
printf("[DDP] error! unknown dstModule=%d \n", pConfig->dstModule);
}
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_RST(gMutexID), 1);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_RST(gMutexID), 0);
if(pConfig->srcModule==DISP_MODULE_RDMA0)
{
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_MOD(gMutexID), 0x80); //rdma0=7
}
else
{
if(pConfig->dstModule==DISP_MODULE_WDMA1)
{
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_MOD(gMutexID), 0x44); //ovl=2, wdma1=6
}
else
{
#if defined(MTK_AAL_SUPPORT)
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_MOD(gMutexID), 0x284); //ovl=2, bls=9, rdma0=7
#else
// Elsa: de-couple BLS from OVL stream
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_MOD(gMutexID), 0x84); //ovl=2, rdma0=7
#endif
}
}
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_SOF(gMutexID), mutex_mode);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_INTSTA, (1 << gMutexID));
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_INTEN, (1 << gMutexID));
// disp_path_get_mutex();
///> config config reg
switch(pConfig->dstModule)
{
case DISP_MODULE_DSI:
case DISP_MODULE_DSI_VDO:
case DISP_MODULE_DSI_CMD:
DISP_REG_SET(DISP_REG_CONFIG_OVL_MOUT_EN, 0x2); // ovl_mout output to bls
DISP_REG_SET(DISP_REG_CONFIG_BLS_SEL, 0); // bls_sel from overlay
DISP_REG_SET(DISP_REG_CONFIG_RDMA0_OUT_SEL, 0); // rdma0_mout to dsi0
break;
case DISP_MODULE_DPI0:
printf("DISI_MODULE_DPI0\n");
DISP_REG_SET(DISP_REG_CONFIG_OVL_MOUT_EN, 0x2); // ovl_mout output to bls
DISP_REG_SET(DISP_REG_CONFIG_BLS_SEL, 0); // bls_sel from overlay
DISP_REG_SET(DISP_REG_CONFIG_RDMA0_OUT_SEL, 0x2); // rdma0_mout to dpi0
DISP_REG_SET(DISP_REG_CONFIG_DPI0_SEL, 0); // dpi0_sel from rdma0
break;
case DISP_MODULE_DBI:
DISP_REG_SET(DISP_REG_CONFIG_OVL_MOUT_EN, 0x2); // ovl_mout output to bls
DISP_REG_SET(DISP_REG_CONFIG_BLS_SEL, 0); // bls_sel from overlay
DISP_REG_SET(DISP_REG_CONFIG_RDMA0_OUT_SEL, 0x1); // rdma0_mout to dbi
DISP_REG_SET(DISP_REG_CONFIG_DBI_SEL, 0); // dbi_sel from rdma0
break;
case DISP_MODULE_WDMA1:
DISP_REG_SET(DISP_REG_CONFIG_OVL_MOUT_EN, 0x1); // ovl_mout output to wdma1
break;
default:
printf("[DDP] error! unknown dstModule=%d \n", pConfig->dstModule);
}
///> config engines
if(pConfig->srcModule!=DISP_MODULE_RDMA0)
{ // config OVL
OVLStop();
// OVLReset();
OVLROI(pConfig->bgROI.width, // width
pConfig->bgROI.height, // height
pConfig->bgColor);// background B
OVLLayerSwitch(pConfig->ovl_config.layer, pConfig->ovl_config.layer_en);
if(pConfig->ovl_config.layer_en!=0)
{
OVLLayerConfig(pConfig->ovl_config.layer, // layer
pConfig->ovl_config.source, // data source (0=memory)
pConfig->ovl_config.fmt,
pConfig->ovl_config.addr, // addr
pConfig->ovl_config.x, // x
pConfig->ovl_config.y, // y
pConfig->ovl_config.w, // width
pConfig->ovl_config.h, // height
pConfig->ovl_config.pitch,
pConfig->ovl_config.keyEn, //color key
pConfig->ovl_config.key, //color key
pConfig->ovl_config.aen, // alpha enable
pConfig->ovl_config.alpha); // alpha
}
OVLStart();
if(pConfig->dstModule==DISP_MODULE_WDMA1) //1. mem->ovl->wdma1->mem
{
WDMAReset(1);
WDMAConfig(1,
WDMA_INPUT_FORMAT_ARGB,
pConfig->srcROI.width,
pConfig->srcROI.height,
0,
0,
pConfig->srcROI.width,
pConfig->srcROI.height,
pConfig->outFormat,
pConfig->dstAddr,
pConfig->srcROI.width,
1,
0);
WDMAStart(1);
}
else //2. ovl->bls->rdma0->lcd
{
#if defined(MTK_AAL_SUPPORT)
disp_bls_init(pConfig->srcROI.width, pConfig->srcROI.height);
#endif
///config RDMA
RDMAStop(0);
RDMAReset(0);
RDMAConfig(0,
RDMA_MODE_DIRECT_LINK, ///direct link mode
RDMA_INPUT_FORMAT_RGB888, // inputFormat
NULL, // address
pConfig->outFormat, // output format
pConfig->pitch, // pitch
pConfig->srcROI.width, // width
pConfig->srcROI.height, // height
0, //byte swap
0); // is RGB swap
RDMAStart(0);
}
}
else //3. mem->rdma->lcd
{
///config RDMA
RDMAStop(0);
RDMAReset(0);
RDMAConfig(0,
RDMA_MODE_MEMORY, ///direct link mode
pConfig->inFormat, // inputFormat
pConfig->addr, // address
pConfig->outFormat, // output format
pConfig->pitch, //
pConfig->srcROI.width,
pConfig->srcROI.height,
0, //byte swap
0); // is RGB swap
RDMAStart(0);
}
disp_dump_reg(DISP_MODULE_OVL);
disp_dump_reg(DISP_MODULE_WDMA1);
disp_dump_reg(DISP_MODULE_DPI0);
disp_dump_reg(DISP_MODULE_RDMA0);
disp_dump_reg(DISP_MODULE_CONFIG);
// disp_path_release_mutex();
return 0;
}
