static int
qla24xx_soft_reset(scsi_qla_host_t *ha)
{
int rval = QLA_SUCCESS;
uint32_t cnt;
uint16_t mb0, wd;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
/* Reset RISC. */
WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
for (cnt = 0; cnt < 30000; cnt++) {
if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
break;
udelay(10);
}
WRT_REG_DWORD(®->ctrl_status,
CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
udelay(100);
/* Wait for firmware to complete NVRAM accesses. */
mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
for (cnt = 10000 ; cnt && mb0; cnt--) {
udelay(5);
mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
barrier();
}
/* Wait for soft-reset to complete. */
for (cnt = 0; cnt < 30000; cnt++) {
if ((RD_REG_DWORD(®->ctrl_status) &
CSRX_ISP_SOFT_RESET) == 0)
break;
udelay(10);
}
WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
RD_REG_DWORD(®->hccr); /* PCI Posting. */
for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 &&
rval == QLA_SUCCESS; cnt--) {
if (cnt)
udelay(100);
else
rval = QLA_FUNCTION_TIMEOUT;
}
return rval;
}
/**
* qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
* @ha: HA context
*
* Returns 0 on success.
*/
static inline void
qla24xx_reset_risc(scsi_qla_host_t *vha)
{
unsigned long flags = 0;
struct qla_hw_data *ha = vha->hw;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
uint32_t cnt, d2;
uint16_t wd;
static int abts_cnt; /* ISP abort retry counts */
spin_lock_irqsave(&ha->hardware_lock, flags);
/* Reset RISC. */
WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
for (cnt = 0; cnt < 30000; cnt++) {
if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
break;
udelay(10);
}
WRT_REG_DWORD(®->ctrl_status,
CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
udelay(100);
/* Wait for firmware to complete NVRAM accesses. */
d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
for (cnt = 10000 ; cnt && d2; cnt--) {
udelay(5);
d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
barrier();
}
/* Wait for soft-reset to complete. */
d2 = RD_REG_DWORD(®->ctrl_status);
for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
udelay(5);
d2 = RD_REG_DWORD(®->ctrl_status);
barrier();
}
/* If required, do an MPI FW reset now */
if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
if
static inline void
qla27xx_read32(void __iomem *window, void *buf, ulong *len)
{
uint32_t value = ~0;
if (buf) {
value = RD_REG_DWORD(window);
}
qla27xx_insert32(value, buf, len);
}
static inline int
qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
{
int rval = QLA_SUCCESS;
uint32_t cnt;
if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE)
return rval;
WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 &&
rval == QLA_SUCCESS; cnt--) {
if (cnt)
udelay(100);
else
rval = QLA_FUNCTION_TIMEOUT;
}
return rval;
}
static uint32_t *
qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
uint32_t count, uint32_t *buf)
{
uint32_t __iomem *dmp_reg;
WRT_REG_DWORD(®->iobase_addr, iobase);
dmp_reg = ®->iobase_window;
while (count--)
*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
return buf;
}
/**
* qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
* @ha: HA context
*
* Returns 0 on success.
*/
int
qla24xx_pci_config(scsi_qla_host_t *vha)
{
uint16_t w;
unsigned long flags = 0;
struct qla_hw_data *ha = vha->hw;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
pci_set_master(ha->pdev);
pci_try_set_mwi(ha->pdev);
pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
w &= ~PCI_COMMAND_INTX_DISABLE;
pci_write_config_word(ha->pdev, PCI_COMMAND, w);
pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
/* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
pcix_set_mmrbc(ha->pdev, 2048);
/* PCIe -- adjust Maximum Read Request Size (2048). */
if (pci_is_pcie(ha->pdev))
pcie_set_readrq(ha->pdev, 2048);
pci_disable_rom(ha->pdev);
ha->chip_revision = ha->pdev->revision;
/* Get PCI bus information. */
spin_lock_irqsave(&ha->hardware_lock, flags);
ha->pci_attr = RD_REG_DWORD(®->ctrl_status);
spin_unlock_irqrestore(&ha->hardware_lock, flags);
return QLA_SUCCESS;
}
/**
* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
* @ha: HA context
* @hardware_locked: Called with the hardware_lock
*/
void
qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
{
int rval;
uint32_t cnt, timer;
uint32_t risc_address;
uint16_t mb0, mb2;
uint32_t stat;
device_reg_t __iomem *reg = ha->iobase;
uint16_t __iomem *dmp_reg;
unsigned long flags;
struct qla2300_fw_dump *fw;
uint32_t dump_size, data_ram_cnt;
risc_address = data_ram_cnt = 0;
mb0 = mb2 = 0;
flags = 0;
if (!hardware_locked)
spin_lock_irqsave(&ha->hardware_lock, flags);
if (ha->fw_dump != NULL) {
qla_printk(KERN_WARNING, ha,
"Firmware has been previously dumped (%p) -- ignoring "
"request...\n", ha->fw_dump);
goto qla2300_fw_dump_failed;
}
/* Allocate (large) dump buffer. */
dump_size = sizeof(struct qla2300_fw_dump);
dump_size += (ha->fw_memory_size - 0x11000) * sizeof(uint16_t);
ha->fw_dump_order = get_order(dump_size);
ha->fw_dump = (struct qla2300_fw_dump *) __get_free_pages(GFP_ATOMIC,
ha->fw_dump_order);
if (ha->fw_dump == NULL) {
qla_printk(KERN_WARNING, ha,
"Unable to allocated memory for firmware dump (%d/%d).\n",
ha->fw_dump_order, dump_size);
goto qla2300_fw_dump_failed;
}
fw = ha->fw_dump;
rval = QLA_SUCCESS;
fw->hccr = RD_REG_WORD(®->hccr);
/* Pause RISC. */
WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
if (IS_QLA2300(ha)) {
for (cnt = 30000;
(RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
rval == QLA_SUCCESS; cnt--) {
if (cnt)
udelay(100);
else
rval = QLA_FUNCTION_TIMEOUT;
}
} else {
RD_REG_WORD(®->hccr); /* PCI Posting. */
udelay(10);
}
if (rval == QLA_SUCCESS) {
dmp_reg = (uint16_t __iomem *)(reg + 0);
for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40);
for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->ctrl_status, 0x40);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->ctrl_status, 0x50);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->ctrl_status, 0x00);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->pcr, 0x2000);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->pcr, 0x2200);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->pcr, 0x2400);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->pcr, 0x2600);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->pcr, 0x2800);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->pcr, 0x2A00);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->pcr, 0x2C00);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->pcr, 0x2E00);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->ctrl_status, 0x10);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->ctrl_status, 0x20);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
WRT_REG_WORD(®->ctrl_status, 0x30);
dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
/* Reset RISC. */
WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
for (cnt = 0; cnt < 30000; cnt++) {
if ((RD_REG_WORD(®->ctrl_status) &
CSR_ISP_SOFT_RESET) == 0)
break;
udelay(10);
}
}
if (!IS_QLA2300(ha)) {
for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
rval == QLA_SUCCESS; cnt--) {
if (cnt)
udelay(100);
else
rval = QLA_FUNCTION_TIMEOUT;
}
}
if (rval == QLA_SUCCESS) {
/* Get RISC SRAM. */
risc_address = 0x800;
WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
}
for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
cnt++, risc_address++) {
WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address);
WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
for (timer = 6000000; timer; timer--) {
/* Check for pending interrupts. */
stat = RD_REG_DWORD(®->u.isp2300.host_status);
if (stat & HSR_RISC_INT) {
stat &= 0xff;
if (stat == 0x1 || stat == 0x2) {
set_bit(MBX_INTERRUPT,
&ha->mbx_cmd_flags);
mb0 = RD_MAILBOX_REG(ha, reg, 0);
mb2 = RD_MAILBOX_REG(ha, reg, 2);
/* Release mailbox registers. */
WRT_REG_WORD(®->semaphore, 0);
WRT_REG_WORD(®->hccr,
HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
break;
} else if (stat == 0x10 || stat == 0x11) {
set_bit(MBX_INTERRUPT,
&ha->mbx_cmd_flags);
mb0 = RD_MAILBOX_REG(ha, reg, 0);
mb2 = RD_MAILBOX_REG(ha, reg, 2);
WRT_REG_WORD(®->hccr,
HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
break;
}
/* clear this intr; it wasn't a mailbox intr */
WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
}
udelay(5);
}
if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
rval = mb0 & MBS_MASK;
fw->risc_ram[cnt] = mb2;
} else {
rval = QLA_FUNCTION_FAILED;
}
}
if (rval == QLA_SUCCESS) {
/* Get stack SRAM. */
risc_address = 0x10000;
WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
}
for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS;
cnt++, risc_address++) {
WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
for (timer = 6000000; timer; timer--) {
/* Check for pending interrupts. */
stat = RD_REG_DWORD(®->u.isp2300.host_status);
if (stat & HSR_RISC_INT) {
stat &= 0xff;
if (stat == 0x1 || stat == 0x2) {
set_bit(MBX_INTERRUPT,
&ha->mbx_cmd_flags);
mb0 = RD_MAILBOX_REG(ha, reg, 0);
mb2 = RD_MAILBOX_REG(ha, reg, 2);
/* Release mailbox registers. */
WRT_REG_WORD(®->semaphore, 0);
WRT_REG_WORD(®->hccr,
HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
break;
} else if (stat == 0x10 || stat == 0x11) {
set_bit(MBX_INTERRUPT,
&ha->mbx_cmd_flags);
mb0 = RD_MAILBOX_REG(ha, reg, 0);
mb2 = RD_MAILBOX_REG(ha, reg, 2);
WRT_REG_WORD(®->hccr,
HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
break;
}
/* clear this intr; it wasn't a mailbox intr */
WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
}
udelay(5);
}
if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
rval = mb0 & MBS_MASK;
fw->stack_ram[cnt] = mb2;
} else {
rval = QLA_FUNCTION_FAILED;
}
}
if (rval == QLA_SUCCESS) {
/* Get data SRAM. */
risc_address = 0x11000;
data_ram_cnt = ha->fw_memory_size - risc_address + 1;
WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
}
for (cnt = 0; cnt < data_ram_cnt && rval == QLA_SUCCESS;
cnt++, risc_address++) {
WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
for (timer = 6000000; timer; timer--) {
/* Check for pending interrupts. */
stat = RD_REG_DWORD(®->u.isp2300.host_status);
if (stat & HSR_RISC_INT) {
stat &= 0xff;
if (stat == 0x1 || stat == 0x2) {
set_bit(MBX_INTERRUPT,
&ha->mbx_cmd_flags);
mb0 = RD_MAILBOX_REG(ha, reg, 0);
mb2 = RD_MAILBOX_REG(ha, reg, 2);
/* Release mailbox registers. */
WRT_REG_WORD(®->semaphore, 0);
WRT_REG_WORD(®->hccr,
HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
break;
} else if (stat == 0x10 || stat == 0x11) {
set_bit(MBX_INTERRUPT,
&ha->mbx_cmd_flags);
mb0 = RD_MAILBOX_REG(ha, reg, 0);
mb2 = RD_MAILBOX_REG(ha, reg, 2);
WRT_REG_WORD(®->hccr,
HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
break;
}
/* clear this intr; it wasn't a mailbox intr */
WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
}
udelay(5);
}
if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
rval = mb0 & MBS_MASK;
fw->data_ram[cnt] = mb2;
} else {
rval = QLA_FUNCTION_FAILED;
}
}
if (rval != QLA_SUCCESS) {
qla_printk(KERN_WARNING, ha,
"Failed to dump firmware (%x)!!!\n", rval);
free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
ha->fw_dump = NULL;
} else {
qla_printk(KERN_INFO, ha,
"Firmware dump saved to temp buffer (%ld/%p).\n",
ha->host_no, ha->fw_dump);
}
qla2300_fw_dump_failed:
if (!hardware_locked)
spin_unlock_irqrestore(&ha->hardware_lock, flags);
}
/**
* qla2x00_intr_handler() - Process interrupts for the ISP.
* @irq:
* @dev_id: SCSI driver HA context
* @regs:
*
* Called by system whenever the host adapter generates an interrupt.
*
* Returns handled flag.
*/
irqreturn_t
qla2x00_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
{
scsi_qla_host_t *ha;
device_reg_t *reg;
uint32_t mbx;
int status = 0;
unsigned long flags = 0;
unsigned long mbx_flags = 0;
unsigned long intr_iter;
uint32_t stat;
uint16_t hccr;
/* Don't loop forever, interrupt are OFF */
intr_iter = 50;
ha = (scsi_qla_host_t *) dev_id;
if (!ha) {
printk(KERN_INFO
"%s(): NULL host pointer\n", __func__);
return (IRQ_NONE);
}
reg = ha->iobase;
spin_lock_irqsave(&ha->hardware_lock, flags);
for (;;) {
/* Relax CPU! */
if (!(intr_iter--))
break;
if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
if ((RD_REG_WORD(®->istatus) & ISR_RISC_INT) == 0)
break;
if (RD_REG_WORD(®->semaphore) & BIT_0) {
WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
/* Get mailbox data. */
mbx = RD_MAILBOX_REG(ha, reg, 0);
if (mbx > 0x3fff && mbx < 0x8000) {
qla2x00_mbx_completion(ha,
(uint16_t)mbx);
status |= MBX_INTERRUPT;
} else if (mbx > 0x7fff && mbx < 0xc000) {
qla2x00_async_event(ha, mbx);
} else {
/*EMPTY*/
DEBUG2(printk("scsi(%ld): Unrecognized "
"interrupt type (%d)\n",
ha->host_no, mbx));
}
/* Release mailbox registers. */
WRT_REG_WORD(®->semaphore, 0);
/* Workaround for ISP2100 chip. */
if (IS_QLA2100(ha))
RD_REG_WORD(®->semaphore);
} else {
qla2x00_process_response_queue(ha);
WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
}
} else /* IS_QLA23XX(ha) */ {
stat = RD_REG_DWORD(®->u.isp2300.host_status);
if ((stat & HSR_RISC_INT) == 0)
break;
mbx = MSW(stat);
switch (stat & 0xff) {
case 0x13:
qla2x00_process_response_queue(ha);
break;
case 0x1:
case 0x2:
case 0x10:
case 0x11:
qla2x00_mbx_completion(ha, (uint16_t)mbx);
status |= MBX_INTERRUPT;
/* Release mailbox registers. */
WRT_REG_WORD(®->semaphore, 0);
break;
case 0x12:
qla2x00_async_event(ha, mbx);
break;
case 0x15:
mbx = mbx << 16 | MBA_CMPLT_1_16BIT;
qla2x00_async_event(ha, mbx);
break;
case 0x16:
mbx = mbx << 16 | MBA_SCSI_COMPLETION;
qla2x00_async_event(ha, mbx);
break;
default:
hccr = RD_REG_WORD(®->hccr);
if (hccr & HCCR_RISC_PAUSE) {
qla_printk(KERN_INFO, ha,
"RISC paused, dumping HCCR=%x\n",
hccr);
/*
* Issue a "HARD" reset in order for
* the RISC interrupt bit to be
* cleared. Schedule a big hammmer to
* get out of the RISC PAUSED state.
*/
WRT_REG_WORD(®->hccr,
HCCR_RESET_RISC);
RD_REG_WORD(®->hccr);
set_bit(ISP_ABORT_NEEDED,
&ha->dpc_flags);
break;
} else {
DEBUG2(printk("scsi(%ld): Unrecognized "
"interrupt type (%d)\n",
ha->host_no, stat & 0xff));
}
break;
}
WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
RD_REG_WORD(®->hccr);
}
}
spin_unlock_irqrestore(&ha->hardware_lock, flags);
qla2x00_next(ha);
ha->last_irq_cpu = smp_processor_id();
ha->total_isr_cnt++;
if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
(status & MBX_INTERRUPT) && ha->flags.mbox_int) {
/* There was a mailbox completion */
DEBUG3(printk("%s(%ld): Going to get mbx reg lock.\n",
__func__, ha->host_no));
spin_lock_irqsave(&ha->mbx_reg_lock, mbx_flags);
if (ha->mcp == NULL) {
DEBUG3(printk("%s(%ld): Error mbx pointer.\n",
__func__, ha->host_no));
} else {
DEBUG3(printk("%s(%ld): Going to set mbx intr flags. "
"cmd=%x.\n",
__func__, ha->host_no, ha->mcp->mb[0]));
}
set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
DEBUG3(printk("%s(%ld): Going to wake up mbx function for "
"completion.\n",
__func__, ha->host_no));
up(&ha->mbx_intr_sem);
DEBUG3(printk("%s(%ld): Going to release mbx reg lock.\n",
__func__, ha->host_no));
spin_unlock_irqrestore(&ha->mbx_reg_lock, mbx_flags);
}
if (!list_empty(&ha->done_queue))
qla2x00_done(ha);
/* Wakeup the DPC routine */
if ((!ha->flags.mbox_busy &&
(test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) ||
test_bit(RESET_MARKER_NEEDED, &ha->dpc_flags) ||
test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))) &&
ha->dpc_wait && !ha->dpc_active) {
up(ha->dpc_wait);
}
return (IRQ_HANDLED);
}
/**
* qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
* @irq:
* @dev_id: SCSI driver HA context
* @regs:
*
* Called by system whenever the host adapter generates an interrupt.
*
* Returns handled flag.
*/
irqreturn_t
qla24xx_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
{
scsi_qla_host_t *ha;
struct device_reg_24xx __iomem *reg;
int status;
unsigned long flags;
unsigned long iter;
uint32_t stat;
uint32_t hccr;
uint16_t mb[4];
ha = (scsi_qla_host_t *) dev_id;
if (!ha) {
printk(KERN_INFO
"%s(): NULL host pointer\n", __func__);
return IRQ_NONE;
}
reg = &ha->iobase->isp24;
status = 0;
spin_lock_irqsave(&ha->hardware_lock, flags);
for (iter = 50; iter--; ) {
stat = RD_REG_DWORD(®->host_status);
if (stat & HSRX_RISC_PAUSED) {
hccr = RD_REG_DWORD(®->hccr);
qla_printk(KERN_INFO, ha, "RISC paused -- HCCR=%x, "
"Dumping firmware!\n", hccr);
qla24xx_fw_dump(ha, 1);
set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
break;
} else if ((stat & HSRX_RISC_INT) == 0)
break;
switch (stat & 0xff) {
case 0x1:
case 0x2:
case 0x10:
case 0x11:
qla24xx_mbx_completion(ha, MSW(stat));
status |= MBX_INTERRUPT;
break;
case 0x12:
mb[0] = MSW(stat);
mb[1] = RD_REG_WORD(®->mailbox1);
mb[2] = RD_REG_WORD(®->mailbox2);
mb[3] = RD_REG_WORD(®->mailbox3);
qla2x00_async_event(ha, mb);
break;
case 0x13:
qla24xx_process_response_queue(ha);
break;
default:
DEBUG2(printk("scsi(%ld): Unrecognized interrupt type "
"(%d).\n",
ha->host_no, stat & 0xff));
break;
}
WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
RD_REG_DWORD_RELAXED(®->hccr);
}
spin_unlock_irqrestore(&ha->hardware_lock, flags);
if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
(status & MBX_INTERRUPT) && ha->flags.mbox_int) {
spin_lock_irqsave(&ha->mbx_reg_lock, flags);
set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
up(&ha->mbx_intr_sem);
spin_unlock_irqrestore(&ha->mbx_reg_lock, flags);
}
return IRQ_HANDLED;
}
/**
* qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
* @irq:
* @dev_id: SCSI driver HA context
* @regs:
*
* Called by system whenever the host adapter generates an interrupt.
*
* Returns handled flag.
*/
irqreturn_t
qla2300_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
{
scsi_qla_host_t *ha;
struct device_reg_2xxx __iomem *reg;
int status;
unsigned long flags;
unsigned long iter;
uint32_t stat;
uint16_t hccr;
uint16_t mb[4];
ha = (scsi_qla_host_t *) dev_id;
if (!ha) {
printk(KERN_INFO
"%s(): NULL host pointer\n", __func__);
return (IRQ_NONE);
}
reg = &ha->iobase->isp;
status = 0;
spin_lock_irqsave(&ha->hardware_lock, flags);
for (iter = 50; iter--; ) {
stat = RD_REG_DWORD(®->u.isp2300.host_status);
if (stat & HSR_RISC_PAUSED) {
hccr = RD_REG_WORD(®->hccr);
if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
qla_printk(KERN_INFO, ha,
"Parity error -- HCCR=%x.\n", hccr);
else
qla_printk(KERN_INFO, ha,
"RISC paused -- HCCR=%x.\n", hccr);
/*
* Issue a "HARD" reset in order for the RISC
* interrupt bit to be cleared. Schedule a big
* hammmer to get out of the RISC PAUSED state.
*/
WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
RD_REG_WORD(®->hccr);
set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
break;
} else if ((stat & HSR_RISC_INT) == 0)
break;
switch (stat & 0xff) {
case 0x1:
case 0x2:
case 0x10:
case 0x11:
qla2x00_mbx_completion(ha, MSW(stat));
status |= MBX_INTERRUPT;
/* Release mailbox registers. */
WRT_REG_WORD(®->semaphore, 0);
break;
case 0x12:
mb[0] = MSW(stat);
mb[1] = RD_MAILBOX_REG(ha, reg, 1);
mb[2] = RD_MAILBOX_REG(ha, reg, 2);
mb[3] = RD_MAILBOX_REG(ha, reg, 3);
qla2x00_async_event(ha, mb);
break;
case 0x13:
qla2x00_process_response_queue(ha);
break;
case 0x15:
mb[0] = MBA_CMPLT_1_16BIT;
mb[1] = MSW(stat);
qla2x00_async_event(ha, mb);
break;
case 0x16:
mb[0] = MBA_SCSI_COMPLETION;
mb[1] = MSW(stat);
mb[2] = RD_MAILBOX_REG(ha, reg, 2);
qla2x00_async_event(ha, mb);
break;
default:
DEBUG2(printk("scsi(%ld): Unrecognized interrupt type "
"(%d).\n",
ha->host_no, stat & 0xff));
break;
}
WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
RD_REG_WORD_RELAXED(®->hccr);
}
spin_unlock_irqrestore(&ha->hardware_lock, flags);
if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
(status & MBX_INTERRUPT) && ha->flags.mbox_int) {
spin_lock_irqsave(&ha->mbx_reg_lock, flags);
set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
up(&ha->mbx_intr_sem);
spin_unlock_irqrestore(&ha->mbx_reg_lock, flags);
}
return (IRQ_HANDLED);
}
/**************************************************************************
* qla4xxx_mailbox_command
* This routine sssue mailbox commands and waits for completion.
*
* Input:
* ha - Pointer to host adapter structure.
* inCount - number of mailbox registers to load.
* outCount - number of mailbox registers to return.
* mbx_cmd - data pointer for mailbox in registers.
* mbx_sts - data pointer for mailbox out registers.
*
* Output:
* mbx_sts - returned mailbox out data.
*
* Remarks:
* If outCount is 0, this routine completes successfully WITHOUT waiting
* for the mailbox command to complete.
*
* Returns:
* QLA_SUCCESS - Mailbox command completed successfully
* QLA_ERROR - Mailbox command competed in error.
*
* Context:
* Kernel context.
**************************************************************************/
uint8_t
qla4xxx_mailbox_command(scsi_qla_host_t *ha,
uint8_t inCount,
uint8_t outCount,
uint32_t *mbx_cmd,
uint32_t *mbx_sts)
{
uint8_t status = QLA_ERROR;
uint8_t i;
u_long wait_count;
uint32_t intr_status;
unsigned long flags = 0;
DECLARE_WAITQUEUE(wait, current);
down(&ha->mbox_sem);
set_bit(AF_MBOX_COMMAND, &ha->flags);
/* Make sure that pointers are valid */
if (!mbx_cmd || !mbx_sts) {
QL4PRINT(QLP2,
printk("scsi%d: %s: Invalid mbx_cmd or mbx_sts pointer\n",
ha->host_no, __func__));
goto mbox_exit;
}
/* To prevent overwriting mailbox registers for a command that has
* not yet been serviced, check to see if a previously issued
* mailbox command is interrupting.
* -----------------------------------------------------------------
*/
spin_lock_irqsave(&ha->hardware_lock, flags);
intr_status = RD_REG_DWORD(&ha->reg->ctrl_status);
if (intr_status & CSR_SCSI_PROCESSOR_INTR) {
QL4PRINT(QLP5,
printk("scsi%d: %s: Trying to execute a mailbox request, "
"while another one is interrupting\n"
"Service existing interrupt first\n",
ha->host_no, __func__));
/* Service existing interrupt */
qla4xxx_interrupt_service_routine(ha, intr_status);
clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
}
/* Send the mailbox command to the firmware
* ----------------------------------------
*/
ha->f_start = jiffies;
ha->mbox_status_count = outCount;
for (i=0; i < MBOX_REG_COUNT; i++) {
ha->mbox_status[i] = 0;
}
for (i=0; i<inCount; i++) {
QL4PRINT(QLP11, printk("scsi%d: %s: Mailbox In[%d] 0x%08X\n",
ha->host_no, __func__, i, mbx_cmd[i]));
}
/* Load all mailbox registers, except mailbox 0.*/
for (i = 1; i < inCount; i++) {
WRT_REG_DWORD(&ha->reg->mailbox[i], mbx_cmd[i]);
}
for (i = inCount; i < MBOX_REG_COUNT; i++) {
WRT_REG_DWORD(&ha->reg->mailbox[i], 0);
}
/* Write Mailbox 0 to alert the firmware that the mailbox registers
* contain a command to be processed. NOTE: We could be interrupted
* here if system interrupts are enabled */
WRT_REG_DWORD(&ha->reg->mailbox[0], mbx_cmd[0]);
PCI_POSTING(&ha->reg->mailbox[0]);
WRT_REG_DWORD(&ha->reg->ctrl_status, SET_RMASK(CSR_INTR_RISC));
PCI_POSTING(&ha->reg->ctrl_status);
spin_unlock_irqrestore(&ha->hardware_lock, flags);
add_wait_queue(&ha->mailbox_wait_queue,&wait);
/*
* If we don't want status, don't wait for the mailbox command to
* complete. For example, MBOX_CMD_RESET_FW doesn't return status,
* you must poll the inbound Interrupt Mask for completion.
*/
if (outCount == 0) {
status = QLA_SUCCESS;
remove_wait_queue(&ha->mailbox_wait_queue,&wait);
ha->f_end = jiffies;
goto mbox_exit;
}
/*
* Wait for command to complete
* -----------------------------
*/
wait_count = jiffies + MBOX_TOV * HZ;
while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
if (time_after_eq(jiffies, wait_count)) {
break;
}
spin_lock_irqsave(&ha->hardware_lock, flags);
intr_status = RD_REG_DWORD(&ha->reg->ctrl_status);
QL4PRINT(QLP11, printk("scsi%d: %s: INTR_STATUS = 0x%X\n",
ha->host_no, __func__, intr_status));
if (intr_status & INTR_PENDING) {
/*
* Service the interrupt.
* The ISR will save the mailbox status registers
* to a temporary storage location in the adapter
* structure.
*/
ha->mbox_status_count = outCount;
qla4xxx_interrupt_service_routine(ha, intr_status);
if (!list_empty(&ha->done_srb_q))
qla4xxx_done(ha);
}
spin_unlock_irqrestore(&ha->hardware_lock, flags);
/*
* Delay for 10 microseconds
* NOTE: Interrupt_handler may be called here,
* if interrupts are enabled
*/
mdelay(10);
} /* wait loop */
remove_wait_queue(&ha->mailbox_wait_queue,&wait);
/*
* Check for mailbox timeout
*/
if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
QL4PRINT(QLP2,
printk("scsi%d: Mailbox Cmd 0x%08X timed out ...,"
" Scheduling Adapter Reset\n",
ha->host_no, mbx_cmd[0]));
ha->mailbox_timeout_count++;
mbx_sts[0] = (-1);
/*
* If the mailbox timed out due to CSR_SCSI_RESET_INTR,
* then the adapter will simply reinitialize, otherwise,
* a full on adapter reset will be done.
*/
if (qla4xxx_poll_and_ack_scsi_reset(ha) == QLA_ERROR)
set_bit(DPC_RESET_HA, &ha->dpc_flags);
goto mbox_exit;
}
QL4PRINT(QLP11,
printk("scsi%d: %s: mailbox cmd done!\n",
ha->host_no, __func__));
/*
* Copy the mailbox out registers to the caller's mailbox in/out
* structure.
*/
spin_lock_irqsave(&ha->hardware_lock, flags);
for (i=0; i < outCount; i++) {
mbx_sts[i] = ha->mbox_status[i];
QL4PRINT(QLP11,
printk("scsi%d: %s: Mailbox Status[%d] 0x%08X\n",
ha->host_no, __func__, i, mbx_sts[i]));
}
/*
* Set return status and error flags (if applicable)
*/
switch (ha->mbox_status[0]) {
case MBOX_STS_COMMAND_COMPLETE:
status = QLA_SUCCESS;
break;
case MBOX_STS_INTERMEDIATE_COMPLETION:
status = QLA_SUCCESS;
QL4PRINT(QLP5,
printk("scsi%d: %s: Cmd = %08X, Intermediate completion\n",
ha->host_no, __func__, mbx_cmd[0]));
break;
case MBOX_STS_BUSY:
QL4PRINT(QLP2, printk("scsi%d: %s: Cmd = %08X, ISP BUSY\n",
ha->host_no, __func__, mbx_cmd[0]));
ha->mailbox_timeout_count++;
break;
case MBOX_STS_COMMAND_PARAMETER_ERROR:
break;
case MBOX_STS_INVALID_COMMAND:
case MBOX_STS_HOST_INTERFACE_ERROR:
case MBOX_STS_TEST_FAILED:
case MBOX_STS_COMMAND_ERROR:
default:
QL4PRINT(QLP2,
printk("scsi%d: %s: **** FAILED, cmd = %08X, "
"sts = %08X ****\n",
ha->host_no, __func__, mbx_cmd[0], mbx_sts[0]));
__dump_registers(QLP2, ha);
break;
} /* switch mbox status */
spin_unlock_irqrestore(&ha->hardware_lock, flags);
mbox_exit:
clear_bit(AF_MBOX_COMMAND, &ha->flags);
clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
up(&ha->mbox_sem);
return(status);
}
void
qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
{
int rval;
uint32_t cnt;
uint32_t risc_address;
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
uint32_t __iomem *dmp_reg;
uint32_t *iter_reg;
uint16_t __iomem *mbx_reg;
unsigned long flags;
struct qla24xx_fw_dump *fw;
uint32_t ext_mem_cnt;
void *nxt;
risc_address = ext_mem_cnt = 0;
flags = 0;
if (!hardware_locked)
spin_lock_irqsave(&ha->hardware_lock, flags);
if (!ha->fw_dump) {
qla_printk(KERN_WARNING, ha,
"No buffer available for dump!!!\n");
goto qla24xx_fw_dump_failed;
}
if (ha->fw_dumped) {
qla_printk(KERN_WARNING, ha,
"Firmware has been previously dumped (%p) -- ignoring "
"request...\n", ha->fw_dump);
goto qla24xx_fw_dump_failed;
}
fw = &ha->fw_dump->isp.isp24;
qla2xxx_prep_dump(ha, ha->fw_dump);
fw->host_status = htonl(RD_REG_DWORD(®->host_status));
/* Pause RISC. */
rval = qla24xx_pause_risc(reg);
if (rval != QLA_SUCCESS)
goto qla24xx_fw_dump_failed_0;
/* Host interface registers. */
dmp_reg = ®->flash_addr;
for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
/* Disable interrupts. */
WRT_REG_DWORD(®->ictrl, 0);
RD_REG_DWORD(®->ictrl);
/* Shadow registers. */
WRT_REG_DWORD(®->iobase_addr, 0x0F70);
RD_REG_DWORD(®->iobase_addr);
WRT_REG_DWORD(®->iobase_select, 0xB0000000);
fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
WRT_REG_DWORD(®->iobase_select, 0xB0100000);
fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
WRT_REG_DWORD(®->iobase_select, 0xB0200000);
fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
WRT_REG_DWORD(®->iobase_select, 0xB0300000);
fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
WRT_REG_DWORD(®->iobase_select, 0xB0400000);
fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
WRT_REG_DWORD(®->iobase_select, 0xB0500000);
fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
WRT_REG_DWORD(®->iobase_select, 0xB0600000);
fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
/* Mailbox registers. */
mbx_reg = ®->mailbox0;
for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
/* Transfer sequence registers. */
iter_reg = fw->xseq_gp_reg;
iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
/* Receive sequence registers. */
iter_reg = fw->rseq_gp_reg;
iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
/* Command DMA registers. */
qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
/* Queues. */
iter_reg = fw->req0_dma_reg;
iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
dmp_reg = ®->iobase_q;
for (cnt = 0; cnt < 7; cnt++)
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
iter_reg = fw->resp0_dma_reg;
iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
dmp_reg = ®->iobase_q;
for (cnt = 0; cnt < 7; cnt++)
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
iter_reg = fw->req1_dma_reg;
iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
dmp_reg = ®->iobase_q;
for (cnt = 0; cnt < 7; cnt++)
*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
/* Transmit DMA registers. */
iter_reg = fw->xmt0_dma_reg;
iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
qla24xx_read_window(reg, 0x7610, 16, iter_reg);
iter_reg = fw->xmt1_dma_reg;
iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
qla24xx_read_window(reg, 0x7630, 16, iter_reg);
iter_reg = fw->xmt2_dma_reg;
iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
qla24xx_read_window(reg, 0x7650, 16, iter_reg);
iter_reg = fw->xmt3_dma_reg;
iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
qla24xx_read_window(reg, 0x7670, 16, iter_reg);
iter_reg = fw->xmt4_dma_reg;
iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
qla24xx_read_window(reg, 0x7690, 16, iter_reg);
qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
/* Receive DMA registers. */
iter_reg = fw->rcvt0_data_dma_reg;
iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
qla24xx_read_window(reg, 0x7710, 16, iter_reg);
iter_reg = fw->rcvt1_data_dma_reg;
iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
qla24xx_read_window(reg, 0x7730, 16, iter_reg);
/* RISC registers. */
iter_reg = fw->risc_gp_reg;
iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
/* Local memory controller registers. */
iter_reg = fw->lmc_reg;
iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
qla24xx_read_window(reg, 0x3060, 16, iter_reg);
/* Fibre Protocol Module registers. */
iter_reg = fw->fpm_hdw_reg;
iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
/* Frame Buffer registers. */
iter_reg = fw->fb_hdw_reg;
iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
rval = qla24xx_soft_reset(ha);
if (rval != QLA_SUCCESS)
goto qla24xx_fw_dump_failed_0;
rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
fw->ext_mem, &nxt);
if (rval != QLA_SUCCESS)
goto qla24xx_fw_dump_failed_0;
nxt = qla2xxx_copy_queues(ha, nxt);
if (ha->eft)
memcpy(nxt, ha->eft, ntohl(ha->fw_dump->eft_size));
qla24xx_fw_dump_failed_0:
if (rval != QLA_SUCCESS) {
qla_printk(KERN_WARNING, ha,
"Failed to dump firmware (%x)!!!\n", rval);
ha->fw_dumped = 0;
} else {
qla_printk(KERN_INFO, ha,
"Firmware dump saved to temp buffer (%ld/%p).\n",
ha->host_no, ha->fw_dump);
ha->fw_dumped = 1;
}
qla24xx_fw_dump_failed:
if (!hardware_locked)
spin_unlock_irqrestore(&ha->hardware_lock, flags);
}
static int
qla24xx_dump_memory(scsi_qla_host_t *ha, uint32_t *code_ram,
uint32_t cram_size, uint32_t *ext_mem, void **nxt)
{
int rval;
uint32_t cnt, stat, timer, risc_address, ext_mem_cnt;
uint16_t mb[4];
struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
rval = QLA_SUCCESS;
risc_address = ext_mem_cnt = 0;
memset(mb, 0, sizeof(mb));
/* Code RAM. */
risc_address = 0x20000;
WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED);
clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
for (cnt = 0; cnt < cram_size / 4 && rval == QLA_SUCCESS;
cnt++, risc_address++) {
WRT_REG_WORD(®->mailbox1, LSW(risc_address));
WRT_REG_WORD(®->mailbox8, MSW(risc_address));
RD_REG_WORD(®->mailbox8);
WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
for (timer = 6000000; timer; timer--) {
/* Check for pending interrupts. */
stat = RD_REG_DWORD(®->host_status);
if (stat & HSRX_RISC_INT) {
stat &= 0xff;
if (stat == 0x1 || stat == 0x2 ||
stat == 0x10 || stat == 0x11) {
set_bit(MBX_INTERRUPT,
&ha->mbx_cmd_flags);
mb[0] = RD_REG_WORD(®->mailbox0);
mb[2] = RD_REG_WORD(®->mailbox2);
mb[3] = RD_REG_WORD(®->mailbox3);
WRT_REG_DWORD(®->hccr,
HCCRX_CLR_RISC_INT);
RD_REG_DWORD(®->hccr);
break;
}
/* Clear this intr; it wasn't a mailbox intr */
WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
RD_REG_DWORD(®->hccr);
}
udelay(5);
}
if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
rval = mb[0] & MBS_MASK;
code_ram[cnt] = htonl((mb[3] << 16) | mb[2]);
} else {
rval = QLA_FUNCTION_FAILED;
}
}
if (rval == QLA_SUCCESS) {
/* External Memory. */
risc_address = 0x100000;
ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
WRT_REG_WORD(®->mailbox0, MBC_READ_RAM_EXTENDED);
clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
}
for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
cnt++, risc_address++) {
WRT_REG_WORD(®->mailbox1, LSW(risc_address));
WRT_REG_WORD(®->mailbox8, MSW(risc_address));
RD_REG_WORD(®->mailbox8);
WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
for (timer = 6000000; timer; timer--) {
/* Check for pending interrupts. */
stat = RD_REG_DWORD(®->host_status);
if (stat & HSRX_RISC_INT) {
stat &= 0xff;
if (stat == 0x1 || stat == 0x2 ||
stat == 0x10 || stat == 0x11) {
set_bit(MBX_INTERRUPT,
&ha->mbx_cmd_flags);
mb[0] = RD_REG_WORD(®->mailbox0);
mb[2] = RD_REG_WORD(®->mailbox2);
mb[3] = RD_REG_WORD(®->mailbox3);
WRT_REG_DWORD(®->hccr,
HCCRX_CLR_RISC_INT);
RD_REG_DWORD(®->hccr);
break;
}
/* Clear this intr; it wasn't a mailbox intr */
WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
RD_REG_DWORD(®->hccr);
}
udelay(5);
}
if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
rval = mb[0] & MBS_MASK;
ext_mem[cnt] = htonl((mb[3] << 16) | mb[2]);
} else {
rval = QLA_FUNCTION_FAILED;
}
}
*nxt = rval == QLA_SUCCESS ? &ext_mem[cnt]: NULL;
return rval;
}
/**
* qla2x00_req_pkt() - Retrieve a request packet from the request ring.
* @ha: HA context
*
* Note: The caller must hold the hardware lock before calling this routine.
*
* Returns NULL if function failed, else, a pointer to the request packet.
*/
static request_t *
qla2x00_req_pkt(scsi_qla_host_t *ha)
{
device_reg_t __iomem *reg = ha->iobase;
request_t *pkt = NULL;
uint16_t cnt;
uint32_t *dword_ptr;
uint32_t timer;
uint16_t req_cnt = 1;
/* Wait 1 second for slot. */
for (timer = HZ; timer; timer--) {
if ((req_cnt + 2) >= ha->req_q_cnt) {
/* Calculate number of free request entries. */
if (IS_QLA24XX(ha) || IS_QLA25XX(ha))
cnt = (uint16_t)RD_REG_DWORD(
®->isp24.req_q_out);
else
cnt = qla2x00_debounce_register(
ISP_REQ_Q_OUT(ha, ®->isp));
if (ha->req_ring_index < cnt)
ha->req_q_cnt = cnt - ha->req_ring_index;
else
ha->req_q_cnt = ha->request_q_length -
(ha->req_ring_index - cnt);
}
/* If room for request in request ring. */
if ((req_cnt + 2) < ha->req_q_cnt) {
ha->req_q_cnt--;
pkt = ha->request_ring_ptr;
/* Zero out packet. */
dword_ptr = (uint32_t *)pkt;
for (cnt = 0; cnt < REQUEST_ENTRY_SIZE / 4; cnt++)
*dword_ptr++ = 0;
/* Set system defined field. */
pkt->sys_define = (uint8_t)ha->req_ring_index;
/* Set entry count. */
pkt->entry_count = 1;
break;
}
/* Release ring specific lock */
spin_unlock(&ha->hardware_lock);
udelay(2); /* 2 us */
/* Check for pending interrupts. */
/* During init we issue marker directly */
if (!ha->marker_needed)
qla2x00_poll(ha);
spin_lock_irq(&ha->hardware_lock);
}
if (!pkt) {
DEBUG2_3(printk("%s(): **** FAILED ****\n", __func__));
}
return (pkt);
}
