static void combiner_intr(void *arg) { struct combiner_softc *sc; void (*ih) (void *); void *ih_user; int enabled; int intrs; int shift; int cirq; int grp; int i,n; sc = arg; intrs = READ4(sc, CIPSR); for (grp = 0; grp < 32; grp++) { if (intrs & (1 << grp)) { n = (grp / 4); shift = (grp % 4) * 8; cirq = READ4(sc, ISTR(n)); for (i = 0; i < 8; i++) { if (cirq & (1 << (i + shift))) { ih = intr_map[grp][i].ih; ih_user = intr_map[grp][i].ih_user; enabled = intr_map[grp][i].enabled; if (enabled && (ih != NULL)) { ih(ih_user); } } } } } }
static int mtk_gic_intr(void *arg) { struct mtk_gic_softc *sc = arg; struct thread *td; uint32_t i, intr; td = curthread; /* Workaround: do not inflate intr nesting level */ td->td_intr_nesting_level--; intr = READ4(sc, MTK_INTSTAT) & READ4(sc, MTK_INTMASK); while ((i = fls(intr)) != 0) { i--; intr &= ~(1u << i); if (intr_isrc_dispatch(GIC_INTR_ISRC(sc, i), curthread->td_intr_frame) != 0) { device_printf(sc->gic_dev, "Stray interrupt %u detected\n", i); gic_irq_mask(sc, i); continue; } } KASSERT(i == 0, ("all interrupts handled")); td->td_intr_nesting_level++; return (FILTER_HANDLED); }
int omgpio_irq(void *v) { struct omgpio_softc *sc = v; u_int32_t pending; struct intrhand *ih; int bit; pending = READ4(sc, omgpio.irqstatus0); while (pending != 0) { bit = ffs(pending) - 1; ih = sc->sc_handlers[bit]; if (ih != NULL) { if (ih->ih_func(ih->ih_arg)) ih->ih_count.ec_count++; omgpio_clear_intr(ih->ih_gpio); } else { panic("omgpio: irq fired no handler, gpio %x %x %x", sc->sc_dev.dv_unit * 32 + bit, pending, READ4(sc, omgpio.irqstatus0) ); } pending &= ~(1 << bit); } return 1; }
static int spi_attach(device_t dev) { struct spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); if (bus_alloc_resources(dev, spi_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); reg = READ4(sc, SPI_MCR); reg |= MCR_MSTR; reg &= ~(MCR_CONT_SCKE | MCR_MDIS | MCR_FRZ); reg &= ~(MCR_PCSIS_M << MCR_PCSIS_S); reg |= (MCR_PCSIS_M << MCR_PCSIS_S); /* PCS Active low */ reg |= (MCR_CLR_TXF | MCR_CLR_RXF); WRITE4(sc, SPI_MCR, reg); reg = READ4(sc, SPI_RSER); reg |= RSER_EOQF_RE; WRITE4(sc, SPI_RSER, reg); reg = READ4(sc, SPI_MCR); reg &= ~MCR_HALT; WRITE4(sc, SPI_MCR, reg); reg = READ4(sc, SPI_CTAR0); reg &= ~(CTAR_FMSZ_M << CTAR_FMSZ_S); reg |= (CTAR_FMSZ_8 << CTAR_FMSZ_S); /* * TODO: calculate BR * SCK baud rate = ( fsys / PBR ) * (1 + DBR) / BR * * reg &= ~(CTAR_BR_M << CTAR_BR_S); */ reg &= ~CTAR_CPOL; /* Polarity */ reg |= CTAR_CPHA; /* * Set LSB (Less significant bit first) * must be used for some applications, e.g. some LCDs */ reg |= CTAR_LSBFE; WRITE4(sc, SPI_CTAR0, reg); reg = READ4(sc, SPI_CTAR0); reg &= ~(CTAR_PBR_M << CTAR_PBR_S); reg |= (CTAR_PBR_7 << CTAR_PBR_S); WRITE4(sc, SPI_CTAR0, reg); device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); }
int omgpio_pin_read(void *arg, int pin) { struct omgpio_softc *sc = arg; u_int32_t reg; if(omgpio_pin_dir_read(sc, pin) == OMGPIO_DIR_IN) reg = READ4(sc, sc->sc_regs.datain); else reg = READ4(sc, sc->sc_regs.dataout); return (reg >> GPIO_PIN_TO_OFFSET(pin)) & 0x1; }
static int dma_setup(struct edma_softc *sc, struct tcd_conf *tcd) { struct edma_channel *ch; int chnum; int reg; chnum = tcd->channel; ch = &edma_map[chnum]; ch->ih = tcd->ih; ch->ih_user = tcd->ih_user; TCD_WRITE4(sc, DMA_TCDn_SADDR(chnum), tcd->saddr); TCD_WRITE4(sc, DMA_TCDn_DADDR(chnum), tcd->daddr); reg = (tcd->smod << TCD_ATTR_SMOD_SHIFT); reg |= (tcd->dmod << TCD_ATTR_DMOD_SHIFT); reg |= (tcd->ssize << TCD_ATTR_SSIZE_SHIFT); reg |= (tcd->dsize << TCD_ATTR_DSIZE_SHIFT); TCD_WRITE2(sc, DMA_TCDn_ATTR(chnum), reg); TCD_WRITE2(sc, DMA_TCDn_SOFF(chnum), tcd->soff); TCD_WRITE2(sc, DMA_TCDn_DOFF(chnum), tcd->doff); TCD_WRITE4(sc, DMA_TCDn_SLAST(chnum), tcd->slast); TCD_WRITE4(sc, DMA_TCDn_DLASTSGA(chnum), tcd->dlast_sga); TCD_WRITE4(sc, DMA_TCDn_NBYTES_MLOFFYES(chnum), tcd->nbytes); reg = tcd->nmajor; /* Current Major Iteration Count */ TCD_WRITE2(sc, DMA_TCDn_CITER_ELINKNO(chnum), reg); TCD_WRITE2(sc, DMA_TCDn_BITER_ELINKNO(chnum), reg); reg = (TCD_CSR_INTMAJOR); if(tcd->majorelink == 1) { reg |= TCD_CSR_MAJORELINK; reg |= (tcd->majorelinkch << TCD_CSR_MAJORELINKCH_SHIFT); } TCD_WRITE2(sc, DMA_TCDn_CSR(chnum), reg); /* Enable requests */ reg = READ4(sc, DMA_ERQ); reg |= (0x1 << chnum); WRITE4(sc, DMA_ERQ, reg); /* Enable error interrupts */ reg = READ4(sc, DMA_EEI); reg |= (0x1 << chnum); WRITE4(sc, DMA_EEI, reg); return (0); }
static void auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan) { uint32_t val; uint8_t port; uint32_t slot; port = chan->port; DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port)); chan->intr = 0; slot = ALI_PORT2SLOT(port); val = READ4(sc, ALI_DMACR); val |= 1 << (slot+16); /* pause */ val &= ~(1 << slot); /* no start */ WRITE4(sc, ALI_DMACR, val); WRITE1(sc, port + ALI_OFF_CR, 0); while (READ1(sc, port + ALI_OFF_CR)) ; /* reset whole DMA things */ WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR); /* clear interrupts */ WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC); WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port)); }
static void auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan, uint32_t start, uint32_t size, uint32_t blksize, void (*intr)(void *), void *arg) { uint32_t port, slot; uint32_t offs, val; chan->start = start; chan->ptr = 0; chan->p = chan->start; chan->end = chan->start + size; chan->blksize = blksize; chan->ack = 0; chan->intr = intr; chan->arg = arg; auacer_add_entry(chan); auacer_add_entry(chan); port = chan->port; slot = ALI_PORT2SLOT(port); WRITE1(sc, port + ALI_OFF_CIV, 0); WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK); offs = (char *)chan->dmalist - (char *)sc->sc_cdata; WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs); WRITE1(sc, port + ALI_OFF_CR, ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM); val = READ4(sc, ALI_DMACR); val &= ~(1 << (slot+16)); /* no pause */ val |= 1 << slot; /* start */ WRITE4(sc, ALI_DMACR, val); }
/* * IN transfer on EP0 * 1. SETUP IN(0) * 2. SETUP IN(0, ep0_zlp_reply) OUT * 3. SETUP IN(act=len, zero) OUT * 4. SETUP IN(act=len) OUT * 5. SETUP IN(act<len) OUT */ static void handle_ep0_in_req(td243fc_rev2_softc_t *sc) { td243fc_rev2_ep_t *ep = &sc->ep[1]; request_t *req = ep->req; DBG_V(DSLAVE_DCD, ("DCD: handle_ep0_in_req\n")); /* Canceled requests handled in abort */ if (req->status == REQUEST_CANCELLED) return; req->bytes_transferred = req->transfer_size - BFGET4(TD243FC_TTLBTECNT, READ4(TD243FC_EPN_PACKET_CONTROL_REG(0, 1))); /* Check if it is a completion on data stage */ if ((req->transfer_size && !req->ep0_zlp_reply) || (!req->transfer_size && req->ep0_zlp_reply)) { ep->req = NULL; /* Start status OUT status stage */ start_transfer(sc, 0, req); } else { req_finish(sc, 1, req, REQUEST_COMPLETED); } }
static int pad_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct pad_softc *sc; struct gpio_bank bank; int pin_shift; int reg; int i; sc = device_get_softc(dev); for (i = 0; i < sc->gpio_npins; i++) { if (sc->gpio_pins[i].gp_pin == pin) break; } if (i >= sc->gpio_npins) return (EINVAL); if (get_bank(sc, pin, &bank, &pin_shift) != 0) return (EINVAL); GPIO_LOCK(sc); reg = READ4(sc, bank.port, bank.con + 0x4); reg &= ~(PIN_OUT << pin_shift); if (value) reg |= (PIN_OUT << pin_shift); WRITE4(sc, bank.port, bank.con + 0x4, reg); GPIO_UNLOCK(sc); return (0); }
static int pad_pin_get(device_t dev, uint32_t pin, unsigned int *val) { struct gpio_bank bank; struct pad_softc *sc; int pin_shift; int i; sc = device_get_softc(dev); for (i = 0; i < sc->gpio_npins; i++) { if (sc->gpio_pins[i].gp_pin == pin) break; } if (i >= sc->gpio_npins) return (EINVAL); if (get_bank(sc, pin, &bank, &pin_shift) != 0) return (EINVAL); GPIO_LOCK(sc); if (READ4(sc, bank.port, bank.con + 0x4) & (1 << pin_shift)) *val = 1; else *val = 0; GPIO_UNLOCK(sc); return (0); }
static jresult_t td243fc_rev2_attach(jdevice_t dev) { td243fc_rev2_softc_t *sc = (td243fc_rev2_softc_t *)j_device_get_softc(dev); jbus_h bus = j_device_get_bus(dev); jresult_t rc; DBG_I(DSLAVE_DCD, ("DCD: Attaching controller: %s\n", j_device_get_nameunit(dev))); /* initializing device controller data */ sc->dev = dev; /* Due to DMA limitation - it's operating not with transfer size but with * "mega buffers" size we have to define all out requests as 64 bytes * alligned for ep0*/ rc = jdma_alloc(TD243FC_EP0_MAX_PACKET_SIZE, 0, &sc->dma_buf.vaddr, &sc->dma_buf.dma_addr, 0, &sc->dma_buf.cookie); KASSERT(!rc, ("Can't alloc dma buffer for EP0 OUT\n")); sc->dma_buf.buffer_size = TD243FC_EP0_MAX_PACKET_SIZE; sc->mem_res = j_bus_alloc_resource(bus, SYS_RES_MEMORY, 0); if (!sc->mem_res) { DBG_E(DSLAVE_DCD, ("DCD: Error allocating memory resource\n")); rc = JEINVAL; goto Error; } sc->irq_res = j_bus_alloc_resource(bus, SYS_RES_IRQ, 0); if (!sc->irq_res) { DBG_E(DSLAVE_DCD, ("DCD: Error allocating interrupt resource\n")); rc = JEINVAL; goto Error; } sc->sc_lock = NULL; jspinlock_init(&sc->sc_lock); dcd_hw_init(sc); rc = core_register_dcd(dev, &dcd_ops, &sc->core_ctx); if (rc) { DBG_E(DSLAVE_DCD, ("DCD: register_dcd failed, rc=%d\n", rc)); goto Error; } DBG_V(DSLAVE_DCD, ("DCD: TD243 attached, controller revision=%.2x\n", BFGET4(TD243FC_FCREV, READ4(TD243FC_HARDWARE_MODE_REG)))); return 0; Error: td243fc_rev2_detach(dev); return rc; }
static int adc_attach(device_t dev) { struct adc_softc *sc; int err; int reg; sc = device_get_softc(dev); if (bus_alloc_resources(dev, adc_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); adc_sc = sc; /* Setup interrupt handler */ err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, NULL, adc_intr, sc, &sc->ih); if (err) { device_printf(dev, "Unable to alloc interrupt resource.\n"); return (ENXIO); } /* Configure 12-bit mode */ reg = READ4(sc, ADC_CFG); reg &= ~(CFG_MODE_M << CFG_MODE_S); reg |= (CFG_MODE_12 << CFG_MODE_S); /* 12bit */ WRITE4(sc, ADC_CFG, reg); /* Configure for continuous conversion */ reg = READ4(sc, ADC_GC); reg |= (GC_ADCO | GC_AVGE); WRITE4(sc, ADC_GC, reg); /* Disable interrupts */ reg = READ4(sc, ADC_HC0); reg &= HC_AIEN; WRITE4(sc, ADC_HC0, reg); return (0); }
static void edma_err_intr(void *arg) { struct edma_softc *sc; int reg; sc = arg; reg = READ4(sc, DMA_ERR); #if 0 device_printf(sc->dev, "DMA_ERR 0x%08x, ES 0x%08x\n", reg, READ4(sc, DMA_ES)); #endif WRITE1(sc, DMA_CERR, CERR_CAEI); }
static int ccm_attach(device_t dev) { struct ccm_softc *sc; int reg; int i; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, ccm_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); /* Enable oscillator */ reg = READ4(sc, CCM_CCR); reg |= (FIRC_EN | FXOSC_EN); WRITE4(sc, CCM_CCR, reg); /* Wait 10 times */ for (i = 0; i < 10; i++) { if (READ4(sc, CCM_CSR) & FXOSC_RDY) { device_printf(sc->dev, "On board oscillator is ready.\n"); break; } cpufunc_nullop(); } /* Clock is on during all modes, except stop mode. */ for (i = 0; i < CCM_CCGRN; i++) { WRITE4(sc, CCM_CCGR(i), 0xffffffff); } /* Enable ENET clocks */ reg = READ4(sc, CCM_CSCDR1); reg |= (ENET_TS_EN | RMII_CLK_EN); WRITE4(sc, CCM_CSCDR1, reg); return (0); }
static int fimd_init(struct fimd_softc *sc) { struct panel_info *panel; int reg; panel = sc->panel; /* fb_init */ reg = panel->ivclk | panel->fixvclk; DWRITE4(sc,VIDCON1,reg); reg = (VIDCON0_ENVID | VIDCON0_ENVID_F); reg |= (panel->clkval_f << CLKVAL_F_OFFSET); WRITE4(sc,VIDCON0,reg); reg = (panel->v_pulse_width << VSYNC_PULSE_WIDTH_OFFSET); reg |= (panel->v_front_porch << V_FRONT_PORCH_OFFSET); reg |= (panel->v_back_porch << V_BACK_PORCH_OFFSET); DWRITE4(sc,VIDTCON0,reg); reg = (panel->h_pulse_width << HSYNC_PULSE_WIDTH_OFFSET); reg |= (panel->h_front_porch << H_FRONT_PORCH_OFFSET); reg |= (panel->h_back_porch << H_BACK_PORCH_OFFSET); DWRITE4(sc,VIDTCON1,reg); reg = ((panel->width - 1) << HOZVAL_OFFSET); reg |= ((panel->height - 1) << LINEVAL_OFFSET); DWRITE4(sc,VIDTCON2,reg); reg = sc->sc_info.fb_pbase; WRITE4(sc, VIDW00ADD0B0, reg); reg += (sc->sc_info.fb_stride * (sc->sc_info.fb_height + 1)); WRITE4(sc, VIDW00ADD1B0, reg); WRITE4(sc, VIDW00ADD2, sc->sc_info.fb_stride); reg = ((panel->width - 1) << OSD_RIGHTBOTX_F_OFFSET); reg |= ((panel->height - 1) << OSD_RIGHTBOTY_F_OFFSET); WRITE4(sc,VIDOSD0B,reg); reg = panel->width * panel->height; WRITE4(sc,VIDOSD0C,reg); reg = READ4(sc, SHADOWCON); reg |= CHANNEL0_EN; reg &= ~(1 << 5); /* disable local path for channel0 */ WRITE4(sc,SHADOWCON,reg); reg = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; reg |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; /* Note: swap=0 when ENLOCAL==1 */ reg &= ~ENLOCAL_F; /* use DMA */ WRITE4(sc,WINCON0,reg); /* Enable DisplayPort Clk */ WRITE4(sc, DPCLKCON, DPCLKCON_EN); return (0); }
static int parse_dbi_ex_header(char *data, int max_len, SDBIExHeader *dbi_ex_header) { ut32 read_bytes = 0, before_read_bytes = 0; READ4(read_bytes, max_len, dbi_ex_header->opened, data, ut32); before_read_bytes = read_bytes; read_bytes += parse_ssymbol_range (data, max_len, &dbi_ex_header->range); data += (read_bytes - before_read_bytes); READ2(read_bytes, max_len, dbi_ex_header->flags, data, ut16); READ2(read_bytes, max_len, dbi_ex_header->stream, data, st16); READ4(read_bytes, max_len, dbi_ex_header->symSize, data, ut32); READ4(read_bytes, max_len, dbi_ex_header->oldLineSize, data, ut32); READ4(read_bytes, max_len, dbi_ex_header->lineSize, data, ut32); READ2(read_bytes, max_len, dbi_ex_header->nSrcFiles, data, st16); READ2(read_bytes, max_len, dbi_ex_header->padding1, data, st16); READ4(read_bytes, max_len, dbi_ex_header->offsets, data, ut32); READ4(read_bytes, max_len, dbi_ex_header->niSource, data, ut32); READ4(read_bytes, max_len, dbi_ex_header->niCompiler, data, ut32); before_read_bytes = read_bytes; parse_sctring(&dbi_ex_header->modName, (unsigned char *)data, &read_bytes, max_len); data += (read_bytes - before_read_bytes); before_read_bytes = read_bytes; parse_sctring(&dbi_ex_header->objName, (unsigned char *)data, &read_bytes, max_len); data += (read_bytes - before_read_bytes); return read_bytes; }
static int pio_read(device_t dev) { struct pio_softc *sc; sc = device_get_softc(dev); return (READ4(sc, PIO_DATA)); }
static int auacer_set_params(void *v, int setmode, int usemode, audio_params_t *play, audio_params_t *rec, stream_filter_list_t *pfil, stream_filter_list_t *rfil) { struct auacer_softc *sc; struct audio_params *p; stream_filter_list_t *fil; uint32_t control; int mode, index; DPRINTF(ALI_DEBUG_API, ("auacer_set_params\n")); sc = v; for (mode = AUMODE_RECORD; mode != -1; mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { if ((setmode & mode) == 0) continue; p = mode == AUMODE_PLAY ? play : rec; if (p == NULL) continue; if ((p->sample_rate != 8000) && (p->sample_rate != 11025) && (p->sample_rate != 12000) && (p->sample_rate != 16000) && (p->sample_rate != 22050) && (p->sample_rate != 24000) && (p->sample_rate != 32000) && (p->sample_rate != 44100) && (p->sample_rate != 48000)) return (EINVAL); fil = mode == AUMODE_PLAY ? pfil : rfil; index = auconv_set_converter(sc->sc_formats, AUACER_NFORMATS, mode, p, TRUE, fil); if (index < 0) return EINVAL; if (fil->req_size > 0) p = &fil->filters[0].param; /* p points HW encoding */ if (sc->sc_formats[index].frequency_type != 1 && auacer_set_rate(sc, mode, p->sample_rate)) return EINVAL; if (mode == AUMODE_PLAY) { control = READ4(sc, ALI_SCR); control &= ~ALI_SCR_PCM_246_MASK; if (p->channels == 4) control |= ALI_SCR_PCM_4; else if (p->channels == 6) control |= ALI_SCR_PCM_6; WRITE4(sc, ALI_SCR, control); } } return (0); }
int omgpio_pin_dir_read(struct omgpio_softc *sc, unsigned int gpio) { u_int32_t reg; reg = READ4(sc, sc->sc_regs.oe); if (reg & (1 << GPIO_PIN_TO_OFFSET(gpio))) return OMGPIO_DIR_IN; else return OMGPIO_DIR_OUT; }
static void handle_ep0(td243fc_rev2_softc_t *sc, juint32_t ep_intr) { DBG_V(DSLAVE_DCD, ("DCD: handle_ep0\n")); if(READ4(TD243FC_EPN_CONFIG_CONTROL_REG(0, 1)) & TD243FC_STL) dcd_stall_ep(sc->dev, NULL, 0); if (ep_intr & TD243FC_EP_BIT(0, 1)) { handle_ep0_in_req(sc); } else { if (READ4(TD243FC_EPN_CONFIG_CONTROL_REG(0, 0)) & TD243FC_SETUP_RECV) handle_setup(sc); else handle_ep0_out_req(sc); } }
static void handle_reset(td243fc_rev2_softc_t *sc) { if (sc->is_suspend) { core_resume(sc->core_ctx); sc->is_suspend = 0; } core_disconnect(sc->core_ctx); sc->address = 0; set_hw_address(sc); sc->sys_intr_mask |= (TD243FC_SUSP | TD243FC_DONEREG); WRITE4(TD243FC_SYSTEM_INT_ENABLE_REG, sc->sys_intr_mask); /* Configure EP0 OUT for SETUP packet */ WRITE4(TD243FC_EPN_CONFIG_CONTROL_REG(0, 0), BFSET4(TD243FC_FORMAT, TD243FC_CTRL_EP) | BFSET4(TD243FC_MAXPKTSIZ, TD243FC_EP0_MAX_PACKET_SIZE)); WRITE4(TD243FC_EPN_XY_BUFFER_ADDRESS_REG(0,0), BFSET4(TD243FC_XBSA, TD243FC_GET_IADDR(sc->ep[0].xaddr)) | BFSET4(TD243FC_YBSA, TD243FC_GET_IADDR(sc->ep[0].yaddr))); /* Configure EP0 IN */ WRITE4(TD243FC_EPN_CONFIG_CONTROL_REG(0, 1), BFSET4(TD243FC_FORMAT, TD243FC_CTRL_EP) | BFSET4(TD243FC_MAXPKTSIZ, TD243FC_EP0_MAX_PACKET_SIZE)); WRITE4(TD243FC_EPN_XY_BUFFER_ADDRESS_REG(0,1), BFSET4(TD243FC_XBSA, TD243FC_GET_IADDR(sc->ep[1].xaddr)) | BFSET4(TD243FC_YBSA, TD243FC_GET_IADDR(sc->ep[1].yaddr))); /* Reset toggle for all endpoints */ WRITE4(TD243FC_EP_TOGGLE_REG, READ4(TD243FC_EP_TOGGLE_REG)); /* Enable EP0 */ ENABLE_EP(0, 0); ENABLE_EP(0, 1); WRITE4(TD243FC_EP_READY_REG, READ4(TD243FC_EP_READY_REG)); prepare_setup_transfer(sc); }
static int spi_txrx(struct spi_softc *sc, uint8_t *out_buf, uint8_t *in_buf, int bufsz, int cs) { uint32_t reg, wreg; uint32_t txcnt; uint32_t i; txcnt = 0; for (i = 0; i < bufsz; i++) { txcnt++; wreg = out_buf[i]; wreg |= PUSHR_CONT; wreg |= (cs << PUSHR_PCS_S); if (i == 0) wreg |= PUSHR_CTCNT; if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) wreg |= PUSHR_EOQ; WRITE4(sc, SPI_PUSHR, wreg); if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) { txcnt = 0; /* Wait last entry in a queue to be transmitted */ while((READ4(sc, SPI_SR) & SR_EOQF) == 0) continue; reg = READ4(sc, SPI_SR); reg |= (SR_TCF | SR_EOQF); WRITE4(sc, SPI_SR, reg); } /* Wait until RX FIFO is empty */ while((READ4(sc, SPI_SR) & SR_RFDF) == 0) continue; in_buf[i] = READ1(sc, SPI_POPR); } return (0); }
static jint_t dcd_intr(void* arg) { td243fc_rev2_softc_t *sc = (td243fc_rev2_softc_t *)arg; juint32_t chip_intr; chip_intr = READ4(TD243FC_CHIP_INT_STATUS_REG); if (!(chip_intr & TD243FC_INTF)) return ISR_DONT_CALL_SOFT_INTR; sc->sys_intr |= READ4(TD243FC_SYSTEM_INT_STATUS_REG); sc->ep_intr |= READ4(TD243FC_EP_DONE_STATUS_REG); sc->fc_cmd |= READ4(TD243FC_COMMAND_REG); /* Disable device controller global interrupt */ CLEAR4(TD243FC_SYSTEM_INT_ENABLE_REG, sc->sys_intr); CLEAR4(TD243FC_CHIP_INT_ENABLE_REG, TD243FC_INTF); return ISR_CALL_SOFT_INTR; }
static int dma_stop(struct edma_softc *sc, int chnum) { int reg; reg = READ4(sc, DMA_ERQ); reg &= ~(0x1 << chnum); WRITE4(sc, DMA_ERQ, reg); return (0); }
uint32_t adc_read(void) { struct adc_softc *sc; sc = adc_sc; if (sc == NULL) return (0); return (READ4(sc, ADC_R0)); }
static control_reg_t get_control_reg(struct beri_softc *sc, int dir) { uint32_t offset; uint16_t dst[4]; control_reg_t c; uint16_t *cp; int i; cp = (uint16_t *)&c; offset = dir ? sc->control_write : sc->control_read; ((uint32_t *)dst)[0] = READ4(sc, offset); ((uint32_t *)dst)[1] = READ4(sc, offset + 4); for (i = 0; i < 4; i++) cp[i] = dst[3 - i]; return (c); }
static void pad_pin_configure(struct pad_softc *sc, struct gpio_pin *pin, unsigned int flags) { struct gpio_bank bank; int pin_shift; int reg; GPIO_LOCK(sc); /* * Manage input/output */ if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); if (get_bank(sc, pin->gp_pin, &bank, &pin_shift) != 0) return; pin_shift *= 4; #if 0 printf("bank is 0x%08x pin_shift %d\n", bank.con, pin_shift); #endif if (flags & GPIO_PIN_OUTPUT) { pin->gp_flags |= GPIO_PIN_OUTPUT; reg = READ4(sc, bank.port, bank.con); reg &= ~(0xf << pin_shift); reg |= (PIN_OUT << pin_shift); WRITE4(sc, bank.port, bank.con, reg); } else { pin->gp_flags |= GPIO_PIN_INPUT; reg = READ4(sc, bank.port, bank.con); reg &= ~(0xf << pin_shift); WRITE4(sc, bank.port, bank.con, reg); } } GPIO_UNLOCK(sc); }
static int dwmmc_ctrl_reset(struct dwmmc_softc *sc, int reset_bits) { int reg; int i; reg = READ4(sc, SDMMC_CTRL); reg |= (reset_bits); WRITE4(sc, SDMMC_CTRL, reg); /* Wait reset done */ for (i = 0; i < 100; i++) { if (!(READ4(sc, SDMMC_CTRL) & reset_bits)) return (0); DELAY(10); } device_printf(sc->dev, "Reset failed\n"); return (1); }
static int auacer_sema_codec(struct auacer_softc *sc) { int ttime; ttime = 100; while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY)) delay(1); if (!ttime) aprint_normal("auacer_sema_codec: timeout\n"); return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY); }