static MFC_ERROR_CODE s3c_mfc_set_dec_frame_buffer(s3c_mfc_inst_ctx *MfcCtx, int buf_addr, unsigned int buf_size)
{
unsigned int Width, Height, FrameSize, dec_dpb_addr;
mfc_debug("buf_addr : 0x%08x buf_size : %d\n", buf_addr, buf_size);
Width = (MfcCtx->img_width + 15)/16*16;
Height = (MfcCtx->img_height + 31)/32*32;
FrameSize = (Width*Height*3)>>1;
mfc_debug("width : %d height : %d framesize : %d buf_size : %d MfcCtx->DPBCnt :%d\n", \
Width, Height, FrameSize, buf_size, MfcCtx->DPBCnt);
if(buf_size < FrameSize*MfcCtx->totalDPBCnt){
mfc_err("MFCINST_ERR_FRM_BUF_SIZE\n");
return MFCINST_ERR_FRM_BUF_SIZE;
}
WRITEL(Align(buf_addr, BUF_ALIGN_UNIT), S3C_FIMV_DEC_DPB_ADR);
dec_dpb_addr = READL(S3C_FIMV_DEC_DPB_ADR);
WRITEL(Align(dec_dpb_addr + FrameSize*MfcCtx->DPBCnt, BUF_ALIGN_UNIT), S3C_FIMV_DPB_COMV_ADR);
if((MfcCtx->MfcCodecType == MPEG4_DEC)
||(MfcCtx->MfcCodecType == MPEG2_DEC)
||(MfcCtx->MfcCodecType == XVID_DEC)
||(MfcCtx->MfcCodecType == DIVX_DEC) ) {
dec_dpb_addr = READL(S3C_FIMV_DEC_DPB_ADR);
WRITEL(Align(dec_dpb_addr + ((3*FrameSize*MfcCtx->DPBCnt)>>1), BUF_ALIGN_UNIT), S3C_FIMV_POST_ADR);
}
void mfc_interrupt_debug(int nCnt)
{
int nn =0;
for(nn = 0; nn <nCnt; nn++){
mdelay(100);
mfc_err("[%d] Timeout (0x64: 0x%08x) (0xF4: 0x%08x)\n", nn, READL(0x64), READL(0xF4));
}
}
static void update_window(struct display_controller *disp_ctrl,
struct soc_nvidia_tegra124_config *config)
{
u32 val;
WRITEL(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header);
WRITEL(((config->yres << 16) | config->xres), &disp_ctrl->win.size);
WRITEL(((config->yres << 16) |
(config->xres * config->framebuffer_bits_per_pixel / 8)),
&disp_ctrl->win.prescaled_size);
WRITEL(((config->xres * config->framebuffer_bits_per_pixel / 8 + 31) /
32 * 32), &disp_ctrl->win.line_stride);
WRITEL(config->color_depth, &disp_ctrl->win.color_depth);
WRITEL(config->framebuffer_base, &disp_ctrl->winbuf.start_addr);
WRITEL((V_DDA_INC(0x1000) | H_DDA_INC(0x1000)), &disp_ctrl->win.dda_increment);
WRITEL(COLOR_WHITE, &disp_ctrl->disp.blend_background_color);
WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
WRITEL(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
val |= GENERAL_UPDATE | WIN_A_UPDATE;
WRITEL(val, &disp_ctrl->cmd.state_ctrl);
// Enable win_a
val = READL(&disp_ctrl->win.win_opt);
WRITEL(val | WIN_ENABLE, &disp_ctrl->win.win_opt);
}
void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor)
{
u32 reg_val;
struct display_controller *disp_ctrl = (void *)sor->dc->base;
tegra_dc_sor_enable_dc(sor);
tegra_dc_sor_config_panel(sor, 0);
WRITEL(0x9f00, &disp_ctrl->cmd.state_ctrl);
WRITEL(0x9f, &disp_ctrl->cmd.state_ctrl);
WRITEL(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE |
PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
&disp_ctrl->cmd.disp_pow_ctrl);
reg_val = tegra_sor_readl(sor, NV_SOR_TEST);
if (reg_val & NV_SOR_TEST_ATTACHED_TRUE)
return;
tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
NV_SOR_SUPER_STATE1_ATTACHED_NO);
/*
* Enable display2sor clock at least 2 cycles before DC start,
* to clear sor internal valid signal.
*/
WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
WRITEL(0, &disp_ctrl->disp.disp_win_opt);
WRITEL(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);
/* Attach head */
tegra_dc_sor_update(sor);
tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
NV_SOR_SUPER_STATE1_ATTACHED_YES);
tegra_sor_writel(sor, NV_SOR_SUPER_STATE1,
NV_SOR_SUPER_STATE1_ATTACHED_YES |
NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE |
NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL);
tegra_dc_sor_super_update(sor);
/* Enable dc */
reg_val = READL(&disp_ctrl->cmd.state_access);
WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
WRITEL(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);
WRITEL(reg_val, &disp_ctrl->cmd.state_access);
if (tegra_dc_sor_poll_register(sor, NV_SOR_TEST,
NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK,
NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE,
100, TEGRA_SOR_ATTACH_TIMEOUT_MS * 1000))
printk(BIOS_ERR, "dc timeout waiting for OPMOD = AWAKE\n");
else
printk(BIOS_INFO, "%s: sor is attached\n", __func__);
#if DEBUG_SOR
dump_sor_reg(sor);
#endif
}
irqreturn_t mfc_irq(int irq, void *dev_id)
{
unsigned int int_reason;
unsigned int err_status;
int_reason = READL(MFC_RISC2HOST_COMMAND) & 0x1FFFF;
err_status = READL(MFC_RISC2HOST_ARG2);
mfc_disp_err_status = err_status >> 16;
mfc_dec_err_status = err_status & 0xFFFF;
mfc_debug_L0("mfc_irq() : Interrupt !! : %d\n", int_reason);
if( ((int_reason & R2H_CMD_EMPTY) == R2H_CMD_EMPTY) ||
((int_reason & R2H_CMD_OPEN_INSTANCE_RET) == R2H_CMD_OPEN_INSTANCE_RET) ||
((int_reason & R2H_CMD_CLOSE_INSTANCE_RET) == R2H_CMD_CLOSE_INSTANCE_RET) ||
((int_reason & R2H_CMD_ERROR_RET) == R2H_CMD_ERROR_RET) ||
((int_reason & R2H_CMD_SEQ_DONE_RET) == R2H_CMD_SEQ_DONE_RET) ||
((int_reason & R2H_CMD_FRAME_DONE_RET) == R2H_CMD_FRAME_DONE_RET) ||
((int_reason & R2H_CMD_SLICE_DONE_RET) == R2H_CMD_SLICE_DONE_RET) ||
((int_reason & R2H_CMD_ENC_COMPLETE_RET) == R2H_CMD_ENC_COMPLETE_RET) ||
((int_reason & R2H_CMD_SYS_INIT_RET) == R2H_CMD_SYS_INIT_RET) ||
((int_reason & R2H_CMD_FW_STATUS_RET) == R2H_CMD_FW_STATUS_RET) ||
((int_reason & R2H_CMD_SLEEP_RET) == R2H_CMD_SLEEP_RET) ||
((int_reason & R2H_CMD_WAKEUP_RET) == R2H_CMD_WAKEUP_RET) ||
((int_reason & R2H_CMD_FLUSH_COMMAND_RET) == R2H_CMD_FLUSH_COMMAND_RET) ||
((int_reason & R2H_CMD_CMD_ABORT_RET) == R2H_CMD_CMD_ABORT_RET) ||
((int_reason & R2H_CMD_CMD_BATCH_ENC_RET) == R2H_CMD_CMD_BATCH_ENC_RET) ||
((int_reason & R2H_CMD_INIT_BUFFERS_RET) == R2H_CMD_INIT_BUFFERS_RET) ||
((int_reason & R2H_CMD_EDFU_INT_RET) == R2H_CMD_EDFU_INT_RET) ||
((int_reason & R2H_CMD_DECODE_ERR_RET) == R2H_CMD_DECODE_ERR_RET))
{
mfc_int_type = int_reason;
wake_up_interruptible(&mfc_wait_queue);
}
else
mfc_info("Strange Interrupt !! : %d\n", int_reason);
WRITEL(0, MFC_RISC_HOST_INT);
WRITEL(0, MFC_RISC2HOST_COMMAND);
WRITEL(0xffff, MFC_SI_RTN_CHID);
return IRQ_HANDLED;
}
static int mfc_resume(struct platform_device *pdev)
{
int ret = 0;
unsigned int mc_status;
#if ENABLE_MONITORING_MFC_DD
mfc_info("mfc_resume......#1\n");
#endif
mutex_lock(&mfc_mutex);
if (!mfc_is_running())
{
#if ENABLE_MONITORING_MFC_DD
mfc_info("mfc_resume......#2-0\n");
#endif
mutex_unlock(&mfc_mutex);
return 0;
}
#if ENABLE_MONITORING_MFC_DD
mfc_info("mfc_resume......#2-1\n");
#endif
#if Frame_Base_Power_CTR_ON
clk_enable(mfc_clk);
#endif
/*
* 1. MFC reset
*/
do {
mc_status = READL(MFC_MC_STATUS);
} while(mc_status != 0);
mfc_cmd_reset();
WRITEL(mfc_port0_base_paddr, MFC_MC_DRAMBASE_ADDR_A);
WRITEL(mfc_port1_base_paddr, MFC_MC_DRAMBASE_ADDR_B);
WRITEL(1, MFC_NUM_MASTER);
ret = mfc_set_wakeup();
if(ret != MFCINST_RET_OK){
mutex_unlock(&mfc_mutex);
return ret;
}
#if Frame_Base_Power_CTR_ON
clk_disable(mfc_clk);
#endif
mutex_unlock(&mfc_mutex);
return 0;
}
static void tegra_dc_sor_io_set_dpd(struct tegra_dc_sor_data *sor, int up)
{
u32 reg_val;
void *pmc_base = sor->pmc_base;
if (up) {
WRITEL(APBDEV_PMC_DPD_SAMPLE_ON_ENABLE,
pmc_base + APBDEV_PMC_DPD_SAMPLE);
WRITEL(10, pmc_base + APBDEV_PMC_SEL_DPD_TIM);
}
reg_val = READL(pmc_base + APBDEV_PMC_IO_DPD2_REQ);
reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||
APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK);
reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |
APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF :
APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF |
APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON;
WRITEL(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);
/* Polling */
u32 temp = 10*1000;
do {
udelay(20);
reg_val = READL(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);
if (temp > 20)
temp -= 20;
else
break;
} while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);
if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0)
printk(BIOS_ERR,
"PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);
if (up)
WRITEL(APBDEV_PMC_DPD_SAMPLE_ON_DISABLE,
pmc_base + APBDEV_PMC_DPD_SAMPLE);
}
static void tegra_dc_sor_enable_dc(struct tegra_dc_sor_data *sor)
{
struct tegra_dc *dc = sor->dc;
struct display_controller *disp_ctrl = (void *)dc->base;
u32 reg_val = READL(&disp_ctrl->cmd.state_access);
WRITEL(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);
WRITEL(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);
/* Enable DC now - otherwise pure text console may not show. */
WRITEL(DISP_CTRL_MODE_C_DISPLAY, &disp_ctrl->cmd.disp_cmd);
WRITEL(reg_val, &disp_ctrl->cmd.state_access);
}
static int mfc_resume(struct platform_device *pdev)
{
int ret = 0;
unsigned int mc_status;
mutex_lock(&mfc_mutex);
if (!mfc_is_running()) {
mutex_unlock(&mfc_mutex);
return 0;
}
clk_enable(mfc_sclk);
/*
* 1. MFC reset
*/
do {
mc_status = READL(MFC_MC_STATUS);
} while (mc_status != 0);
if (mfc_cmd_reset() == false) {
clk_disable(mfc_sclk);
mutex_unlock(&mfc_mutex);
mfc_err("MFCINST_ERR_INIT_FAIL\n");
return MFCINST_ERR_INIT_FAIL;
}
WRITEL(mfc_port0_base_paddr, MFC_MC_DRAMBASE_ADDR_A);
WRITEL(mfc_port1_base_paddr, MFC_MC_DRAMBASE_ADDR_B);
WRITEL(1, MFC_NUM_MASTER);
ret = mfc_set_wakeup();
if (ret != MFCINST_RET_OK) {
clk_disable(mfc_sclk);
mutex_unlock(&mfc_mutex);
return ret;
}
clk_disable(mfc_sclk);
mutex_unlock(&mfc_mutex);
return 0;
}
void configure_gpio_output(u32 gpio_num)
{
u32 gpio_base_id = 0;
u32 gpio_offset = 0;
u32 gpio_oe_address = 0;
u32 oe_val = 0;
// error validation
if (!is_valid_gpio_number(gpio_num))
{
return;
}
// get basic gpio info
gpio_base_id = gpio_num / 32;
gpio_offset = gpio_num % 32;
gpio_oe_address = gpio_base_addresses[gpio_base_id] + OMAP4_GPIO_OE;
// read current value , mask in our single bit, then write
oe_val = READL(gpio_oe_address);
oe_val &= ~(1 << gpio_offset);
WRITEL(oe_val, gpio_oe_address);
}
u32 get_gpio_value(u32 gpio_num)
{
u32 gpio_base_id = gpio_num / 32;
u32 gpio_offset = gpio_num % 32;
u32 read_address = gpio_base_addresses[gpio_base_id];
u32 value = 0;
// error validation
if (!is_valid_gpio_number(gpio_num))
{
printf("Error, invalid gpio number\n");
return 0;
}
read_address += OMAP4_GPIO_DATAIN;
value = READL(read_address);
value = value >> gpio_offset;
value &= 1;
#if 0
printf("GPIO_DATAIN 0x%x\n", READL(0x4a310138));
printf("GPIO_IRQSTATUS 0x%x\n", READL(0x4a310020));
printf("GPIO_IRQSTATUS 0x%x\n", READL(0x4a31002c));
printf("GPIO_CONTROL 0x%x\n", READL(0x4a310010));
if (once){
volatile u8 reg = READL(0x4a310010); //enable wakeup pin
reg |= (1 << 2);
WRITEL(reg, 0x4a310010);
reg = READL(0x4a310044); //enable wakeup pin
reg |= (1 << 2);
WRITEL(reg, 0x4a310044);
once = 0;
}
#endif
return value;
}
/* Initialize decoding */
int hevc_init_decode(struct hevc_ctx *ctx)
{
struct hevc_dev *dev;
struct hevc_dec *dec;
unsigned int reg = 0, pix_val;
int fmo_aso_ctrl = 0;
hevc_debug_enter();
if (!ctx) {
hevc_err("no hevc context to run\n");
return -EINVAL;
}
dev = ctx->dev;
if (!dev) {
hevc_err("no hevc device to run\n");
return -EINVAL;
}
dec = ctx->dec_priv;
if (!dec) {
hevc_err("no hevc decoder to run\n");
return -EINVAL;
}
hevc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, HEVC_CH_SEQ_HEADER);
hevc_debug(2, "BUFs: %08x %08x %08x\n",
READL(HEVC_D_CPB_BUFFER_ADDR),
READL(HEVC_D_CPB_BUFFER_ADDR),
READL(HEVC_D_CPB_BUFFER_ADDR));
reg |= (dec->idr_decoding << HEVC_D_OPT_IDR_DECODING_SHFT);
/* FMO_ASO_CTRL - 0: Enable, 1: Disable */
reg |= (fmo_aso_ctrl << HEVC_D_OPT_FMO_ASO_CTRL_MASK);
/* When user sets desplay_delay to 0,
* It works as "display_delay enable" and delay set to 0.
* If user wants display_delay disable, It should be
* set to negative value. */
if (dec->display_delay >= 0) {
reg |= (0x1 << HEVC_D_OPT_DDELAY_EN_SHIFT);
WRITEL(dec->display_delay, HEVC_D_DISPLAY_DELAY);
}
if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
reg |= (0x1 << HEVC_D_OPT_TILE_MODE_SHIFT);
hevc_debug(2, "HEVC_D_DEC_OPTIONS : 0x%x\n", reg);
WRITEL(0x20, HEVC_D_DEC_OPTIONS);
switch (ctx->dst_fmt->fourcc) {
case V4L2_PIX_FMT_NV12M:
case V4L2_PIX_FMT_NV12MT_16X16:
pix_val = 0;
break;
case V4L2_PIX_FMT_NV21M:
pix_val = 1;
break;
case V4L2_PIX_FMT_YVU420M:
pix_val = 2;
break;
case V4L2_PIX_FMT_YUV420M:
pix_val = 3;
break;
default:
pix_val = 0;
break;
}
hevc_debug(2, "pixel format: %d\n", pix_val);
WRITEL(pix_val, HEVC_PIXEL_FORMAT);
/* sei parse */
reg = dec->sei_parse;
hevc_debug(2, "sei parse: %d\n", dec->sei_parse);
/* Enable realloc interface if SEI is enabled */
if (dec->sei_parse)
reg |= (0x1 << HEVC_D_SEI_NEED_INIT_BUFFER_SHIFT);
WRITEL(reg, HEVC_D_SEI_ENABLE);
WRITEL(ctx->inst_no, HEVC_INSTANCE_ID);
WRITEL(0xffffffff, HEVC_D_AVAILABLE_DPB_FLAG_UPPER);
WRITEL(0xffffffff, HEVC_D_AVAILABLE_DPB_FLAG_LOWER);
hevc_cmd_host2risc(HEVC_CH_SEQ_HEADER, NULL);
hevc_debug_leave();
return 0;
}
int mfc_wait_for_done(mfc_wait_done_type command)
{
unsigned int nwait_time = 100;
unsigned int ret_val = 1;
if((command == R2H_CMD_CLOSE_INSTANCE_RET) ||
(command == R2H_CMD_OPEN_INSTANCE_RET) ||
(command == R2H_CMD_FW_STATUS_RET))
nwait_time = MFC_WAIT_4_TIME;
else
nwait_time = MFC_WAIT_2_TIME;
#if defined(MFC_REQUEST_TIME)
long sec, msec;
#endif
#if defined(MFC_POLLING)
unsigned long timeo = jiffies;
timeo += 20; /* waiting for 100ms */
#endif
//set_user_nice(current, -20);
#if defined(MFC_REQUEST_TIME)
do_gettimeofday(&mfc_wakeup_before);
if (mfc_wakeup_before.tv_usec - mfc_wakeup_after.tv_usec < 0)
{
msec = 1000000 + mfc_wakeup_before.tv_usec - mfc_wakeup_after.tv_usec;
sec = mfc_wakeup_before.tv_sec - mfc_wakeup_after.tv_sec - 1;
}
else
{
msec = mfc_wakeup_before.tv_usec - mfc_wakeup_after.tv_usec;
sec = mfc_wakeup_before.tv_sec - mfc_wakeup_after.tv_sec;
}
#endif
#if defined(MFC_POLLING)
while (time_before(jiffies, timeo))
{
ret_val = READL(MFC_RISC2HOST_COMMAND) & 0x1ffff;
if (ret_val != 0)
{
WRITEL(0, MFC_RISC_HOST_INT);
WRITEL(0, MFC_RISC2HOST_COMMAND);
WRITEL(0xffff, MFC_SI_RTN_CHID);
mfc_int_type = ret_val;
break;
}
msleep_interruptible(2);
}
if (ret_val == 0)
printk("MFC timeouted!\n");
#else
if (interruptible_sleep_on_timeout(&mfc_wait_queue, nwait_time) == 0)
{
ret_val = R2H_CMD_TIMEOUT;
mfc_err("Interrupt Time Out(Cmd: %d) (Ver: 0x%08x) (0x64: 0x%08x) (0xF4: 0x%08x) (0x80: 0x%08x)\n", command, READL(0x58), READL(0x64), READL(0xF4),READL(0x80));
#if ENABLE_MFC_INTERRUPT_DEBUG // For MFC Interrupt Debugging.
mfc_interrupt_debug(10);
#endif
mfc_int_type = ret_val;
return ret_val;
}
else if (mfc_int_type == R2H_CMD_DECODE_ERR_RET)
{
mfc_err("MFC Error Returned Disp Error Status(%d), Dec Error Status(%d)\n", mfc_disp_err_status, mfc_dec_err_status );
}
else if (command != mfc_int_type)
{
mfc_err("Interrupt Error Returned (%d) waiting for (%d)\n", mfc_int_type, command);
}
#endif
#if defined(MFC_REQUEST_TIME)
do_gettimeofday(&mfc_wakeup_after);
if (mfc_wakeup_after.tv_usec - mfc_wakeup_before.tv_usec < 0)
{
msec = 1000000 + mfc_wakeup_after.tv_usec - mfc_wakeup_before.tv_usec;
sec = mfc_wakeup_after.tv_sec - mfc_wakeup_before.tv_sec - 1;
}
else
{
msec = mfc_wakeup_after.tv_usec - mfc_wakeup_before.tv_usec;
sec = mfc_wakeup_after.tv_sec - mfc_wakeup_before.tv_sec;
}
mfc_info("mfc_wait_for_done: mfc request interval time is %ld(sec), %ld(msec)\n", sec, msec);
#endif
ret_val = mfc_int_type;
mfc_int_type = 0;
return ret_val;
}
}
WRITEL(Align(buf_addr, BUF_ALIGN_UNIT), S3C_FIMV_DEC_DPB_ADR);
dec_dpb_addr = READL(S3C_FIMV_DEC_DPB_ADR);
WRITEL(Align(dec_dpb_addr + FrameSize*MfcCtx->DPBCnt, BUF_ALIGN_UNIT), S3C_FIMV_DPB_COMV_ADR);
if((MfcCtx->MfcCodecType == MPEG4_DEC)
||(MfcCtx->MfcCodecType == MPEG2_DEC)
||(MfcCtx->MfcCodecType == XVID_DEC)
||(MfcCtx->MfcCodecType == DIVX_DEC) ) {
dec_dpb_addr = READL(S3C_FIMV_DEC_DPB_ADR);
WRITEL(Align(dec_dpb_addr + ((3*FrameSize*MfcCtx->DPBCnt)>>1), BUF_ALIGN_UNIT), S3C_FIMV_POST_ADR);
}
mfc_debug("DEC_DPB_ADR : 0x%08x DPB_COMV_ADR : 0x%08x POST_ADR : 0x%08x\n", \
READL(S3C_FIMV_DEC_DPB_ADR), READL(S3C_FIMV_DPB_COMV_ADR), READL(S3C_FIMV_POST_ADR));
return MFCINST_RET_OK;
}
static MFC_ERROR_CODE s3c_mfc_set_vsp_buffer(int InstNo)
{
unsigned int VSPPhyBuf;
VSPPhyBuf = s3c_mfc_get_vsp_buf_phys_addr(InstNo);
WRITEL(Align(VSPPhyBuf, BUF_ALIGN_UNIT), S3C_FIMV_VSP_BUF_ADDR);
WRITEL(Align(VSPPhyBuf + VSP_BUF_SIZE, BUF_ALIGN_UNIT), S3C_FIMV_DB_STT_ADDR);
mfc_debug("InstNo : %d VSP_BUF_ADDR : 0x%08x DB_STT_ADDR : 0x%08x\n", \
InstNo, READL(S3C_FIMV_VSP_BUF_ADDR), READL(S3C_FIMV_DB_STT_ADDR));
static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
{
void *addr = dp->aux_base + (u32)(reg <<2);
u32 reg_val = READL(addr);
return reg_val;
}
static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
{
void *addr = sor->base + (u32) (reg << 2);
u32 reg_val = READL(addr);
return reg_val;
}
