unsigned long rtl865x_getTimer1PassedJiffies(void) { unsigned long jifPassed=0; unsigned long currTC1CNT; unsigned long tc0data; //tc0data = READ_MEM32(TC0DATA)>>TCD_OFFSET; tc0data =((MHZ * 250) / HZ); /* compute passed time since last time executed this function */ #ifdef CONFIG_RTL8196C_REVISION_B currTC1CNT = READ_MEM32(TC1CNT) & 0xfffffff0; #else currTC1CNT = READ_MEM32(TC1CNT) & 0xffffff00; #endif #if defined(CONFIG_RTL_819X) /* In RTL865xC, timer / counter is incremental */ #ifdef CONFIG_RTL8196C_REVISION_B if ( previousTC1CNT <= currTC1CNT ) { /* No wrap happend. */ tuRemainder += (currTC1CNT-previousTC1CNT)>>4; /* how many units are passed since last check? */ }
void rtl865x_setupTimer1(void) { WRITE_MEM32( TCCNR, READ_MEM32(TCCNR) & ~TC1EN );/* Disable timer1 */ WRITE_MEM32( TC1DATA, 0xffffff00); WRITE_MEM32( TCCNR, ( READ_MEM32(TCCNR) | TC1EN ) | TC1MODE_TIMER );/* Enable timer1 - timer mode */ WRITE_MEM32( TCIR, READ_MEM32(TCIR) & ~TC1IE ); /* Disable timer1 interrupt */ }
static int rtl8196b_pcibios_config_access(unsigned char access_type, unsigned int addr, unsigned int *data) { /* Do 8bit/16bit/32bit access */ if (access_type & PCI_ACCESS_WRITE) { if (access_type & PCI_8BIT_ACCESS) WRITE_MEM8(addr, *data); else if (access_type & PCI_16BIT_ACCESS) WRITE_MEM16(addr, *data); else WRITE_MEM32(addr, *data); } else if (access_type & PCI_ACCESS_READ) { if (access_type & PCI_8BIT_ACCESS) *data = READ_MEM8(addr); else if (access_type & PCI_16BIT_ACCESS) *data = READ_MEM16(addr); else *data = READ_MEM32(addr); } /* If need to check for PCIE access timeout, put code here */ /* ... */ return 0; }
static int rtl8196b_pcibios_config_access(unsigned char access_type, unsigned int addr, unsigned int *data) { /* Do 8bit/16bit/32bit access */ if (access_type & PCI_ACCESS_WRITE) { if (access_type & PCI_8BIT_ACCESS) WRITE_MEM8(addr, *data); else if (access_type & PCI_16BIT_ACCESS) WRITE_MEM16(addr, *data); else WRITE_MEM32(addr, *data); } else if (access_type & PCI_ACCESS_READ) { if (access_type & PCI_8BIT_ACCESS) { #ifdef CONFIG_RTL8198_REVISION_B unsigned int data_temp=0; int swap[4]={0,8,16,24}; int diff = addr&0x3; data_temp=READ_MEM32(addr); *data=(unsigned int)(( data_temp>>swap[diff])&0xff); #else *data = READ_MEM8(addr); #endif } else if (access_type & PCI_16BIT_ACCESS) {
static int rtl8196b_pci_reset(void) { /* If PCI needs to be reset, put code here. * Note: * Software may need to do hot reset for a period of time, say ~100us. * Here we put 2ms. */ #if 1 //Modified for PCIE PHY parameter due to RD center suggestion by Jason 12252009 WRITE_MEM32(0xb8000044, 0x9);//Enable PCIE PLL mdelay(10); //WRITE_MEM32(0xb8000010, 0x00FFFFD6);//Active LX & PCIE Clock in 8196B system register WRITE_MEM32(0xb8000010, READ_MEM32(0xb8000010)|(1<<8)|(1<<9)|(1<<10)); #ifdef PIN_208 WRITE_MEM32(0xb8000010, READ_MEM32(0xb8000010)|(1<<12)); #endif mdelay(10); WRITE_MEM32(0xb800003C, 0x1);//PORT0 PCIE PHY MDIO Reset mdelay(10); WRITE_MEM32(0xb800003C, 0x3);//PORT0 PCIE PHY MDIO Reset mdelay(10); #ifdef PIN_208 WRITE_MEM32(0xb8000040, 0x1);//PORT1 PCIE PHY MDIO Reset mdelay(10); WRITE_MEM32(0xb8000040, 0x3);//PORT1 PCIE PHY MDIO Reset mdelay(10); #endif WRITE_MEM32(0xb8b01008, 0x1);// PCIE PHY Reset Close:Port 0 mdelay(10); WRITE_MEM32(0xb8b01008, 0x81);// PCIE PHY Reset On:Port 0 mdelay(10); #ifdef PIN_208 WRITE_MEM32(0xb8b21008, 0x1);// PCIE PHY Reset Close:Port 1 mdelay(10); WRITE_MEM32(0xb8b21008, 0x81);// PCIE PHY Reset On:Port 1 mdelay(10); #endif #ifdef OUT_CYSTALL WRITE_MEM32(0xb8b01000, 0xcc011901);// PCIE PHY Reset On:Port 0 mdelay(10); #ifdef PIN_208 WRITE_MEM32(0xb8b21000, 0xcc011901);// PCIE PHY Reset On:Port 1 mdelay(10); #endif #endif //WRITE_MEM32(0xb8000010, 0x01FFFFD6);// PCIE PHY Reset On:Port 1 WRITE_MEM32(0xb8000010, READ_MEM32(0xb8000010)|(1<<24)); mdelay(10); #endif WRITE_MEM32(BSP_PCIE0_H_PWRCR, READ_MEM32(BSP_PCIE0_H_PWRCR) & 0xFFFFFF7F); #ifdef PIN_208 WRITE_MEM32(BSP_PCIE1_H_PWRCR, READ_MEM32(BSP_PCIE1_H_PWRCR) & 0xFFFFFF7F); #endif mdelay(100); WRITE_MEM32(BSP_PCIE0_H_PWRCR, READ_MEM32(BSP_PCIE0_H_PWRCR) | 0x00000080); #ifdef PIN_208 WRITE_MEM32(BSP_PCIE1_H_PWRCR, READ_MEM32(BSP_PCIE1_H_PWRCR) | 0x00000080); #endif return 0; }
int PCIE_reset_procedure(int portnum, int Use_External_PCIE_CLK, int mdio_reset) { // dprintf("port=%x, mdio_rst=%x \n", portnum, mdio_reset); int result=0; //first, Turn On PCIE IP #define CLK_MANAGE 0xb8000010 if(portnum==0) REG32(CLK_MANAGE) |= (1<<14); //enable active_pcie0 else if(portnum==1) REG32(CLK_MANAGE) |= (1<<16); //enable active_pcie1 else return result; if (portnum==0) { REG32(CLK_MANAGE) |= (1<<26); //PERST=1 } else if (portnum==1) { REG32(0xb8000040)|=0x300; REG32(PEFGHCNR_REG) &= ~(0x1000); /*port F bit 4 */ REG32(PEFGHDIR_REG) |= (0x1000); /*port F bit 4 */ REG32(PEFGHDAT_REG) |= (0x1000); //PERST=1 } #if defined(CONFIG_RTL_819XD) || defined(CONFIG_RTL_8196E) REG32(CLK_MANAGE) |= (1<<12)| (1<<13)|(1<<18); #endif mdelay(500); #ifdef CONFIG_RTL8198_REVISION_B if(portnum==1) { #define PAD_CONTROL 0xb8000048 REG32(PAD_CONTROL)|=(1<<27); } #endif if(mdio_reset) { if(at2_mode==0) //no auto test, show message printk("Do MDIO_RESET\n"); mdelay(1); // 3.MDIO Reset PCIE_MDIO_Reset(portnum); } /* PCIE_PHY_Reset(portnum); */ mdelay(500); mdelay(500); //---------------------------------------- if(mdio_reset) { //fix 8198 test chip pcie tx problem. #if defined(CONFIG_RTL8198_REVISION_B) || defined(CONFIG_RTL_819XD) || defined(CONFIG_RTL_8196E) if ((REG32(BSP_REVR) >= BSP_RTL8198_REVISION_B) || ((REG32(BSP_REVR)&0xfffff000) == BSP_RTL8197D) || ((REG32(BSP_REVR) & 0xFFFFF000) == BSP_RTL8196E)) { #if 1//def RTL8198_FORMALCHIP_A HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD087); //bokai tell, and fix HostPCIe_SetPhyMdioWrite(portnum, 1, 0x0003); HostPCIe_SetPhyMdioWrite(portnum, 2, 0x4d18); #ifdef CONFIG_PHY_EAT_40MHZ HostPCIe_SetPhyMdioWrite(portnum, 5, 0x0BCB); //40M #endif #ifdef CONFIG_PHY_EAT_40MHZ HostPCIe_SetPhyMdioWrite(portnum, 6, 0xF148); //40M #else HostPCIe_SetPhyMdioWrite(portnum, 6, 0xf848); //25M #endif HostPCIe_SetPhyMdioWrite(portnum, 7, 0x31ff); HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d5); //peisi tune #if 0 //old, HostPCIe_SetPhyMdioWrite(portnum, 9, 0x531c); HostPCIe_SetPhyMdioWrite(portnum, 0xd, 0x1766); //peisi tune #else //saving more power, 8196c pe-si tune HostPCIe_SetPhyMdioWrite(portnum, 0x09, 0x539c); HostPCIe_SetPhyMdioWrite(portnum, 0x0a, 0x20eb); HostPCIe_SetPhyMdioWrite(portnum, 0x0d, 0x1766); #endif #if defined(CONFIG_RTL_819XD) || defined(CONFIG_RTL_8196E) HostPCIe_SetPhyMdioWrite(portnum, 0x0b, 0x0711); //for sloving low performance #else HostPCIe_SetPhyMdioWrite(portnum, 0x0b, 0x0511); //for sloving low performance #endif HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0a00); HostPCIe_SetPhyMdioWrite(portnum, 0x19, 0xFCE0); HostPCIe_SetPhyMdioWrite(portnum, 0x1a, 0x7e4f); //formal chip, reg 0x1a.4=0 HostPCIe_SetPhyMdioWrite(portnum, 0x1b, 0xFC01); //formal chip reg 0x1b.0=1 HostPCIe_SetPhyMdioWrite(portnum, 0x1e, 0xC280); #endif } else #endif { //#define PHY_USE_TEST_CHIP 1 // 1: test chip, 0: fib chip //#define PHY_EAT_40MHZ 0 // 0: 25MHz, 1: 40MHz //HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD187);//ori HostPCIe_SetPhyMdioWrite(portnum, 0, 0xD087); HostPCIe_SetPhyMdioWrite(portnum, 1, 0x0003); //HostPCIe_SetPhyMdioWrite(portnum, 2, 0x4d18); HostPCIe_SetPhyMdioWrite(portnum, 6, 0xf448); //new HostPCIe_SetPhyMdioWrite(portnum, 6, 0x408); //avoid noise infuse //15-12=0, 7-5=0, 0448 HostPCIe_SetPhyMdioWrite(portnum, 7, 0x31ff); HostPCIe_SetPhyMdioWrite(portnum, 8, 0x18d5); //new HostPCIe_SetPhyMdioWrite(portnum, 9, 0x531c); //HostPCIe_SetPhyMdioWrite(portnum, 0xa, 0x00C9); //HostPCIe_SetPhyMdioWrite(portnum, 0xb, 0xe511); //HostPCIe_SetPhyMdioWrite(portnum, 0xc, 0x0820); HostPCIe_SetPhyMdioWrite(portnum, 0xd, 0x1766); HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0010);//ori // HostPCIe_SetPhyMdioWrite(portnum, 0xf, 0x0a00); HostPCIe_SetPhyMdioWrite(portnum, 0x19, 0xFCE0); HostPCIe_SetPhyMdioWrite(portnum, 0x1e, 0xC280); #if 0 //saving more power HostPCIe_SetPhyMdioWrite(0xa, 0xeb); HostPCIe_SetPhyMdioWrite(0x9, 0x538c); // HostPCIe_SetPhyMdioWrite(0xc, 0xC828); //original // HostPCIe_SetPhyMdioWrite(0x0, 0x502F); //fix HostPCIe_SetPhyMdioWrite(0xc, 0x8828); //new HostPCIe_SetPhyMdioWrite(0x0, 0x502F); //fix #endif } } //--------------------------------------- PCIE_Device_PERST(portnum); PCIE_PHY_Reset(portnum); mdelay(500); mdelay(500); result=PCIE_Check_Link(portnum); #if 0 if(portnum==0) { if(result) { WRITE_MEM32(BSP_PCIE0_H_PWRCR, READ_MEM32(BSP_PCIE0_H_PWRCR) & 0xFFFFFF7F); mdelay(100); WRITE_MEM32(BSP_PCIE0_H_PWRCR, READ_MEM32(BSP_PCIE0_H_PWRCR) | 0x00000080); } } else { #ifdef PIN_208 if(result) { WRITE_MEM32(BSP_PCIE1_H_PWRCR, READ_MEM32(BSP_PCIE1_H_PWRCR) & 0xFFFFFF7F); mdelay(100); WRITE_MEM32(BSP_PCIE1_H_PWRCR, READ_MEM32(BSP_PCIE1_H_PWRCR) | 0x00000080); } #endif } #endif return result; }
} else if (access_type & PCI_ACCESS_READ) { if (access_type & PCI_8BIT_ACCESS) { #ifdef CONFIG_RTL8198_REVISION_B unsigned int data_temp=0; int swap[4]={0,8,16,24}; int diff = addr&0x3; data_temp=READ_MEM32(addr); *data=(unsigned int)(( data_temp>>swap[diff])&0xff); #else *data = READ_MEM8(addr); #endif } else if (access_type & PCI_16BIT_ACCESS) { #ifdef CONFIG_RTL8198_REVISION_B unsigned int data_temp=0; int swap[4]={0,8,16,24}; int diff = addr&0x3; data_temp=READ_MEM32(addr); *data=(unsigned int)(( data_temp>>swap[diff])&0xffff); #else *data = READ_MEM16(addr); #endif } else *data = READ_MEM32(addr); } /* If need to check for PCIE access timeout, put code here */ /* ... */ return 0; }