/*!
* ======== InterruptM3_intClear ========
* Clear interrupt and return payload
*/
UInt InterruptM3_intClear()
{
UInt arg = InterruptM3_INVALIDPAYLOAD;
/* First check whether incoming mailbox has a message */
if (Core_getId() == 0) {
/* If FIFO is empty, return InterruptM3_INVALIDPAYLOAD */
if (REG32(MAILBOX_STATUS(SYSM3_MBX)) == 0) {
return (arg);
}
else {
/* If there is a message, return the argument to the caller */
arg = REG32(MAILBOX_MESSAGE(SYSM3_MBX));
REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(SYSM3_MBX);
}
}
else {
/* Clear the inter-M3 interrupt if necessary */
if ((REG16(INTERRUPT_CORE_1) & 0x1) == 0x1) {
REG16(INTERRUPT_CORE_1) &= ~(0x1);
}
/* If FIFO is empty, return InterruptM3_INVALIDPAYLOAD */
if (REG32(MAILBOX_STATUS(APPM3_MBX)) == 0) {
return (arg);
}
else {
/* If there is a message, return the argument to the caller */
arg = REG32(MAILBOX_MESSAGE(APPM3_MBX));
REG32(MAILBOX_IRQSTATUS_CLR_M3) = MAILBOX_REG_VAL(APPM3_MBX);
if (REG32(MAILBOX_STATUS(APPM3_MBX)) != 0) {
/* Trigger our own interrupt since another interrupt pending */
REG16(INTERRUPT_CORE_1) |= 0x1;
}
}
}
return (arg);
}
void platform_init_timer(void)
{
/* GPT2 */
RMWREG32(CM_CLKSEL_PER, 0, 1, 1);
RMWREG32(CM_ICLKEN_PER, 3, 1, 1);
RMWREG32(CM_FCLKEN_PER, 3, 1, 1);
// reset the GP timer
TIMER_REG(TIOCP_CFG) = 0x2;
while ((TIMER_REG(TISTAT) & 1) == 0)
;
// set GPT2-9 clock inputs over to 32k
*REG32(CM_CLKSEL_PER) = 0;
// disable ints
TIMER_REG(TIER) = 0;
TIMER_REG(TISR) = 0x7; // clear any pending bits
// XXX make sure 32K timer is running
register_int_handler(GPT2_IRQ, &os_timer_tick, NULL);
}
static void swNic_dumpPkthdrDescRing(void){
uint32 i, *temp=
(uint32 *)rtlglue_malloc(sizeof(uint32)*totalRxPkthdr);
uint32 value,asicIdx = ((uint32 *)REG32(CPURPDCR))-RxPkthdrRing;
for(i=0;i<totalRxPkthdr;i++)
temp[i]=RxPkthdrRing[i];
rtlglue_printf("Rx phdr ring starts at 0x%x\n",(uint32)RxPkthdrRing );
for(i=0;i<totalRxPkthdr;i++){
struct rtl_pktHdr *ph;
struct rtl_mBuf *m;
value=temp[i];
ph=(struct rtl_pktHdr *)(value &~0x3);
rtlglue_printf("%03d.",(uint16)i);
if(ph){
rtlglue_printf("p:%08x ",value &~0x3);
m=ph->ph_mbuf;
if(m)
rtlglue_printf("m:%08x c:%08x d:%08x", (uint32)m, (uint32)m->m_extbuf, (uint32)m->m_data);
else
rtlglue_printf("No mbuf!! ");
}else
rtlglue_printf("No pkthdr!! ");
rtlglue_printf("%s ", ((value & 1)== 0)?"(CPU)":"(SWC)");
if(asicIdx==i)
rtlglue_printf("ASIC ");
if(rxPhdrIndex==i)
rtlglue_printf("Rx ");
if(lastReclaim==i)
rtlglue_printf("Reclaim ");
if((value & 2)== 2){
rtlglue_printf("WRAP!!\n");
return;
}else
rtlglue_printf("\n");
}
rtlglue_free(temp);
/*!
* ======== InterruptDsp_intSend ========
* Send interrupt to the remote processor
*/
Void InterruptDsp_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo,
UArg arg)
{
UInt key;
/*
* Before writing to a mailbox, check whehter it already contains a message
* If so, then don't write to the mailbox since we want one and only one
* message per interrupt. Disable interrupts between reading
* the MSGSTATUS_X register and writing to the mailbox to protect from
* another thread doing an intSend at the same time
*
* Note regarding possible race condition between local 'intSend' and
* remote 'intClear':
* It is possible that we we read the MAILBOX_MSGSTATUS_X register during
* the remote side's intClear. Therefore, we might choose _not_ to send
* write to the mailbox even though the mailbox is about to be cleared a
* few cycles later. In this case, the interrupt will be lost.
* This is OK, however. intClear should always be called by the Notify
* driver _before_ shared memory is read, so the event will be picked up
* anyway by the previous interrupt that caused intClear to be called.
*/
if (remoteProcId == InterruptDsp_hostProcId) {
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(DSP_TO_HOST)) == 0) {
REG32(MAILBOX_MESSAGE(DSP_TO_HOST)) = arg;
}
Hwi_restore(key);
}
else if (remoteProcId == InterruptDsp_videoProcId) {
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(DSP_TO_VIDEO)) == 0) {
REG32(MAILBOX_MESSAGE(DSP_TO_VIDEO)) = arg;
}
Hwi_restore(key);
}
else { /* VPSS-M3 */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(DSP_TO_VPSS)) == 0) {
REG32(MAILBOX_MESSAGE(DSP_TO_VPSS)) = arg;
}
Hwi_restore(key);
}
}
/* STATIC VARIABLE DECLARATIONS
*/
static HEADER * frhd; /* free list head */
static UINT32 memleft; /* memory left */
void console_init(void)
{
int i;
unsigned long dl;
unsigned long dll;
unsigned long dlm;
REG32( UART_LCR)=0x03000000; //Line Control Register 8,n,1
REG32( UART_FCR)=0xc7000000; //FIFO Ccontrol Register
REG32( UART_IER)=0x00000000;
dl = (200000000 /16)/38400-1;
*(volatile unsigned long *)(0xa1000000) = dl ;
dll = dl & 0xff;
dlm = dl / 0x100;
REG32( UART_LCR)=0x83000000; //Divisor latch access bit=1
REG32( UART_DLL)=dll*0x1000000;
REG32( UART_DLM)=dlm*0x1000000;
REG32( UART_LCR)=0x83000000& 0x7fffffff; //Divisor latch access bit=0
}
/*!
* ======== InterruptDsp_intClear ========
* Clear interrupt
*/
UInt InterruptDsp_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
if (remoteProcId == InterruptDsp_hostProcId) {
arg = REG32(MAILBOX_MESSAGE(HOST_TO_DSP));
REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(HOST_TO_DSP);
}
else if (remoteProcId == InterruptDsp_videoProcId) {
arg = REG32(MAILBOX_MESSAGE(VIDEO_TO_DSP));
REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(VIDEO_TO_DSP);
}
else { /* VPSS-M3 */
arg = REG32(MAILBOX_MESSAGE(VPSS_TO_DSP));
REG32(MAILBOX_IRQSTATUS_CLR_DSP) = MAILBOX_REG_VAL(VPSS_TO_DSP);
}
/* Write to EOI (End Of Interrupt) register */
REG32(MAILBOX_EOI_REG) = 0x1;
return (arg);
}
int dvrmain(void)
{
int r;
unsigned short cpu_id;
char commandline[MAX_COMMANDLINE_LENGTH];
init_printf(NULL, _putc);
init_commands();
printf("\n");
info(0, NULL);
/* check CPU ID */
cpu_id = REG32(RTGALAXY_SB2_CHIP_ID) & 0xffff;
if (cpu_id != RTGALAXY_MARS) {
printf("Wrong CPU ID detected (%04X) - aborting\n", cpu_id);
return -1;
}
for (;;) {
printf("rtdsr> ");
r = get_command(commandline, MAX_COMMANDLINE_LENGTH, -1);
if (r > 0) {
if ((r = parse_command(commandline)) < 0 ) {
if (r == PROGRAM_EXIT) {
return 0;
}
printf("error %d executing command\n", r);
}
}
}
return 0;
}
//void __init bsp_timer_init(void)
void __init plat_time_init(void)
{
unsigned int ocp;
unsigned int cpu_freq_sel;
/* set cp0_compare_irq and cp0_perfcount_irq */
#if 0
cp0_compare_irq = BSP_COMPARE_IRQ; //mark_bb , wana rm !!
cp0_perfcount_irq = BSP_PERFCOUNT_IRQ;
if (cp0_perfcount_irq == cp0_compare_irq)
cp0_perfcount_irq = -1;
#endif
//write_c0_count(0); //mark_bb
// mips_hpt_frequency = BSP_CPU0_FREQ / 2;
cpu_freq_sel=GET_BITVAL(REG32(SYS_HW_STRAP), ST_CPU_FREQ_SEL_OFFSET, RANG4);
ocp=cpu_clksel_table[cpu_freq_sel] * 1000000;
mips_hpt_frequency = ocp / 2;
write_c0_count(0); //need
//mips_clockevent_init(cp0_compare_irq); // mark_bb , no need
//mips_clocksource_init();
}
/**
* ipc_write: ISH -> Host Communication
*
* 1. ISH FW ensures ISH2HOST doorbell busy bit [31] is cleared.
* 2. ISH FW writes data (upto 128 bytes) to ISH2HOST message registers.
* 3. ISH FW writes to ISH2HOST doorbell, busy bit (31) is set.
* 4. Host SW receives interrupt, reads host PISR[0] to realize event.
* 5. Upon reading data, Host driver clears ISH2HOST doorbell busy bit. This
* de-asserts the interrupt.
* 6. ISH FW also receieves an interrupt for the clear event.
*/
static int ipc_write(uint8_t peer_id, void *buff, uint32_t buff_size)
{
struct ipc_if_ctx *ctx;
uint32_t drbl_val = 0;
#ifdef ISH_DEBUG
int i;
#endif
ctx = &ipc_peer_ctxs[peer_id];
if (ipc_wait_until_msg_consumed(ctx, IPC_TIMEOUT)) {
/* timeout */
return IPC_FAILURE;
}
#ifdef ISH_DEBUG
CPRINTF("ipc_write, len=0x%0x [", buff_size);
for (i = 0; i < buff_size; i++)
CPRINTF("0x%0x ", (uint8_t) ((char *)buff)[i]);
CPUTS("]\n");
#endif
/* write message */
if (buff_size <= IPC_MSG_MAX_SIZE) {
/* write to message register */
memcpy((uint32_t *) ctx->out_msg_reg, buff, buff_size);
drbl_val = IPC_BUILD_HEADER(buff_size, IPC_PROTOCOL_ECP,
SET_BUSY);
} else {
return IPC_FAILURE;
}
/* write doorbell */
REG32(ctx->out_drbl_reg) = drbl_val;
return EC_SUCCESS;
}
void
nxc2600_aic_set_dma_mode_rx_packet(struct nxc2600_dma_mode *dma_mode)
{
switch(REG32(NXC2600_AIC_CR2)&NXC2600_AIC_CR2_IASS_MASK)
{
case NXC2600_AIC_CR2_IASS_8_BIT:
dma_mode->mode |= NXC2600_DMA_DCS_TSZ_8_BIT |
NXC2600_DMA_DCS_DP_8_BIT |
NXC2600_DMA_DCS_SP_8_BIT;
break;
case NXC2600_AIC_CR2_IASS_16_BIT:
dma_mode->mode |= NXC2600_DMA_DCS_TSZ_16_BIT |
NXC2600_DMA_DCS_DP_16_BIT |
NXC2600_DMA_DCS_SP_16_BIT;
break;
case NXC2600_AIC_CR2_IASS_18_BIT:
case NXC2600_AIC_CR2_IASS_20_BIT:
dma_mode->mode |= NXC2600_DMA_DCS_TSZ_32_BIT |
NXC2600_DMA_DCS_DP_32_BIT |
NXC2600_DMA_DCS_SP_32_BIT;
break;
}
}
void audio_AGC_DMA_Isr(void)
{
u32 agc_sta = rd_reg(AGC_STA);
//deg_Printf(" %x\n",agc_sta);
if((agc_sta & 0x1) == 0x1)
wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(0));
wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)&(~BIT(5)));
if((g_stcJpegInfo.iAudioFillBufCnt+1) < (g_stcJpegInfo.iAudioFSWriteBufCnt + AUDIO_BUFFER_NUM))
{
if(audio_buffer_ptr == ((u32)JPEG_BUFFER_END_ADDRESS - 0x2000))
audio_buffer_ptr = (u32)JPEG_BUFFER_END_ADDRESS-(AUDIO_BUFFER_NUM*0x2000);
else
audio_buffer_ptr += g_stcJpegInfo.dwAudiobufSize;
g_stcJpegInfo.iAudioFillBufCnt++;
}
else
{
deg_Printf("d");
g_stcJpegInfo.i30FrameCnt -=((192*(u32Framecount+1))/25 -(192*u32Framecount)/25);
u32Framecount++;
if(u32Framecount >= 25)
{
u32Framecount = 0;
}
g_stcJpegInfo.iJpeg10MSCnt -= 25;
}
dmac_channel_disable(AUDIO_ADC_DMA_CH);
//dma_peri2mem_Ext(AUDIO_ADC_DMA_CH, (0<<11)|(6<<7)|(0<<1), (0<<11)|(0<<10), AUADC_DMA_TX_ADR, (audio_buffer_ptr+8), (2048-2));
REG32(DMA_DAR0L + AUDIO_ADC_DMA_CH*0x58) = (u32)(audio_buffer_ptr+8);
dmac_channel_enable(AUDIO_ADC_DMA_CH);
wr_reg(AGC_CFG0,rd_reg(AGC_CFG0)|(BIT(5)));
wr_reg(AGC_CFG_CLR, rd_reg(AGC_CFG_CLR)|BIT(5));
}
/*
* ======== InterruptEve_intPost ========
* Simulate an interrupt from a remote processor
*/
Void InterruptEve_intPost(UInt16 srcProcId, IInterrupt_IntInfo *intInfo,
UArg arg)
{
UInt key;
if (srcProcId == InterruptEve_hostProcId) {
/* disable interrupts */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(HOST_TO_EVE)) == 0) {
/* write the mailbox message to arp32 */
REG32(MAILBOX_MESSAGE(HOST_TO_EVE)) = arg;
}
/* restore interrupts */
Hwi_restore(key);
}
else if ((srcProcId == InterruptEve_videoProcId) ||
(srcProcId == InterruptEve_vpssProcId)) {
/* disable interrupts */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(VIDEO_TO_EVE)) == 0) {
/* write the mailbox message to arp32 */
REG32(MAILBOX_MESSAGE(VIDEO_TO_EVE)) = arg;
}
/* restore interrupts */
Hwi_restore(key);
}
else {
/* disable interrupts */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(DSP_TO_EVE)) == 0) {
/* write the mailbox message to arp32 */
REG32(MAILBOX_MESSAGE(DSP_TO_EVE)) = arg;
}
/* restore interrupts */
Hwi_restore(key);
}
}
/*
* ======== InterruptEve_intSend ========
* Send interrupt to the remote processor
*/
Void InterruptEve_intSend(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo,
UArg arg)
{
UInt key;
if (remoteProcId == InterruptEve_hostProcId) {
/* disable interrupts */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(EVE_TO_HOST)) == 0) {
/* write the mailbox message to host */
REG32(MAILBOX_MESSAGE(EVE_TO_HOST)) = arg;
}
/* restore interrupts */
Hwi_restore(key);
}
else if ((remoteProcId == InterruptEve_videoProcId) ||
(remoteProcId == InterruptEve_vpssProcId)) {
/* disable interrupts */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(EVE_TO_VIDEO)) == 0) {
/* write the mailbox message to video-m3 */
REG32(MAILBOX_MESSAGE(EVE_TO_VIDEO)) = arg;
}
/* restore interrupts */
Hwi_restore(key);
}
else {
/* disable interrupts */
key = Hwi_disable();
if (REG32(MAILBOX_STATUS(EVE_TO_DSP)) == 0) {
/* write the mailbox message to dsp */
REG32(MAILBOX_MESSAGE(EVE_TO_DSP)) = arg;
}
/* restore interrupts */
key = Hwi_disable();
}
}
static void I486OP(cpuid)(void) /* Opcode 0x0F A2 */
{
switch (REG32(EAX))
{
case 0:
{
REG32(EAX) = I.cpuid_max_input_value_eax;
REG32(EBX) = I.cpuid_id0;
REG32(ECX) = I.cpuid_id2;
REG32(EDX) = I.cpuid_id1;
CYCLES(CYCLES_CPUID);
break;
}
case 1:
{
REG32(EAX) = I.cpu_version;
REG32(EDX) = I.feature_flags;
CYCLES(CYCLES_CPUID_EAX1);
break;
}
}
}
/*
* ======== InterruptEve_intClear ========
* Clear interrupt
*/
UInt InterruptEve_intClear(UInt16 remoteProcId, IInterrupt_IntInfo *intInfo)
{
UInt arg;
if (remoteProcId == InterruptEve_hostProcId) { /* HOST */
arg = REG32(MAILBOX_MESSAGE(HOST_TO_EVE));
REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(HOST_TO_EVE);
}
else if ((remoteProcId == InterruptEve_videoProcId) || /* VIDEO-M3 */
(remoteProcId == InterruptEve_vpssProcId)) {
arg = REG32(MAILBOX_MESSAGE(VIDEO_TO_EVE));
REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(VIDEO_TO_EVE);
}
else { /* DSP */
arg = REG32(MAILBOX_MESSAGE(DSP_TO_EVE));
REG32(MAILBOX_IRQSTATUS_CLR_EVE) = MAILBOX_REG_VAL(DSP_TO_EVE);
}
/* Write to EOI (End Of Interrupt) register */
REG32(MAILBOX_EOI_REG) = 0x1;
return (arg);
}
static void unmask_irq(unsigned int irq)
{
#ifdef CONFIG_RTL_EB8186
outl((inl(GIMR0) | (1 << irq)),GIMR0);
inl(GIMR0);
#endif
#ifdef CONFIG_RTL865X
#ifdef CONFIG_RTK_VOIP
if (irq == 6) // PCM
REG32(GIMR) = (REG32(GIMR)) | (1 << (25-irq));
else
#endif
REG32(GIMR) = (REG32(GIMR)) | (1 << (17-irq));
if ( (irq == 0) || (irq == 1) || (irq == 6) )
REG32(IRR2)|= ((irqRoute[irq].idx & 0xF)<<irqRoute[irq].base);
else
REG32(IRR1)|= ((irqRoute[irq].idx & 0xF)<<irqRoute[irq].base);
#endif
}
/* Illegal instruction test */
int illegal_insn_test (void)
{
int ret;
/* Reset except counter */
except_count = 0;
except_mask = 0;
except_pc = 0;
except_ea = 0;
/* Set illegal insn code.
Original code had two bugs. First it jumped to the illegal instruction,
rather than the immediately preceding l.jr r9 (allowing us to
recover). Secondly it used 0xffffffff as an illegal instruction. Except
it isn't - it's l.cust8 0x3ffffff.
Fixed by a) jumping to the correct location and b) really using an
illegal instruction (opcode 0x3a. */
#ifndef __OR1K_NODELAY__
REG32(RAM_START + (RAM_SIZE/2)) = REG32((unsigned long)jump_back + 4);
REG32(RAM_START + (RAM_SIZE/2) + 4) = 0xe8000000;
/* Check if there was illegal insn exception. Note that if an illegal
instruction occurs in a delay slot (like this one), then the exception
PC is the address of the jump instruction. */
#else
REG32(RAM_START + (RAM_SIZE/2)) = 0xe8000000;
REG32(RAM_START + (RAM_SIZE/2) + 4) = REG32((unsigned long)jump_back + 8);
#endif
ret = call (RAM_START + (RAM_SIZE/2), 0 ); /* JPB */
(void) ret; /* suppress unused variable warning */
ASSERT(except_count == 1);
ASSERT(except_mask == (1 << V_ILLINSN));
ASSERT(except_pc == (RAM_START + (RAM_SIZE/2)));
return 0;
}
void dac_init()
{
// Uart_SendByte ('\n');Uart_SendByte ('e');Uart_SendByte ('\n');
REG32(PCON0) &= ~(1<<21); // enable dac clock
REG32(CLKCON0) &= ~(BIT(6)|BIT(7));
REG32(CLKCON1) &= ~(0xf<<8);
REG32(CLKCON1) |= (9<<8);//10 div 240M/(9+1)=24M
obuf_cfg();
REG32(DAC_ACON0) |= BIT(2);
wr_reg(FIFO_CNT, DAC_BLOCK_CNT);//
// wr_reg(OBUF_CLR, 0x02);//clear pending
// dac_analog_init();
#if 0
if(adc_single_double_ch)
{
music_llp0.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (1<<4) | (1<<1);
music_llp1.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (1<<4) | (1<<1);
}
else
{
music_llp0.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (2<<4) | (2<<1);
music_llp1.CTL_L = (1<<28) | (1<<27) | (0 << 25) | (1 << 23) | (1<<20) | (1 << 14) | (0 << 11)| (0<<9) | (2<<7) | (2<<4) | (2<<1);
}
#endif
llp_peri2mem (AUDIO_DAC_DMA_CH, (0<<7)|(7<<11), 0, &adc_dac0);
wr_reg(DACCFG, (rd_reg(DACCFG)& 0xffffff0f) | ((DAC_SAMPLE_32000)<<4) | DAC_EN);
digital_volume_set(0x3fff,1,0);//
REG32(DAC_ACON0) &= ~BIT(2);
deg_Printf("dac_init\r\n");
return;
}
LOCAL BOOLEAN __is_rw_ok(uint32 addr,uint32 val)
{
volatile uint32 i;
BOOLEAN ret = SCI_TRUE;
REG32(addr) = 0;
REG32(addr) = val;
REG32(addr + 4) = 0;
REG32(addr + 4) = (~val);
delay(100);
if ((REG32(addr) == val) && (REG32(addr + 4) == (~val)))
{
ret = SCI_TRUE;
}
else
{
ret = SCI_FALSE;
}
return ret;
}
//#pragma ghs section text=".iram"
__IRAM int32 swNic_intHandler(int32 *param)
{
int32 curDesc=-1;
int32 sched=0;
uint32 cpuiisr,intPending;
spin_lock(rtl865xSpinlock);
while(1){
/* Read the interrupt status register */
cpuiisr=intPending = REG32(CPUIISR);
// filter those intr we don't care. only those intrs with its IIMR bit set would trigger ISR.
intPending &= REG32(CPUIIMR);
//rtlglue_printf("mask:%x, iisr:%x, iimr:%x\n", INTPENDING_NIC_MASK,cpuiisr,REG32(CPUIIMR));
/* Check and handle NIC interrupts */
if (intPending & INTPENDING_NIC_MASK){
REG32(CPUIISR) = intPending;
if(intPending & PKTHDR_DESC_RUNOUT_IP){
REG32(CPUIIMR)&=~PKTHDR_DESC_RUNOUT_IE;
sched=1;
}
if ( intPending &RX_DONE_IP){
REG32(CPUIIMR)&=~RX_DONE_IE;
sched=1;
}
if (sched){
curDesc=(uint32 *)REG32(CPURPDCR)-RxPkthdrRing;
if (intPending & PKTHDR_DESC_RUNOUT_IP){
rxPkthdrRunoutNum++;
rxRunoutIdx=curDesc;
rxPkthdr_runout=1;
}
if(curDesc-1<0)
curDesc=totalRxPkthdr-1;
else
curDesc-=1;
lastIntRxDescIdx=curDesc; //Last pkt of this run. ASIC won't run cross it before we consume this last pkt.
if(intPending & RX_DONE_IP)
rxIntNum++;
}
if ( intPending & (RX_ERR_IP|TX_ERR_IP)){
if ( intPending& TX_ERR_IP)
txPktErrorNum++;
else
rxPktErrorNum++;
}
}
/* Check and handle link change interrupt */
if (intPending & LINK_CHANG_IP)
swNic_linkChgIntHandler();
if ((intPending & (INTPENDING_NIC_MASK|LINK_CHANG_IP)) == 0){
REG32(CPUIISR) = cpuiisr & ~(INTPENDING_NIC_MASK|LINK_CHANG_IP); //clear all uninterested intrs
break;
}
}
spin_unlock(rtl865xSpinlock);
return sched;
}
static inline Void IpcPower_setWugen()
{
REG32(WUGEN_MEVT1) |= WUGEN_INT_MASK;
}
/*
* ======== Core_getId ========
*/
UInt Core_getId()
{
return (REG32(PID0_ADDRESS));
}
__IRAM int32 swNic_write(void * output)
{
struct rtl_pktHdr * pPkt = (struct rtl_pktHdr *) output;
struct rtl_mBuf *pMbuf=pPkt->ph_mbuf;
uint32 len=pPkt->ph_len;
int32 rxDescIdx;
int32 s;
#ifdef NIC_TX_ALIGN
uint16 pLen;
#endif /* NIC_TX_ALIGN */
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfEnterPoint(ROMEPERF_INDEX_12);
#endif
spin_lock_irqsave(rtl865xSpinlock,s);
if(!txEnable){ //Tx is not enabled now
spin_unlock_irqrestore(rtl865xSpinlock,s);
return FAILED;
}
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfExitPoint(ROMEPERF_INDEX_12);
#endif
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfEnterPoint(ROMEPERF_INDEX_13);
#endif
#ifdef CONFIG_RTL865X_MULTILAYER_BSP
rtl8651_txPktPostProcessing(pPkt);
#endif
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfExitPoint(ROMEPERF_INDEX_13);
#endif
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfEnterPoint(ROMEPERF_INDEX_14);
#endif
if(len <60 && mBuf_padding(pMbuf, 60-len, MBUF_DONTWAIT)==NULL)
{
spin_unlock_irqrestore(rtl865xSpinlock,s);
return FAILED;
}
assert(pPkt->ph_len>=60);
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfExitPoint(ROMEPERF_INDEX_14);
#endif
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfEnterPoint(ROMEPERF_INDEX_15);
#endif
#ifdef NIC_TX_ALIGN
pLen = pPkt->ph_len + 4; /* CRC is included */
if (((pLen&0x1c) == 0) && ((pLen&0x03) != 0))
{
assert(pPkt->ph_len == pMbuf->m_len);
pPkt->ph_len = (pPkt->ph_len&0xFFFC) + 0x4; /* let it become 4-byte alignment */
pMbuf->m_len = pPkt->ph_len;
}
#endif /* NIC_TX_ALIGN */
//rtlglue_printf("len[%d] rx[%d] plist[%x] sepn[%d] espl[%x]\n", pPkt->ph_len, pPkt->ph_rxdesc, pPkt->ph_portlist, pPkt->ph_srcExtPortNum, pPkt->ph_extPortList);
pPkt->ph_nextHdr = (struct rtl_pktHdr *) NULL;
rxDescIdx=pPkt->ph_rxdesc;
if(TxPkthdrDescFull){
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfEnterPoint(ROMEPERF_INDEX_16);
#endif
swNic_isrTxRecycle(0);//force reclaim Tx descriptors if any.
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfExitPoint(ROMEPERF_INDEX_16);
#endif
if(TxPkthdrDescFull){//check again, if still full, drop the pkt.
// if((rxDescIdx>=0)&&(rxDescIdx<totalRxPkthdr))
// swNic_isrReclaim(rxDescIdx, pPkt, pMbuf);//pkt was rcvd from network. free it..
spin_unlock_irqrestore(rtl865xSpinlock,s);
return FAILED;
}
}
#ifdef CONFIG_RTL865X_ROMEREAL
rtl8651_romerealRecord( pPkt, 0x00000002 );
#endif/*CONFIG_RTL865X_ROMEREAL*/
//yes, we have a Tx desc fro sending this pkt.
//mark desc as swcore own to send the packet...
//printfByPolling("T%d ,",txFreeIndex);
TxPkthdrRing[txFreeIndex]|=((uint32)pPkt|DESC_OWNED_BIT);
wmb();
txFreeIndex++;
txFreeIndex&=(1<<totalTxPkthdrShift)-1;
spin_unlock_irqrestore(rtl865xSpinlock,s);
//memDump(pMbuf->m_len, 64, "sending...");
//rtlglue_printf("LEN[%d] rx[%d] plist[%x] sepn[%d] espl[%x]\n", pPkt->ph_len, pPkt->ph_rxdesc, pPkt->ph_portlist, pPkt->ph_srcExtPortNum, pPkt->ph_extPortList);
REG32(CPUICR) |= TXFD;
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfExitPoint(ROMEPERF_INDEX_15);
#endif
return SUCCESS;
}
void inline bsp_timer_ack(void)
{
REG32(BSP_TCIR) |= BSP_TC0IP;
}
/* Do basic initialization */
void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec)
{
unsigned long mem_size;
//strcpy(arcs_cmdline, "console=tty0 console=ttyS0,115200");
#ifdef CONFIG_RTK_MTD_ROOT
strcat(arcs_cmdline,"root=/dev/mtdblock1 console=0 single");
#else
strcat(arcs_cmdline,"root=/dev/ram console=0 ramdisk_start=0 single");
#endif
mips_machgroup = MACH_GROUP_PHILIPS;
mips_machtype = MACH_PHILIPS_NINO;
#ifdef CONFIG_RTL_EB8186
#ifdef CONFIG_NINO_4MB
mem_size = 4 << 20;
#elif CONFIG_NINO_8MB
mem_size = 8 << 20;
#elif CONFIG_NINO_16MB
mem_size = 16 << 20;
#elif CONFIG_NINO_32MB
mem_size = 32 << 20;
#endif
#endif
#ifdef CONFIG_RTL865X
unsigned int MCRsdram;
switch ( MCRsdram = ( REG32( MCR ) & 0x1C100010 ) )
{
/* SDRAM 16-bit mode */
case 0x00000000:
mem_size = 2<<20;
break;
case 0x04000000:
mem_size = 4<<20;
break;
case 0x08000000:
mem_size = 8<<20;
break;
case 0x0C000000:
mem_size = 16<<20;
break;
case 0x10000000:
mem_size = 32<<20;
break;
case 0x14000000:
mem_size = 64<<20;
break;
/* SDRAM 16-bit mode - 2 chip select */
case 0x00000010:
mem_size = 4<<20;
break;
case 0x04000010:
mem_size = 8<<20;
break;
case 0x08000010:
mem_size = 16<<20;
break;
case 0x0C000010:
mem_size = 32<<20;
break;
case 0x10000010:
mem_size = 64<<20;
break;
case 0x14000010:
mem_size = 128<<20;
break;
/* SDRAM 32-bit mode */
case 0x00100000:
mem_size = 4<<20;
break;
case 0x04100000:
mem_size = 8<<20;
break;
case 0x08100000:
mem_size = 16<<20;
break;
case 0x0C100000:
mem_size = 32<<20;
break;
case 0x10100000:
mem_size = 64<<20;
break;
case 0x14100000:
mem_size =128<<20;
break;
/* SDRAM 32-bit mode - 2 chip select */
case 0x00100010:
mem_size = 8<<20;
break;
case 0x04100010:
mem_size = 16<<20;
break;
case 0x08100010:
mem_size = 32<<20;
break;
case 0x0C100010:
mem_size = 64<<20;
break;
case 0x10100010:
mem_size =128<<20;
break;
/*
case 0x14100010: mem_size =256<<20; break;
*/
default:
printk( "SDRAM unknown(0x%08X)", MCRsdram );
mem_size = 0;
break;
}
#endif
//mem_size = 16 << 20;
add_memory_region(0, mem_size, BOOT_MEM_RAM);
}
__IRAM static int32 _swNic_recvLoop(int32 last){
volatile struct rtl_pktHdr * pPkthdr; //don't optimize
volatile struct rtl_mBuf * pMbuf; //don't optimize
int32 count=0;
do{
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfEnterPoint(ROMEPERF_INDEX_RECVLOOP);
#endif
/* Increment counter */
if((RxPkthdrRing[rxPhdrIndex]&DESC_OWNED_BIT)==1){
goto out;
}
#ifdef SWNIC_EARLYSTOP
if(nicRxEarlyStop && ((count & nicRxEarlyStop)==nicRxEarlyStop)){//check global interrupt status
uint32 gisrNow = REG32(GISR);
if(gisrNow & 0x65000000){ //Bit 30: USB, Bit 29:PCMCIA, Bit 26: PCI, Bit 24:GPIO
nicRxAbort=1;
goto out;
}
}
#endif
#ifdef CONFIG_RTL865X_CACHED_NETWORK_IO
#if 0
/*Invalidate D-Cache*/
lx4180_writeCacheCtrl(0);
lx4180_writeCacheCtrl(1);
lx4180_writeCacheCtrl(0);
pPkthdr = (struct rtl_pktHdr *) (RxPkthdrRing[rxPhdrIndex] & ~(DESC_OWNED_BIT | DESC_WRAP));
pMbuf = pPkthdr->ph_mbuf;
#else
pPkthdr = (struct rtl_pktHdr *) (RxPkthdrRing[rxPhdrIndex] & ~(DESC_OWNED_BIT | DESC_WRAP));
pMbuf = pPkthdr->ph_mbuf;
//force update d-cache if hit.
src32=(uint32 *)UNCACHE(pPkthdr);
dst32=(uint32 *)CACHED(pPkthdr);
dst32[0]=src32[0];
dst32[1]=src32[1];
dst32[2]=src32[2];
dst32[3]=src32[3];
src32=(uint32 *)UNCACHE(pMbuf);
dst32=(uint32 *)CACHED(pMbuf);
dst32[0]=src32[0];
dst32[1]=src32[1];
dst32[2]=src32[2];
dst32[3]=src32[3];
//pkt from ASIC, convert to uncached data pointer for used in
//fwd engine
pMbuf->m_data=UNCACHE(pMbuf->m_data);
pMbuf->m_extbuf=UNCACHE(pMbuf->m_extbuf);
#endif
#else
pPkthdr = (struct rtl_pktHdr *) (RxPkthdrRing[rxPhdrIndex] & ~(DESC_OWNED_BIT | DESC_WRAP));
pMbuf = pPkthdr->ph_mbuf;
#endif //CONFIG_RTL865X_CACHED_NETWORK_IO
#ifdef CONFIG_RTL865XB_EXP_PERFORMANCE_EVALUATION
if(_pernicStart == TRUE){
static uint32 start, end;
if(!_pernicPktCount){
startCOP3Counters(_pernicInst);
start = jiffies;
}
else if(_pernicPktCount == _pernicPktLimit){
end = jiffies;
stopCOP3Counters();
printk("%d pkts. Total %d bytes, %d ms. %u KBps\n", _pernicPktCount, _pernicByteCount, (uint32)((end-start)*10), (uint32)(_pernicByteCount/((end-start)*10)));
_pernicStart = FALSE;
}
_pernicPktCount++;
_pernicByteCount += pPkthdr->ph_len + 4;
swNic_isrReclaim(rxPhdrIndex, pPkthdr, pMbuf);
/* Increment index */
if ( ++rxPhdrIndex == totalRxPkthdr )
rxPhdrIndex = 0;
if ( ++rxMbufIndex == totalRxMbuf )
rxMbufIndex = 0;
continue;
}
#endif
assert(pPkthdr->ph_len>0);
if((pPkthdr->ph_flags&PKTHDR_DRIVERHOLD)==0){
//exception handling
swNic_rxRunoutTxPending((struct rtl_pktHdr *)pPkthdr);
goto out;
}
count++;
//SETBITS(pPkthdr->ph_flags, PKT_INCOMING); //packet from physical port
pPkthdr->ph_rxdesc=rxPhdrIndex;
pPkthdr->ph_flags&=~PKTHDR_DRIVERHOLD;
//Transform extension port numbers to continuous number for fwd engine.
#ifdef CONFIG_RTL865X_MULTILAYER_BSP //Default run this except L2 BSP.
//must call this API after rxPhdrIndex is assigned...
if(rtl8651_rxPktPreprocess(pPkthdr)){
rtlglue_printf("Drop rxDesc=%d\n",rxPhdrIndex );
//memDump(pPkthdr->ph_mbuf->m_data, pPkthdr->ph_len,"Loopback Pkt");
swNic_isrReclaim(rxPhdrIndex, pPkthdr, pMbuf);
}else
#endif
{
#ifdef CONFIG_RTL865X_ROMEREAL
rtl8651_romerealRecord( pPkthdr, 0x00000001 );
#endif/*CONFIG_RTL865X_ROMEREAL*/
/* Invoked installed function pointer to handle packet */
(*installedProcessInputPacket)((struct rtl_pktHdr*)pPkthdr);
}
#ifdef SWNIC_DEBUG
assert(rxPhdrIndex==rxMbufIndex);
#endif
/* Increment index */
if ( ++rxPhdrIndex == totalRxPkthdr )
rxPhdrIndex = 0;
if ( ++rxMbufIndex == totalRxMbuf )
rxMbufIndex = 0;
}while(last>=0&&rxPhdrIndex!=last);
out:
return count;
}
__IRAM void swNic_rxThread(unsigned long param)
{
int32 rxDescIdx=lastIntRxDescIdx;
int32 latestIdx;
int32 s;
spin_lock_irqsave(rtl865xSpinlock,s);
#if EVENT_TRIGGER_TIMEUPDATE > 0
rtl8651_timeUpdate(0); //cfliu: check once per interrupt, not per pkt.
#endif
next_round:
#ifdef CONFIG_RTL865X_ROMEPERF
rtl8651_romeperfExitPoint(ROMEPERF_INDEX_UNTIL_RXTHREAD);/* start at irq.c:irq_dispatch() */
#endif
#ifdef SWNIC_EARLYSTOP
nicRxAbort=0;
#endif
if(rxPhdrIndex!=rxDescIdx){
rxPktCounter+=_swNic_recvLoop(rxDescIdx);
}
if(rxPhdrIndex!=rxDescIdx){
#ifdef SWNIC_EARLYSTOP
if(!nicRxAbort)
#endif
{
REG32(CPUIIMR)|= RX_DONE_IE;
goto out; //abort in _swNic_recvLoop().
}
}
//Last one to recv, but see if we can receive again first
latestIdx=(uint32 *)REG32(CPURPDCR)-RxPkthdrRing;
if(latestIdx-1<0)
latestIdx = totalRxPkthdr-1;
else
latestIdx-=1;
//Did ASIC recv more pkt since we last see it?
if(rxDescIdx!=latestIdx){
#ifdef SWNIC_EARLYSTOP
if(!nicRxAbort)
#endif
{
//yes, keep intr closed. we still have more job to do.
rxDescIdx=latestIdx;
goto next_round;
}
}else{
//No, this is the last to recv.
REG32(CPUIIMR)|= RX_DONE_IE; //enable intr before we recv last pkt, in case intr lost.
rxPktCounter+=_swNic_recvLoop(-1);//just recv one pkt.
}
//No more pkts in this run.
out:
if(rxPkthdr_runout==0 &&(REG32(CPUIISR) & PKTHDR_DESC_RUNOUT_IP)){
rxRunoutIdx=(uint32 *)REG32(CPURPDCR)-RxPkthdrRing;
rxPkthdr_runout=1;
rxPkthdrRunoutNum++;
}
if(rxPkthdr_runout==1){
if(txEnable)
swNic_isrTxRecycle(1);
if(rxRunoutIdx<0)
rxPkthdr_runout=0;
REG32(CPUIIMR)|=PKTHDR_DESC_RUNOUT_IE;
}
spin_unlock_irqrestore(rtl865xSpinlock,s);
}
void PCIE_reset_procedure(int PCIE_Port0and1_8196B_208pin, int Use_External_PCIE_CLK, int mdio_reset)
{
#define SYS_PCIE_PHY0 (0xb8000000 +0x50)
//PCIE Register
#define CLK_MANAGE 0xb8000010
#define PCIE_PHY0_REG 0xb8b01000
//#define PCIE_PHY1_REG 0xb8b21000
#define PCIE_PHY0 0xb8b01008
// #define PCIE_PHY1 0xb8b21008
//JSW:PCIE reset procedure
#if 0
//1. "Enable internal PCIE PLL
//#if Use_External_PCIE_CLK
if(Use_External_PCIE_CLK)
REG32(PIE_PLL) = 0x358; //Use External PCIE CLK (clock chip)
//#else
else
REG32(PCIE_PLL) = 0x9; //Use Internal PCIE CLK and PCIE fine-tune
//#endif
//prom_printf("\nPCIE_PLL(0x%x)=0x%x\n",PCIE_PLL,READ_MEM32(PCIE_PLL));
mdelay(100);//mdelay(10);
#endif
//2.Active LX & PCIE Clock
REG32(CLK_MANAGE) |= (1<<11); //enable active_pcie0
mdelay(100);
#if 1
if(mdio_reset)
{
printk("Do MDIO_RESET\n");
// 3.MDIO Reset
REG32(SYS_PCIE_PHY0) = (1<<3) |(0<<1) | (0<<0); //mdio reset=0,
REG32(SYS_PCIE_PHY0) = (1<<3) |(0<<1) | (1<<0); //mdio reset=1,
REG32(SYS_PCIE_PHY0) = (1<<3) |(1<<1) | (1<<0); //bit1 load_done=1
}
//4. PCIE PHY Reset
REG32(PCIE_PHY0) = 0x1; //bit7 PHY reset=0 bit0 Enable LTSSM=1
REG32(PCIE_PHY0) = 0x81; //bit7 PHY reset=1 bit0 Enable LTSSM=1
mdelay(100);
#endif
mdelay(100);
#if 0
//#if Use_External_PCIE_CLK
if(Use_External_PCIE_CLK)
{
//5. PCIE P0 PHY external clock
mdelay(100);
REG32(PCIE_PHY0_REG) = 0xC3930301; //bit[3] must be "0" for external clock
//REG32(PCIE_PHY0_REG) = 0xC39B0301; //20090304:RDC for for PCIE port 0 Refine-tune
mdelay(100);
REG32(PCIE_PHY0_REG) = 0x3c011901; //close PHY 0 ,"0"=R,"1"=W
mdelay(100);
}
//#endif
#endif
//----------------------------------------
if(mdio_reset)
{
//fix 8196C test chip pcie tx problem.
/*
HostPCIe_SetPhyMdioWrite( 8, HostPCIe_SetPhyMdioRead(8) | (1<<3) );
HostPCIe_SetPhyMdioWrite(0x0d, HostPCIe_SetPhyMdioRead(0x0d) | (5<<5) );
HostPCIe_SetPhyMdioWrite(0x0d, HostPCIe_SetPhyMdioRead(0x0d) | (1<<4) );
HostPCIe_SetPhyMdioWrite(0x0f, HostPCIe_SetPhyMdioRead(0x0f) & ~(1<<4));
HostPCIe_SetPhyMdioWrite(0x06, HostPCIe_SetPhyMdioRead(0x06) | (1<<11) );
*/
HostPCIe_SetPhyMdioWrite(0, 0x5027);
HostPCIe_SetPhyMdioWrite(2, 0x6d18);
HostPCIe_SetPhyMdioWrite(6, 0x8828);
HostPCIe_SetPhyMdioWrite(7, 0x30ff);
HostPCIe_SetPhyMdioWrite(8, 0x18d7);
HostPCIe_SetPhyMdioWrite(0xa, 0xe9);
HostPCIe_SetPhyMdioWrite(0xb, 0x0511);
HostPCIe_SetPhyMdioWrite(0xd, 0x15b6);
HostPCIe_SetPhyMdioWrite(0xf, 0x0f0f);
#if 1 // PHY_EAT_40MHZ
HostPCIe_SetPhyMdioWrite(5, 0xbcb); //[9:3]=1111001 (binary) 121 (10)
HostPCIe_SetPhyMdioWrite(6, 0x8128); //[11]=0 [9:8]=01
#endif
/*
emdiow 0 5027
emdiow 2 6d18
emdiow 6 8828
emdiow 7 30ff
emdiow 8 18dd
emdiow a e9
emdiow b 0511
emdiow d 15b6
emdiow f 0f0f
*/
}
//---------------------------------------
// 6. PCIE Device Reset
REG32(CLK_MANAGE) &= ~(1<<12); //perst=0 off.
mdelay(100);
mdelay(100);
mdelay(100);
REG32(CLK_MANAGE) |= (1<<12); //PERST=1
//prom_printf("\nCLK_MANAGE(0x%x)=0x%x\n\n",CLK_MANAGE,READ_MEM32(CLK_MANAGE));
//4. PCIE PHY Reset
REG32(PCIE_PHY0) = 0x1; //bit7 PHY reset=0 bit0 Enable LTSSM=1
REG32(PCIE_PHY0) = 0x81; //bit7 PHY reset=1 bit0 Enable LTSSM=1
mdelay(100);
mdelay(1000);
#if 1 //wait for LinkUP
int i=100;
while(--i)
{
if( (REG32(0xb8b00728)&0x1f)==0x11)
break;
mdelay(100);
}
if(i==0)
printk("i=%x Cannot LinkUP \n",i);
#endif
printk("devid=%x\n",REG32(0xb8b10000));
}
int32 swNic_setup(uint32 pkthdrs, uint32 mbufs, uint32 txpkthdrs)
{
struct rtl_pktHdr *freePkthdrListHead,*freePkthdrListTail;
struct rtl_mBuf *freeMbufListHead, *freeMbufListTail;
int i;
/* Disable Rx & Tx ,bus burst size, etc */
swNic_txRxSwitch(0,0);
#ifdef SWNIC_EARLYSTOP
nicRxEarlyStop=0;
#endif
/* Initialize index of Tx pkthdr descriptor */
txDoneIndex = 0;
txFreeIndex = 0;
/* Allocate rx pkthdrs */
if(pkthdrs!=mBuf_driverGetPkthdr(pkthdrs, &freePkthdrListHead, &freePkthdrListTail)){
rtlglue_printf("Can't allocate all pkthdrs\n");
return EINVAL;
}
assert(freePkthdrListHead);
assert(freePkthdrListTail);
/* Allocate rx mbufs and clusters */
if(mbufs!=mBuf_driverGet(mbufs, &freeMbufListHead, &freeMbufListTail)){
rtlglue_printf("Can't allocate all mbuf/clusters\n");
return EINVAL;
}
assert(freeMbufListHead);
assert(freeMbufListTail);
/////////////////////////////////////////////////
/* Initialize Tx packet header descriptors */
for (i=0; i<txpkthdrs; i++)
TxPkthdrRing[i] = DESC_RISC_OWNED;
/* Set wrap bit of the last descriptor */
TxPkthdrRing[txpkthdrs - 1] |= DESC_WRAP;
/* Fill Tx packet header FDP */
REG32(CPUTPDCR) = (uint32) TxPkthdrRing;
/////////////////////////////////////////////////
/* Initialize index of current Rx pkthdr descriptor */
rxPhdrIndex = 0;
/* Initialize Rx packet header descriptors */
for (i=0; i<pkthdrs; i++)
{
assert( freePkthdrListHead );
RxPkthdrRing[i] = (uint32) freePkthdrListHead | DESC_SWCORE_OWNED;
if ( (freePkthdrListHead = freePkthdrListHead->ph_nextHdr) == NULL )
freePkthdrListTail = NULL;
}
/* Set wrap bit of the last descriptor */
RxPkthdrRing[pkthdrs - 1] |= DESC_WRAP;
/* Fill Rx packet header FDP */
REG32(CPURPDCR) = (uint32) RxPkthdrRing;
/////////////////////////////////////////////////
/* Initialize index of current Rx pkthdr descriptor */
rxMbufIndex = 0;
/* Initialize Rx mbuf descriptors */
for (i=0; i<mbufs; i++)
{
assert( freeMbufListHead );
RxMbufRing[i] = (uint32) freeMbufListHead | DESC_SWCORE_OWNED;
#ifndef CONFIG_RTL865X_CACHED_NETWORK_IO
freeMbufListHead->m_extbuf=(uint8 *)UNCACHE(freeMbufListHead->m_extbuf);
freeMbufListHead->m_data=(uint8 *)UNCACHE(freeMbufListHead->m_data);
#endif
#if defined(CONFIG_RTL865X_MBUF_HEADROOM)&&defined(CONFIG_RTL865X_MULTILAYER_BSP)
if(mBuf_reserve(freeMbufListHead, CONFIG_RTL865X_MBUF_HEADROOM))
rtlglue_printf("Failed when init Rx %d\n", i);
#endif
if ( (freeMbufListHead = freeMbufListHead->m_next) == NULL )
freeMbufListTail = NULL;
}
/* Set wrap bit of the last descriptor */
RxMbufRing[mbufs - 1] |= DESC_WRAP;
/* Fill Rx mbuf FDP */
REG32(CPURMDCR) = (uint32) RxMbufRing;
REG32(CPUICR) =0;
#ifdef CONFIG_RTL865XB
{
char chipVersion[16];
uint32 align=0;
REG32(CPUICR)|=EXCLUDE_CRC;
GetChipVersion(chipVersion, sizeof(chipVersion), NULL);
if(chipVersion[strlen(chipVersion)-1]=='B')
{
//865xB chips support free Rx align from 0~256 bytes
#ifdef SWNIC_RX_ALIGNED_IPHDR
align+=2;
#endif
REG32(CPUICR)|=align;
rtlglue_printf("Rx shift=%x\n",REG32(CPUICR));
}
}
#endif
/* Enable Rx & Tx. Config bus burst size and mbuf size. */
REG32(CPUICR) |= BUSBURST_32WORDS | MBUF_2048BYTES;
REG32(CPUIIMR) |= LINK_CHANG_IE;
swNic_txRxSwitch(1,1);
return SUCCESS;
}
void HostPCIe_SetPhyMdioWrite(unsigned int regaddr, unsigned short val)
{
REG32(PCIE0_MDIO)= ( (regaddr&0x1f)<<PCIE_MDIO_REG_OFFSET) | ((val&0xffff)<<PCIE_MDIO_DATA_OFFSET) | (1<<PCIE_MDIO_RDWR_OFFSET) ;
//delay
mdelay(1);//mdelay(10);
}
