static void lpe_enable_acpi_mode(device_t dev)
{
static const struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR32(PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1,
LPE_PCICFGCTR1_PCI_CFG_DIS |
LPE_PCICFGCTR1_ACPI_INT_EN),
REG_SCRIPT_END
};
global_nvs_t *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
printk(BIOS_ERR, "Unable to locate Global NVS\n");
return;
}
/* Save BAR0, BAR1, and firmware base to ACPI NVS */
assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);
assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
/* Device is enabled in ACPI mode */
gnvs->dev.lpe_en = 1;
/* Put device in ACPI mode */
reg_script_run_on_dev(dev, ops);
}
void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR32(PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg,
SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN),
REG_SCRIPT_END
};
struct resource *bar;
global_nvs_t *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
printk(BIOS_ERR, "Unable to locate Global NVS\n");
return;
}
/* Save BAR0 and BAR1 to ACPI NVS */
bar = find_resource(dev, PCI_BASE_ADDRESS_0);
if (bar)
gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base;
bar = find_resource(dev, PCI_BASE_ADDRESS_1);
if (bar)
gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base;
/* Device is enabled in ACPI mode */
gnvs->dev.scc_en[nvs_index] = 1;
/* Put device in ACPI mode */
reg_script_run_on_dev(dev, ops);
}
/* Aggressive Clock Gating */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0),
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0),
/* Enable Gfx Turbo. */
REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG,
~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0),
REG_SCRIPT_END
};
static const struct reg_script gpu_pre_vbios_script[] = {
/* Make sure GFX is bus master with MMIO access */
REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
/* Display */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0,
GFX_TIMEOUT),
/* Tx/Rx Lanes */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0),
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0,
GFX_TIMEOUT),
/* Common Lane */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0),
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0,
GFX_TIMEOUT),
/* Ungating Tx only */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0),
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0,
#include <vendorcode/google/chromeos/vbnv_layout.h>
#endif
static const struct reg_script pch_pmc_misc_init_script[] = {
/* SLP_S4=4s, SLP_S3=50ms, disable SLP_X stretching after SUS loss. */
REG_PCI_RMW16(GEN_PMCON_B,
~(S4MAW_MASK | SLP_S3_MIN_ASST_WDTH_MASK),
S4MAW_4S | SLP_S3_MIN_ASST_WDTH_50MS |
DIS_SLP_X_STRCH_SUS_UP),
/* Enable SCI and clear SLP requests. */
REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
REG_SCRIPT_END
};
static const struct reg_script pmc_write1_to_clear_script[] = {
REG_PCI_OR32(GEN_PMCON_A, 0),
REG_PCI_OR32(GEN_PMCON_B, 0),
REG_PCI_OR32(GEN_PMCON_B, 0),
REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0),
REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0),
REG_SCRIPT_END
};
static void pch_pmc_add_mmio_resources(device_t dev)
{
struct resource *res;
/* Memory-mmapped I/O registers. */
res = new_resource(dev, PWRMBASE);
res->base = PCH_PWRM_BASE_ADDRESS;
res->size = PCH_PWRM_BASE_SIZE;
#include <baytrail/iomap.h>
#include <baytrail/iosf.h>
#include <baytrail/pci_devs.h>
#include <baytrail/pmc.h>
#include <baytrail/ramstage.h>
#include <baytrail/ehci.h>
#include "chip.h"
static const struct reg_script ehci_init_script[] = {
/* Enable S0 PLL shutdown
* D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */
REG_PCI_OR16(0x7a, 0x14de),
/* Enable SB local clock gating
* D29:F0:7C[14,3,2]=111b (14 set in clock gating step) */
REG_PCI_OR32(0x7c, 0x0000000c),
REG_PCI_OR32(0x8c, 0x00000001),
/* Enable dynamic clock gating 0x4001=0xCE */
REG_IOSF_RMW(IOSF_PORT_USBPHY, 0x4001, 0xFFFFFF00, 0xCE),
/* Magic RCBA register set sequence */
/* RCBA + 0x200=0x1 */
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x200, 0x00000001),
/* RCBA + 0x204=0x2 */
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x204, 0x00000002),
/* RCBA + 0x208=0x0 */
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x208, 0x00000000),
/* RCBA + 0x240[4,3,2,1,0]=00000b */
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x240, ~0x0000001f, 0),
/* RCBA + 0x318[9,8,6,5,4,3,2,1,0]=000000111b */
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x318, ~0x00000378, 0x00000007),
/* RCBA + 0x31c[3,2,1,0]=0011b */
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <reg_script.h>
#include <soc/iosf.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include "chip.h"
static const struct reg_script emmc_ops[] = {
/* Enable 2ms card stable feature. */
REG_PCI_OR32(0xa8, (1 << 24)),
/* Enable HS200 */
REG_PCI_WRITE32(0xa0, 0x446cc801),
REG_PCI_WRITE32(0xa4, 0x80000807),
/* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */
REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)),
/* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */
REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)),
/* Set slew for HS200 */
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c),
REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c),
/* Max timeout */
REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e),
REG_SCRIPT_END,
};
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <reg_script.h>
#include <soc/intel/common/hda_verb.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
static const struct reg_script init_ops[] = {
/* Enable no snoop traffic. */
REG_PCI_OR16(0x78, 1 << 11),
/* Configure HDMI codec connection. */
REG_PCI_OR32(0xc4, 1 << 1),
REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00),
/* Configure internal settings. */
REG_PCI_OR32(0xc0, 0x7 << 21),
REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)),
REG_PCI_WRITE32(0xc8, 0x82a30000),
REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0),
/* Disable docking. */
REG_PCI_RMW8(0x4d, ~(1 << 7), 0),
REG_SCRIPT_END,
};
static const uint32_t hdmi_codec_verb_table[] = {
/* coreboot specific header */
#include <console/console.h>
#include <console/post_codes.h>
#include <cpu/x86/smm.h>
#include <reg_script.h>
#include <spi-generic.h>
#include <stdlib.h>
#include <soc/pci_devs.h>
#include <soc/lpc.h>
#include <soc/me.h>
#include <soc/rcba.h>
#include <soc/spi.h>
#include <soc/systemagent.h>
const struct reg_script system_agent_finalize_script[] = {
REG_PCI_OR16(0x50, 1 << 0), /* GGC */
REG_PCI_OR32(0x5c, 1 << 0), /* DPR */
REG_PCI_OR32(0x78, 1 << 10), /* ME */
REG_PCI_OR32(0x90, 1 << 0), /* REMAPBASE */
REG_PCI_OR32(0x98, 1 << 0), /* REMAPLIMIT */
REG_PCI_OR32(0xa0, 1 << 0), /* TOM */
REG_PCI_OR32(0xa8, 1 << 0), /* TOUUD */
REG_PCI_OR32(0xb0, 1 << 0), /* BDSM */
REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */
REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */
REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31),
REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31),
/* Set the mixer load resistance */
REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0,
OCFGPIMIXLOAD_1_0_MASK),
REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1,
OCFGPIMIXLOAD_1_0_MASK),
REG_SCRIPT_END
};
static const struct reg_script pcie_bus_init_script[] = {
/* Setup Message Bus Idle Counter (SBIC) values */
REG_PCI_RMW8(R_QNC_PCIE_IOSFSBCTL, ~B_QNC_PCIE_IOSFSBCTL_SBIC_MASK,
V_PCIE_ROOT_PORT_SBIC_VALUE),
REG_PCI_READ8(R_QNC_PCIE_IOSFSBCTL),
/* Set the IPF bit in MCR2 */
REG_PCI_OR32(R_QNC_PCIE_MPC2, B_QNC_PCIE_MPC2_IPF),
REG_PCI_READ32(R_QNC_PCIE_MPC2),
/* Set up the Posted and Non Posted Request sizes for PCIe */
REG_PCI_RMW32(R_QNC_PCIE_CCFG, ~B_QNC_PCIE_CCFG_UPSD,
(B_QNC_PCIE_CCFG_UNRS | B_QNC_PCIE_CCFG_UPRS)),
REG_PCI_READ32(R_QNC_PCIE_CCFG),
REG_SCRIPT_END
};
void pcie_init(void)
{
/* Initialize the PCIe bridges */
reg_script_run(pcie_init_script);
reg_script_run_on_dev(PCIE_PORT0_BDF, pcie_bus_init_script);
reg_script_run_on_dev(PCIE_PORT1_BDF, pcie_bus_init_script);
