static int lge_isa1200_clock(int enable)
{
if (enable) {
REG_WRITEL(
((( 0 & 0xffU) <<16U) + /* N_VAL[23:16] */
(1U<<11U) + /* CLK_ROOT_ENA[11] : Enable(1) */
(0U<<10U) + /* CLK_INV[10] : Disable(0) */
(1U<<9U) + /* CLK_BRANCH_ENA[9] : Enable(1) */
(0U<<8U) + /* NMCNTR_EN[8] : Enable(1) */
(0U<<7U) + /* MNCNTR_RST[7] : Not Active(0) */
(0U<<5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */
(0U<<3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */
(0U<<0U)), /* SRC_SEL[2:0] : pxo (0) */
GP1_NS_REG);
//printk("GPIO_LIN_MOTOR_PWM is enabled. pxo clock.");
} else {
REG_WRITEL(
((( 0 & 0xffU) <<16U) + /* N_VAL[23:16] */
(0U<<11U) + /* CLK_ROOT_ENA[11] : Disable(0) */
(0U<<10U) + /* CLK_INV[10] : Disable(0) */
(0U<<9U) + /* CLK_BRANCH_ENA[9] : Disable(0) */
(0U<<8U) + /* NMCNTR_EN[8] : Disable(0) */
(1U<<7U) + /* MNCNTR_RST[7] : Not Active(0) */
(0U<<5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */
(0U<<3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */
(0U<<0U)), /* SRC_SEL[2:0] : pxo (0) */
GP1_NS_REG);
//printk("GPIO_LIN_MOTOR_PWM is disabled.");
}
return 0;
}
static int android_irrc_set_pwm(int enable,int PWM_CLK, int duty)
{
int M_VAL = 1;
int N_VAL = 1;
int D_VAL = 1;
N_VAL = (9600+PWM_CLK)/(PWM_CLK*2); //Formular in case SRC is 19.2Mhz. N_VAL = SRC/(div*PWM_CLK) + 0.5
D_VAL = (N_VAL*duty+50)/100;
if (D_VAL == 0)
D_VAL = 1;
INFO_MSG("enable:%d, pwm_clk:%d, duty:%d, M:%d,N:%d,D:%d\n", enable,PWM_CLK,duty, M_VAL,N_VAL,D_VAL);
if (enable) {
REG_WRITEL(
((~(N_VAL-M_VAL)) & 0xffU), /* N[7:0] */
MMSS_GP0_CMD_RCGR(0x0C));
REG_WRITEL(
((~(D_VAL << 1)) & 0xffU), /* D[7:0] */
MMSS_GP0_CMD_RCGR(0x10));
REG_WRITEL(
(1 << 1U) + /* ROOT_EN[1] */
(1), /* UPDATE[0] */
MMSS_GP0_CMD_RCGR(0));
} else {
REG_WRITEL(
(0 << 1U) + /* ROOT_EN[1] */
(0), /* UPDATE[0] */
MMSS_GP0_CMD_RCGR(0));
}
return 0;
}
int alessi_vibrator_ic_enable_set(int enable)
{
if(enable) {
REG_WRITEL((GPMN_M_DEFAULT & GPMN_M_MASK), GP_MN_CLK_MDIV);
REG_WRITEL((~(GPMN_N_DEFAULT - GPMN_M_DEFAULT) & GPMN_N_MASK), GP_MN_CLK_NDIV);
gpio_direction_output(GPIO_LIN_MOTOR_EN, 1);
} else {
gpio_direction_output(GPIO_LIN_MOTOR_EN, 0);
}
return 0;
}
static int vibrator_pwm_set(int enable, int amp, int n_value)
{
uint M_VAL = GP_CLK_M_DEFAULT;
uint D_VAL = 0;
uint D_INV = 0;
uint clk_id = gp_clk_id;
pr_debug("%s: amp=%d, n_value=%d\n", __func__, amp, n_value);
if (enable) {
if (amp)
D_VAL = vibrator_adjust_amp(amp) + GP_CLK_D_HALF;
if (D_VAL > GP_CLK_D_HALF) {
D_VAL = GP_CLK_D_MAX - D_VAL;
D_INV = 1;
}
REG_WRITEL(
(((M_VAL & 0xffU) << 16U) + /* M_VAL[23:16] */
((~(D_VAL << 1)) & 0xffU)), /* D_VAL[7:0] */
GPn_MD_REG(clk_id));
REG_WRITEL(
((((~(n_value-M_VAL)) & 0xffU) << 16U) + /* N_VAL[23:16] */
(1U << 11U) + /* CLK_ROOT_ENA[11] : Enable(1) */
((D_INV & 0x01U) << 10U) + /* CLK_INV[10] : Disable(0) */
(1U << 9U) + /* CLK_BRANCH_ENA[9] : Enable(1) */
(1U << 8U) + /* NMCNTR_EN[8] : Enable(1) */
(0U << 7U) + /* MNCNTR_RST[7] : Not Active(0) */
(2U << 5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */
(3U << 3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */
(5U << 0U)), /* SRC_SEL[2:0] : CXO (5) */
GPn_NS_REG(clk_id));
pr_debug("%s: PWM is enable with M=%d N=%d D=%d\n",
__func__,
M_VAL, n_value, D_VAL);
} else {
REG_WRITEL(
((((~(n_value-M_VAL)) & 0xffU) << 16U) + /* N_VAL[23:16] */
(0U << 11U) + /* CLK_ROOT_ENA[11] : Disable(0) */
(0U << 10U) + /* CLK_INV[10] : Disable(0) */
(0U << 9U) + /* CLK_BRANCH_ENA[9] : Disable(0) */
(0U << 8U) + /* NMCNTR_EN[8] : Disable(0) */
(0U << 7U) + /* MNCNTR_RST[7] : Not Active(0) */
(2U << 5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */
(3U << 3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */
(5U << 0U)), /* SRC_SEL[2:0] : CXO (5) */
GPn_NS_REG(clk_id));
pr_debug("%s: PWM is disable\n", __func__);
}
return 0;
}
int bryce_vibrator_pwn_set(int enable, int amp)
{
// printk("[vibrator] %s is called \n", __func__);
int gain = ((PWM_MAX_HALF_DUTY*amp) >> 7)+ GPMN_D_DEFAULT;
REG_WRITEL((GPMN_M_DEFAULT & GPMN_M_MASK), GP_MN_CLK_MDIV_REG);
REG_WRITEL((~( GPMN_N_DEFAULT - GPMN_M_DEFAULT )&GPMN_N_MASK), GP_MN_CLK_NDIV_REG);
// printk("[vibrator] gain : %d, enable : %d \n", gain, enable);
/* [email protected] 2010.09.06 S
add to avoid warning mesg in gpiolib
*/
gpio_request(GPIO_LIN_MOTOR_PWM, "lin_motor_pwn");
/* [email protected] 2010.09.17 start
* changed function number 0 -> 2, Function 2 is for PWM.
*/
// BEGIN : [email protected] 2011-01-26
// DEL: 0014873: [Vibrator] Pwm off sequence.
// gpio_tlmm_config(GPIO_CFG(GPIO_LIN_MOTOR_PWM, 2, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), GPIO_CFG_ENABLE);
// END : [email protected] 2011-01-26
/* [email protected] 2010.09.17 end */
/* [email protected] E 2010.09.06 */
if (enable) {
// BEGIN : [email protected] 2011-01-26
// ADD: 0014873: [Vibrator] Pwm off sequence.
gpio_tlmm_config(GPIO_CFG(GPIO_LIN_MOTOR_PWM, 2, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), GPIO_CFG_ENABLE);
// END : [email protected] 2011-01-26
REG_WRITEL((gain & GPMN_D_MASK), GP_MN_CLK_DUTY_REG);
gpio_direction_output(GPIO_LIN_MOTOR_PWM, 1);
// BEGIN : [email protected] 2011-02-01
// MOD: 0015191: [Vibrator] Vibrator irregular fix
vib_on=1;
// END : [email protected] 2011-02-01
} else {
REG_WRITEL(GPMN_D_DEFAULT, GP_MN_CLK_DUTY_REG);
// BEGIN : [email protected] 2011-01-26
// MOD: 0014873: [Vibrator] Pwm off sequence.
gpio_tlmm_config(GPIO_CFG(GPIO_LIN_MOTOR_PWM, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), GPIO_CFG_ENABLE);
// gpio_direction_output(GPIO_LIN_MOTOR_PWM, 0);
// END : [email protected] 2011-01-26
// BEGIN : [email protected] 2011-02-01
// MOD: 0015191: [Vibrator] Vibrator irregular fix
vib_on=0;
// END : [email protected] 2011-02-01
}
// printk("[vibrator] GPIO_LIN_MOTOR_PWM gpio value :%d \n", gpio_get_value(GPIO_LIN_MOTOR_PWM));
return 0;
}
static int vibrator_pwm_set(int enable, int amp)
{
uint M_VAL = GP1_M_DEFAULT;
uint N_VAL = GP1_N_DEFAULT;
uint D_VAL = GP1_D_DEFAULT;
printk(KERN_INFO "LGE: %s amp=%d\n", __func__, amp);
if (enable) {
// D_VAL = ((PWM_MAX_HALF_DUTY*amp) >> 7)+ GP1_D_DEFAULT;
D_VAL = amp;
REG_WRITEL(
(((M_VAL & 0xffU) <<16U) + /* M_VAL[23:16] */
((~(D_VAL<<1)) & 0xffU)), /* D_VAL[7:0] */
GP1_MD_REG);
REG_WRITEL(
((((~(N_VAL-M_VAL))& 0xffU) <<16U) + /* N_VAL[23:16] */
(1U<<11U) + /* CLK_ROOT_ENA[11] : Enable(1) */
(0U<<10U) + /* CLK_INV[10] : Disable(0) */
(1U<<9U) + /* CLK_BRANCH_ENA[9] : Enable(1) */
(1U<<8U) + /* NMCNTR_EN[8] : Enable(1) */
(0U<<7U) + /* MNCNTR_RST[7] : Not Active(0) */
(2U<<5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */
(3U<<3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */
(0U<<0U)), /* SRC_SEL[2:0] : pxo (0) */
GP1_NS_REG);
printk("[LGE:vibrator] GPIO_LIN_MOTOR_PWM is enable with M=%d N=%d D=%d\n", M_VAL, N_VAL, D_VAL);
} else {
REG_WRITEL(
(((M_VAL & 0xffU) <<16U) + /* M_VAL[23:16] */
((~(D_VAL<<1)) & 0xffU)), /* D_VAL[7:0] */
GP1_MD_REG);
REG_WRITEL(
((((~(N_VAL-M_VAL))& 0xffU) <<16U) + /* N_VAL[23:16] */
(0U<<11U) + /* CLK_ROOT_ENA[11] : Disable(0) */
(0U<<10U) + /* CLK_INV[10] : Disable(0) */
(0U<<9U) + /* CLK_BRANCH_ENA[9] : Disable(0) */
(0U<<8U) + /* NMCNTR_EN[8] : Disable(0) */
(0U<<7U) + /* MNCNTR_RST[7] : Not Active(0) */
(2U<<5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */
(3U<<3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */
(0U<<0U)), /* SRC_SEL[2:0] : pxo (0) */
GP1_NS_REG);
printk("[LGE:vibrator] GPIO_LIN_MOTOR_PWM is disalbe \n");
}
return 0;
}
int thunderg_vibrator_pwm_set(int enable, int amp)
{
int gain = ((PWM_MAX_HALF_DUTY*amp) >> 7)+ GPMN_D_DEFAULT;
REG_WRITEL((GPMN_M_DEFAULT & GPMN_M_MASK), GP_MN_CLK_MDIV_REG);
REG_WRITEL((~( GPMN_N_DEFAULT - GPMN_M_DEFAULT )&GPMN_N_MASK), GP_MN_CLK_NDIV_REG);
if (enable) {
REG_WRITEL((gain & GPMN_D_MASK), GP_MN_CLK_DUTY_REG);
gpio_direction_output(GPIO_LIN_MOTOR_PWM, 1);
} else {
REG_WRITEL(GPMN_D_DEFAULT, GP_MN_CLK_DUTY_REG);
gpio_direction_output(GPIO_LIN_MOTOR_PWM, 0);
}
return 0;
}
int thunderc_vibrator_pwm_set(int enable, int amp)
{
int gain = ((PWM_MAX_HALF_DUTY*amp) >> 7)+ GPMN_D_DEFAULT;
REG_WRITEL((GPMN_M_DEFAULT & GPMN_M_MASK), GP_MN_CLK_MDIV_REG);
REG_WRITEL((~( GPMN_N_DEFAULT - GPMN_M_DEFAULT )&GPMN_N_MASK), GP_MN_CLK_NDIV_REG);
if (enable) {
REG_WRITEL((gain & GPMN_D_MASK), GP_MN_CLK_DUTY_REG);
gpio_tlmm_config(GPIO_CFG(GPIO_LIN_MOTOR_PWM, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_2MA), GPIO_ENABLE);
gpio_direction_output(GPIO_LIN_MOTOR_PWM, 1);
} else {
REG_WRITEL(GPMN_D_DEFAULT, GP_MN_CLK_DUTY_REG);
gpio_tlmm_config(GPIO_CFG(GPIO_LIN_MOTOR_PWM, 1, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), GPIO_ENABLE);
gpio_direction_output(GPIO_LIN_MOTOR_PWM, 0);
}
return 0;
}
int alessi_vibrator_pwn_set(int enable, int amp)
{
int gain = ((PWM_MULTIPLIER * amp) >> 7) + GPMN_D_DEFAULT;
REG_WRITEL((gain & GPMN_D_MASK), GP_MN_CLK_DUTY);
return 0;
}
static int irrc_pwm_set(int enable,int PWM_CLK, int duty)
{
int M_VAL=1;
int N_VAL=1;
int D_VAL=1;
//pwm_clk khz = 19.2 Mhz * M_VAL / Predive *N_VAL
//N_VAL = floor(19200*M_VAL/PWM_CLK*4);
N_VAL = (9600+PWM_CLK)/(PWM_CLK*2);
D_VAL = (N_VAL*duty+50)/100;
if (D_VAL==0)
D_VAL=1;
printk(KERN_INFO "enable = %d ,M_VAL = %d, N_VAL = %d , D_VAL = %d\n",enable,M_VAL,N_VAL,D_VAL);
msm_xo_mode_vote(irrc_clock, MSM_XO_MODE_ON);
//PWM frequency setting
REG_WRITEL(
(((M_VAL & 0xffU) << 16U) + /* M_VAL[23:16] */
((~(D_VAL << 1)) & 0xffU)), /* D_VAL[7:0] */
GPn_MD_REG(GP_CLK_ID));
/* TODO: set clk for amp */
if (enable) {
////GP_CLK ON
////GP_CLK source 32khz select , predive Div -1 select
REG_WRITEL(
((((~(N_VAL-M_VAL)) & 0xffU) << 16U) + /* N_VAL[23:16] */
(0U << 11U) + /* CLK_ROOT_ENA[11] : Disable(0) */
(0U << 10U) + /* CLK_INV[10] : Disable(0) */
(0U << 9U) + /* CLK_BRANCH_ENA[9] : Disable(0) */
(0U << 8U) + /* NMCNTR_EN[8] : Disable(0) */
(1U << 7U) + /* MNCNTR_RST[7] : Not Active(0) */
(2U << 5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */
(3U << 3U) + /* PRE_DIV_SEL[4:3] : Div-4(3) */
(5U << 0U)), /* SRC_SEL[2:0] : CXO (5) */
GPn_NS_REG(GP_CLK_ID));
REG_WRITEL(
((((~(N_VAL-M_VAL)) & 0xffU) << 16U) + /* N_VAL[23:16] */
(1U << 11U) + /* CLK_ROOT_ENA[11] : Enable(1) */
(0U << 10U) + /* CLK_INV[10] : Disable(0) */
(1U << 9U) + /* CLK_BRANCH_ENA[9] : Enable(1) */
(1U << 8U) + /* NMCNTR_EN[8] : Enable(1) */
(0U << 7U) + /* MNCNTR_RST[7] : Not Active(0) */
(2U << 5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */
(3U << 3U) + /* PRE_DIV_SEL[4:3] : Div-4(3) */
(5U << 0U)), /* SRC_SEL[2:0] : CXO (5) */
GPn_NS_REG(GP_CLK_ID));
} else {
////GP_CLK OFF
REG_WRITEL(
((((~(N_VAL-M_VAL)) & 0xffU) << 16U) + /* N_VAL[23:16] */
(0U << 11U) + /* CLK_ROOT_ENA[11] : Disable(0) */
(0U << 10U) + /* CLK_INV[10] : Disable(0) */
(0U << 9U) + /* CLK_BRANCH_ENA[9] : Disable(0) */
(0U << 8U) + /* NMCNTR_EN[8] : Disable(0) */
(1U << 7U) + /* MNCNTR_RST[7] : Not Active(0) */
(2U << 5U) + /* MNCNTR_MODE[6:5] : Dual-edge mode(2) */
(3U << 3U) + /* PRE_DIV_SEL[4:3] : Div-4 (3) */
(5U << 0U)), /* SRC_SEL[2:0] : CXO (5) */
GPn_NS_REG(GP_CLK_ID));
}
return 0;
}